[PATCH] D41895: [X86] Another attempt at support prefer-vector-width function attribute
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 13:39:48 PST 2018
RKSimon added inline comments.
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Comment at: lib/Target/X86/X86ISelLowering.cpp:16580
+ } else {
+ return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
+ }
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Is this right? It isn't the default option for AVX512 anymore.
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Comment at: lib/Target/X86/X86ISelLowering.cpp:18558
+ Hi = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, Hi);
+ SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v16i16, Lo, Hi);
+ return DAG.getNode(ISD::TRUNCATE, dl, VT, Res);
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We have enough of these that we probbaly need a helper function, we already have similar for unary/binary int-256 cases on AVX1.
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Comment at: lib/Target/X86/X86Subtarget.cpp:260
+ if (PreferVectorWidthOverride)
+ PreferVectorWidth = PreferVectorWidthOverride;
+ else if (Prefer256Bit)
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Do we need to assert for a sane value here (else in X86TargetMachine.cpp)?
https://reviews.llvm.org/D41895
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