[PATCH] D42033: [RISCV] Initial Machine Scheduler

[Leslie Zhai via Phabricator via llvm-commits]

xiangzhai created this revision.
xiangzhai added reviewers: asb, javed.absar.
Herald added subscribers: niosHD, sabuasal, apazos, jordy.potman.lists, simoncook, johnrusso, rbar.

Hi LLVM developers,

Motivation:

I am reviewing Compiler Principle about ILP <https://en.wikipedia.org/wiki/Instruction-level_parallelism> and learning Slides <http://lists.llvm.org/pipermail/llvm-dev/2018-January/120356.html> about Machine Scheduler.

So I just initial Machine scheduling model <https://github.com/lowRISC/riscv-llvm/issues/27> for RISCV Target, but I have no idea where to find scheduling information derived from "Which RV32 or RV64 Technical Reference Manual".

And Rocket - RV64G - "in-order", single-issue applicaEon core, BOOM - RV64G  - "out-of-order", superscalar applicaEon core https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-Workshop-3-BOOM.pdf  what about PULP? is it in-order or out-of-order?

Please give me some directions, thanks a lot!

PS: I will rebase this patch based on https://reviews.llvm.org/D41700 and https://reviews.llvm.org/D41653 for porting GlobalISel to RISCV Target.

Regards,
Leslie Zhai


Repository:
  rL LLVM

https://reviews.llvm.org/D42033

Files:
  lib/Target/RISCV/RISCV.td
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVSchedule.td
  lib/Target/RISCV/RISCVScheduleGRV32.td
  lib/Target/RISCV/RISCVSubtarget.cpp
  lib/Target/RISCV/RISCVSubtarget.h
  lib/Target/RISCV/RISCVTargetMachine.cpp

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