[PATCH] D41766: [MachineCombiner] Add check for optimal pattern order.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

TBH I was hoping for a more complete approach to testing this, but I thought I share this relatively straight forward check.

I've run the LLVM test suite with this patch (without the EXPENSIVE_CHECKS guard) on AArch64 with `-O3 -ffast-math` and various mcpu options. I also run the patch on a single X86 machine with -mcpu=native. Beyond that, I did not run this patch on any other targets (except all LLVM unit tests with this change)



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Comment at: test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir:29-30
 # PROFITABLE-LABEL: name: f1_2s
-# PROFITABLE: %5:fpr64 = FNEGv2f32 %2
-# PROFITABLE-NEXT: FMLAv2f32 killed %5, %0, %1
+# PROFITABLE: [[R1:%[0-9]+]]:fpr64 = FNEGv2f32 %2
+# PROFITABLE-NEXT: FMLAv2f32 killed [[R1]], %0, %1
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mssimpso wrote:
> These tests don't need changing because of this patch, right? But you can go ahead and commit the test changes separately if you need to.
Unfortunately they do. Some patterns, at least on AArch64 add additional virtual registers when the pattern is instantiated. Unused virtual registers should be dropped by later passes, but they change the numbers of the registers in this test case.


https://reviews.llvm.org/D41766