[PATCH] D41862: [COST]Fix PR35865: Fix cost model evaluation for shuffle on X86.
Alexey Bataev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 9 07:08:01 PST 2018
ABataev created this revision.
ABataev added reviewers: RKSimon, spatel, mkuper, hfinkel.
If the vector type is transformed to non-vector single type, the compile
may crash trying to get vector information about non-vector type.
https://reviews.llvm.org/D41862
Files:
lib/Target/X86/X86TargetTransformInfo.cpp
test/Transforms/SLPVectorizer/X86/crash_shuffle.ll
Index: test/Transforms/SLPVectorizer/X86/crash_shuffle.ll
===================================================================
--- /dev/null
+++ test/Transforms/SLPVectorizer/X86/crash_shuffle.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -slp-vectorizer < %s -S -o - -mtriple=x86_64-apple-macosx10.10.0 -mcpu=core2 | FileCheck %s
+
+define void @_Z10fooConvertPDv4_xS0_S0_PKS_() {
+; CHECK-LABEL: @_Z10fooConvertPDv4_xS0_S0_PKS_(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = extractelement <16 x half> undef, i32 4
+; CHECK-NEXT: [[CONV_I_4_I:%.*]] = fpext half [[TMP0]] to float
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[CONV_I_4_I]] to i32
+; CHECK-NEXT: [[VECINS_I_4_I:%.*]] = insertelement <8 x i32> undef, i32 [[TMP1]], i32 4
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x half> undef, i32 5
+; CHECK-NEXT: [[CONV_I_5_I:%.*]] = fpext half [[TMP2]] to float
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[CONV_I_5_I]] to i32
+; CHECK-NEXT: [[VECINS_I_5_I:%.*]] = insertelement <8 x i32> [[VECINS_I_4_I]], i32 [[TMP3]], i32 5
+; CHECK-NEXT: ret void
+;
+entry:
+ %0 = extractelement <16 x half> undef, i32 4
+ %conv.i.4.i = fpext half %0 to float
+ %1 = bitcast float %conv.i.4.i to i32
+ %vecins.i.4.i = insertelement <8 x i32> undef, i32 %1, i32 4
+ %2 = extractelement <16 x half> undef, i32 5
+ %conv.i.5.i = fpext half %2 to float
+ %3 = bitcast float %conv.i.5.i to i32
+ %vecins.i.5.i = insertelement <8 x i32> %vecins.i.4.i, i32 %3, i32 5
+ ret void
+}
Index: lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- lib/Target/X86/X86TargetTransformInfo.cpp
+++ lib/Target/X86/X86TargetTransformInfo.cpp
@@ -754,7 +754,8 @@
// type remains the same.
if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
MVT LegalVT = LT.second;
- if (LegalVT.getVectorElementType().getSizeInBits() ==
+ if (LegalVT.isVector() &&
+ LegalVT.getVectorElementType().getSizeInBits() ==
Tp->getVectorElementType()->getPrimitiveSizeInBits() &&
LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) {
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D41862.129077.patch
Type: text/x-patch
Size: 2216 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180109/0851bef5/attachment.bin>
More information about the llvm-commits
mailing list