[PATCH] D41443: [AArch64][SVE] Asm: Add predicated ADD/SUB instructions

[Florian Hahn via Phabricator via llvm-commits]

fhahn accepted this revision.
fhahn added a comment.
This revision is now accepted and ready to land.

Thanks Sander, LGTM



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Comment at: lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp:95
+static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst,
+                                              unsigned RegNo, uint64_t Address,
+                                              const void *Decode);
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Looks like RegNo now could fit on the previous line ;-)


https://reviews.llvm.org/D41443