[PATCH] D41443: [AArch64][SVE] Asm: Add predicated ADD/SUB instructions

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen marked 2 inline comments as done.
sdesmalen added inline comments.


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Comment at: lib/Target/AArch64/AArch64SVEInstrInfo.td:18
 
+  defm ADD_ZPmZ  : sve_int_bin_pred_arit_0<0b000, "add">;
+  defm SUB_ZPmZ  : sve_int_bin_pred_arit_0<0b001, "sub">;
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fhahn wrote:
> It takes 4 registers, shouldn't the name be `ADD_ZPmZZ`? Same below
This is done to distinguish it from cases where the first input register is not tied with the destination register, but also takes 4 registers, e.g. 'FMLA_ZPmZZ'.


https://reviews.llvm.org/D41443