[llvm] r321692 - Thread MCSubtargetInfo through Target::createMCAsmBackend
Daniel Jasper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 3 01:32:43 PST 2018
Ah, just saw r321696. Thank you!
On Wed, Jan 3, 2018 at 10:14 AM, Daniel Jasper <djasper at google.com> wrote:
> Hi Alex,
>
> I see you already fixed cc1as. Can you also fix the WebAssembly backend?
> The call is in: lib/Target/WebAssembly/MCTargetDesc/
> WebAssemblyMCTargetDesc.cpp:119
>
> Thanks,
> Daniel
>
> On Wed, Jan 3, 2018 at 9:53 AM, Alex Bradbury via llvm-commits <
> llvm-commits at lists.llvm.org> wrote:
>
>> Author: asb
>> Date: Wed Jan 3 00:53:05 2018
>> New Revision: 321692
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=321692&view=rev
>> Log:
>> Thread MCSubtargetInfo through Target::createMCAsmBackend
>>
>> Currently it's not possible to access MCSubtargetInfo from a
>> TgtMCAsmBackend.
>> D20830 threaded an MCSubtargetInfo reference through
>> MCAsmBackend::relaxInstruction, but this isn't the only function that
>> would
>> benefit from access. This patch removes the Triple and CPUString arguments
>> from createMCAsmBackend and replaces them with MCSubtargetInfo.
>>
>> This patch just changes the interface without making any intentional
>> functional changes. Once in, several cleanups are possible:
>> * Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend
>> * Support 16-bit instructions when valid in MipsAsmBackend::writeNopData
>> * Get rid of the CPU string parsing in X86AsmBackend and just use a
>> SubtargetFeature for HasNopl
>> * Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed
>> instruction set extension is enabled (see D41221)
>>
>> This change initially exposed PR35686, which has since been resolved in
>> r321026.
>>
>> Differential Revision: https://reviews.llvm.org/D41349
>>
>> Modified:
>> llvm/trunk/include/llvm/Support/TargetRegistry.h
>> llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
>> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
>> llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
>> llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
>> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
>> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
>> llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
>> llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
>> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
>> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
>> llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
>> llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h
>> llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
>> llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
>> llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
>> llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
>> llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
>> llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
>> llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
>> llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
>> llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
>> llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
>> llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
>> llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
>> llvm/trunk/tools/dsymutil/DwarfLinker.cpp
>> llvm/trunk/tools/llvm-dwp/llvm-dwp.cpp
>> llvm/trunk/tools/llvm-mc/llvm-mc.cpp
>> llvm/trunk/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
>>
>> Modified: llvm/trunk/include/llvm/Support/TargetRegistry.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/
>> Support/TargetRegistry.h?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/include/llvm/Support/TargetRegistry.h (original)
>> +++ llvm/trunk/include/llvm/Support/TargetRegistry.h Wed Jan 3 00:53:05
>> 2018
>> @@ -123,8 +123,8 @@ public:
>> using AsmPrinterCtorTy = AsmPrinter *(*)(
>> TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
>> using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T,
>> + const MCSubtargetInfo
>> &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT,
>> StringRef CPU,
>> const MCTargetOptions
>> &Options);
>> using MCAsmParserCtorTy = MCTargetAsmParser *(*)(
>> const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
>> @@ -383,13 +383,12 @@ public:
>> /// createMCAsmBackend - Create a target specific assembly parser.
>> ///
>> /// \param TheTriple The target triple string.
>> - MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
>> - StringRef TheTriple, StringRef CPU,
>> - const MCTargetOptions &Options)
>> - const {
>> + MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> + const MCTargetOptions &Options) const
>> {
>> if (!MCAsmBackendCtorFn)
>> return nullptr;
>> - return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU,
>> Options);
>> + return MCAsmBackendCtorFn(*this, STI, MRI, Options);
>> }
>>
>> /// createMCAsmParser - Create a target specific assembly parser.
>> @@ -1106,10 +1105,10 @@ template <class MCAsmBackendImpl> struct
>> }
>>
>> private:
>> - static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo
>> &MRI,
>> - const Triple &TheTriple, StringRef CPU,
>> + static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo
>> &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options) {
>> - return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);
>> + return new MCAsmBackendImpl(T, STI, MRI);
>> }
>> };
>>
>>
>> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/
>> LLVMTargetMachine.cpp?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Jan 3 00:53:05 2018
>> @@ -136,8 +136,7 @@ bool LLVMTargetMachine::addAsmPrinter(Pa
>> MCE = getTarget().createMCCodeEmitter(MII, MRI, Context);
>>
>> MCAsmBackend *MAB =
>> - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(),
>> TargetCPU,
>> - Options.MCOptions);
>> + getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
>> auto FOut = llvm::make_unique<formatted_raw_ostream>(Out);
>> MCStreamer *S = getTarget().createAsmStreamer(
>> Context, std::move(FOut), Options.MCOptions.AsmVerbose,
>> @@ -151,8 +150,7 @@ bool LLVMTargetMachine::addAsmPrinter(Pa
>> // emission fails.
>> MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI,
>> Context);
>> MCAsmBackend *MAB =
>> - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(),
>> TargetCPU,
>> - Options.MCOptions);
>> + getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
>> if (!MCE || !MAB)
>> return true;
>>
>> @@ -225,17 +223,16 @@ bool LLVMTargetMachine::addPassesToEmitM
>>
>> // Create the code emitter for the target if it exists. If not, .o
>> file
>> // emission fails.
>> + const MCSubtargetInfo &STI = *getMCSubtargetInfo();
>> const MCRegisterInfo &MRI = *getMCRegisterInfo();
>> MCCodeEmitter *MCE =
>> getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
>> MCAsmBackend *MAB =
>> - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(),
>> TargetCPU,
>> - Options.MCOptions);
>> + getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
>> if (!MCE || !MAB)
>> return true;
>>
>> const Triple &T = getTargetTriple();
>> - const MCSubtargetInfo &STI = *getMCSubtargetInfo();
>> std::unique_ptr<MCStreamer> AsmStreamer(getTarget().create
>> MCObjectStreamer(
>> T, *Ctx, std::unique_ptr<MCAsmBackend>(MAB), Out,
>> std::unique_ptr<MCCodeEmitter>(MCE), STI,
>> Options.MCOptions.MCRelaxAll,
>>
>> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend
>> .cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AA
>> rch64/MCTargetDesc/AArch64AsmBackend.cpp?rev=321692&r1=
>> 321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp Wed
>> Jan 3 00:53:05 2018
>> @@ -605,10 +605,10 @@ public:
>> }
>>
>> MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TheTriple,
>> - StringRef CPU,
>> const MCTargetOptions
>> &Options) {
>> + const Triple &TheTriple = STI.getTargetTriple();
>> if (TheTriple.isOSBinFormatMachO())
>> return new DarwinAArch64AsmBackend(T, TheTriple, MRI);
>>
>> @@ -624,10 +624,10 @@ MCAsmBackend *llvm::createAArch64leAsmBa
>> }
>>
>> MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TheTriple,
>> - StringRef CPU,
>> const MCTargetOptions
>> &Options) {
>> + const Triple &TheTriple = STI.getTargetTriple();
>> assert(TheTriple.isOSBinFormatELF() &&
>> "Big endian is only supported for ELF targets!");
>> uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
>>
>> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDe
>> sc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AA
>> rch64/MCTargetDesc/AArch64MCTargetDesc.h?rev=321692&r1=
>> 321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
>> (original)
>> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h Wed
>> Jan 3 00:53:05 2018
>> @@ -45,12 +45,12 @@ MCCodeEmitter *createAArch64MCCodeEmitte
>> const MCRegisterInfo &MRI,
>> MCContext &Ctx);
>> MCAsmBackend *createAArch64leAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> const MCTargetOptions &Options);
>> MCAsmBackend *createAArch64beAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> const MCTargetOptions &Options);
>>
>> std::unique_ptr<MCObjectWriter>
>>
>> Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AM
>> DGPU/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=321692&r1=321691&
>> r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp Wed
>> Jan 3 00:53:05 2018
>> @@ -198,9 +198,9 @@ public:
>> } // end anonymous namespace
>>
>> MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef
>> CPU,
>> const MCTargetOptions
>> &Options) {
>> // Use 64-bit ELF for amdgcn
>> - return new ELFAMDGPUAsmBackend(T, TT);
>> + return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple());
>> }
>>
>> Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AM
>> DGPU/MCTargetDesc/AMDGPUMCTargetDesc.h?rev=321692&r1=321691&
>> r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
>> (original)
>> +++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h Wed
>> Jan 3 00:53:05 2018
>> @@ -45,8 +45,9 @@ MCCodeEmitter *createSIMCCodeEmitter(con
>> const MCRegisterInfo &MRI,
>> MCContext &Ctx);
>>
>> -MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const
>> MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>>
>> std::unique_ptr<MCObjectWriter>
>>
>> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AR
>> M/MCTargetDesc/ARMAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed Jan 3
>> 00:53:05 2018
>> @@ -1176,29 +1176,33 @@ MCAsmBackend *llvm::createARMAsmBackend(
>> }
>>
>> MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef
>> CPU,
>> const MCTargetOptions
>> &Options) {
>> - return createARMAsmBackend(T, MRI, TT, CPU, Options, true);
>> + return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
>> + Options, true);
>> }
>>
>> MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef
>> CPU,
>> const MCTargetOptions
>> &Options) {
>> - return createARMAsmBackend(T, MRI, TT, CPU, Options, false);
>> + return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
>> + Options, false);
>> }
>>
>> MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef
>> CPU,
>> const MCTargetOptions
>> &Options) {
>> - return createARMAsmBackend(T, MRI, TT, CPU, Options, true);
>> + return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
>> + Options, true);
>> }
>>
>> MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef
>> CPU,
>> const MCTargetOptions
>> &Options) {
>> - return createARMAsmBackend(T, MRI, TT, CPU, Options, false);
>> + return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
>> + Options, false);
>> }
>>
>> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AR
>> M/MCTargetDesc/ARMMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original)
>> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Wed Jan 3
>> 00:53:05 2018
>> @@ -73,22 +73,22 @@ MCAsmBackend *createARMAsmBackend(const
>> const MCTargetOptions &Options,
>> bool IsLittleEndian);
>>
>> -MCAsmBackend *createARMLEAsmBackend(const Target &T, const
>> MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createARMLEAsmBackend(const Target &T, const
>> MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>>
>> -MCAsmBackend *createARMBEAsmBackend(const Target &T, const
>> MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createARMBEAsmBackend(const Target &T, const
>> MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>>
>> MCAsmBackend *createThumbLEAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> const MCTargetOptions &Options);
>>
>> MCAsmBackend *createThumbBEAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> const MCTargetOptions &Options);
>>
>> // Construct a PE/COFF machine code streamer which will generate a
>> PE/COFF
>>
>> Modified: llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BP
>> F/MCTargetDesc/BPFAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp (original)
>> +++ llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp Wed Jan 3
>> 00:53:05 2018
>> @@ -104,15 +104,15 @@ BPFAsmBackend::createObjectWriter(raw_pw
>> }
>>
>> MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> - const MCTargetOptions&) {
>> + const MCTargetOptions &) {
>> return new BPFAsmBackend(/*IsLittleEndian=*/true);
>> }
>>
>> MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef
>> CPU,
>> - const MCTargetOptions&) {
>> + const MCTargetOptions &) {
>> return new BPFAsmBackend(/*IsLittleEndian=*/false);
>> }
>>
>> Modified: llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BP
>> F/MCTargetDesc/BPFMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h (original)
>> +++ llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h Wed Jan 3
>> 00:53:05 2018
>> @@ -45,11 +45,11 @@ MCCodeEmitter *createBPFbeMCCodeEmitter(
>> const MCRegisterInfo &MRI,
>> MCContext &Ctx);
>>
>> -MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo
>> &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createBPFAsmBackend(const Target &T, const MCSubtargetInfo
>> &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>> -MCAsmBackend *createBPFbeAsmBackend(const Target &T, const
>> MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createBPFbeAsmBackend(const Target &T, const
>> MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>>
>> std::unique_ptr<MCObjectWriter> createBPFELFObjectWriter(raw_pwrite_stream
>> &OS,
>>
>> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend
>> .cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/He
>> xagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=321692&r1=
>> 321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp Wed
>> Jan 3 00:53:05 2018
>> @@ -765,11 +765,12 @@ public:
>>
>> // MCAsmBackend
>> MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
>> - MCRegisterInfo const & /*MRI*/,
>> - const Triple &TT, StringRef CPU,
>> - const MCTargetOptions &Options) {
>> + const MCSubtargetInfo &STI,
>> + MCRegisterInfo const &
>> /*MRI*/,
>> + const MCTargetOptions
>> &Options) {
>> + const Triple &TT = STI.getTargetTriple();
>> uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
>>
>> - StringRef CPUString = Hexagon_MC::selectHexagonCPU(CPU);
>> + StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU());
>> return new HexagonAsmBackend(T, TT, OSABI, CPUString);
>> }
>>
>> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDe
>> sc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/He
>> xagon/MCTargetDesc/HexagonMCTargetDesc.h?rev=321692&r1=
>> 321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
>> (original)
>> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h Wed
>> Jan 3 00:53:05 2018
>> @@ -61,8 +61,8 @@ MCCodeEmitter *createHexagonMCCodeEmitte
>> MCContext &MCT);
>>
>> MCAsmBackend *createHexagonAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> const MCTargetOptions &Options);
>>
>> std::unique_ptr<MCObjectWriter>
>>
>> Modified: llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/La
>> nai/MCTargetDesc/LanaiAsmBackend.cpp?rev=321692&r1=321691&
>> r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp Wed
>> Jan 3 00:53:05 2018
>> @@ -165,9 +165,10 @@ LanaiAsmBackend::getFixupKindInfo(MCFixu
>> } // namespace
>>
>> MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo & /*MRI*/,
>> - const Triple &TT, StringRef
>> /*CPU*/,
>> const MCTargetOptions &
>> /*Options*/) {
>> + const Triple &TT = STI.getTargetTriple();
>> if (!TT.isOSBinFormatELF())
>> llvm_unreachable("OS not supported");
>>
>>
>> Modified: llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/La
>> nai/MCTargetDesc/LanaiMCTargetDesc.h?rev=321692&r1=321691&
>> r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h
>> (original)
>> +++ llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h Wed
>> Jan 3 00:53:05 2018
>> @@ -38,8 +38,8 @@ MCCodeEmitter *createLanaiMCCodeEmitter(
>> const MCRegisterInfo &MRI,
>> MCContext &Ctx);
>>
>> -MCAsmBackend *createLanaiAsmBackend(const Target &T, const
>> MCRegisterInfo &MRI,
>> - const Triple &TheTriple, StringRef
>> CPU,
>> +MCAsmBackend *createLanaiAsmBackend(const Target &T, const
>> MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>>
>> std::unique_ptr<MCObjectWriter>
>>
>> Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mi
>> ps/MCTargetDesc/MipsAsmBackend.cpp?rev=321692&r1=321691&r2=
>> 321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Wed Jan
>> 3 00:53:05 2018
>> @@ -476,8 +476,9 @@ bool MipsAsmBackend::writeNopData(uint64
>> }
>>
>> MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> const MCTargetOptions &Options)
>> {
>> - return new MipsAsmBackend(T, MRI, TT, CPU, Options.ABIName == "n32");
>> + return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
>> + Options.ABIName == "n32");
>> }
>>
>> Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mi
>> ps/MCTargetDesc/MipsMCTargetDesc.h?rev=321692&r1=321691&r2=
>> 321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h (original)
>> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h Wed Jan
>> 3 00:53:05 2018
>> @@ -45,8 +45,8 @@ MCCodeEmitter *createMipsMCCodeEmitterEL
>> const MCRegisterInfo &MRI,
>> MCContext &Ctx);
>>
>> -MCAsmBackend *createMipsAsmBackend(const Target &T, const MCRegisterInfo
>> &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createMipsAsmBackend(const Target &T, const
>> MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>>
>> std::unique_ptr<MCObjectWriter>
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>> werPC/MCTargetDesc/PPCAsmBackend.cpp?rev=321692&r1=321691&
>> r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Wed
>> Jan 3 00:53:05 2018
>> @@ -18,6 +18,7 @@
>> #include "llvm/MC/MCMachObjectWriter.h"
>> #include "llvm/MC/MCObjectWriter.h"
>> #include "llvm/MC/MCSectionMachO.h"
>> +#include "llvm/MC/MCSubtargetInfo.h"
>> #include "llvm/MC/MCSymbolELF.h"
>> #include "llvm/MC/MCValue.h"
>> #include "llvm/Support/ErrorHandling.h"
>> @@ -231,9 +232,10 @@ namespace {
>> } // end anonymous namespace
>>
>> MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> const MCTargetOptions &Options) {
>> + const Triple &TT = STI.getTargetTriple();
>> if (TT.isOSDarwin())
>> return new DarwinPPCAsmBackend(T);
>>
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>> werPC/MCTargetDesc/PPCMCTargetDesc.h?rev=321692&r1=321691&
>> r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
>> (original)
>> +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h Wed
>> Jan 3 00:53:05 2018
>> @@ -29,6 +29,7 @@ class MCContext;
>> class MCInstrInfo;
>> class MCObjectWriter;
>> class MCRegisterInfo;
>> +class MCSubtargetInfo;
>> class MCTargetOptions;
>> class Target;
>> class Triple;
>> @@ -43,8 +44,8 @@ MCCodeEmitter *createPPCMCCodeEmitter(co
>> const MCRegisterInfo &MRI,
>> MCContext &Ctx);
>>
>> -MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo
>> &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo
>> &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>>
>> /// Construct an PPC ELF object writer.
>>
>> Modified: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RI
>> SCV/MCTargetDesc/RISCVAsmBackend.cpp?rev=321692&r1=321691&
>> r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp Wed
>> Jan 3 00:53:05 2018
>> @@ -230,9 +230,10 @@ RISCVAsmBackend::createObjectWriter(raw_
>> } // end anonymous namespace
>>
>> MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef
>> CPU,
>> const MCTargetOptions
>> &Options) {
>> + const Triple &TT = STI.getTargetTriple();
>> uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
>> return new RISCVAsmBackend(OSABI, TT.isArch64Bit());
>> }
>>
>> Modified: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RI
>> SCV/MCTargetDesc/RISCVMCTargetDesc.h?rev=321692&r1=321691&
>> r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
>> (original)
>> +++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h Wed
>> Jan 3 00:53:05 2018
>> @@ -40,8 +40,8 @@ MCCodeEmitter *createRISCVMCCodeEmitter(
>> const MCRegisterInfo &MRI,
>> MCContext &Ctx);
>>
>> -MCAsmBackend *createRISCVAsmBackend(const Target &T, const
>> MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createRISCVAsmBackend(const Target &T, const
>> MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>>
>> std::unique_ptr<MCObjectWriter>
>>
>> Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sp
>> arc/MCTargetDesc/SparcAsmBackend.cpp?rev=321692&r1=321691&
>> r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp Wed
>> Jan 3 00:53:05 2018
>> @@ -14,6 +14,7 @@
>> #include "llvm/MC/MCExpr.h"
>> #include "llvm/MC/MCFixupKindInfo.h"
>> #include "llvm/MC/MCObjectWriter.h"
>> +#include "llvm/MC/MCSubtargetInfo.h"
>> #include "llvm/MC/MCValue.h"
>> #include "llvm/Support/TargetRegistry.h"
>>
>> @@ -301,8 +302,8 @@ namespace {
>> } // end anonymous namespace
>>
>> MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef
>> CPU,
>> const MCTargetOptions
>> &Options) {
>> - return new ELFSparcAsmBackend(T, TT.getOS());
>> + return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS());
>> }
>>
>> Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sp
>> arc/MCTargetDesc/SparcMCTargetDesc.h?rev=321692&r1=321691&
>> r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
>> (original)
>> +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h Wed
>> Jan 3 00:53:05 2018
>> @@ -40,8 +40,8 @@ Target &getTheSparcelTarget();
>> MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
>> const MCRegisterInfo &MRI,
>> MCContext &Ctx);
>> -MCAsmBackend *createSparcAsmBackend(const Target &T, const
>> MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createSparcAsmBackend(const Target &T, const
>> MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>> std::unique_ptr<MCObjectWriter>
>> createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
>>
>> Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBacke
>> nd.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sy
>> stemZ/MCTargetDesc/SystemZMCAsmBackend.cpp?rev=321692&r1=
>> 321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
>> Wed Jan 3 00:53:05 2018
>> @@ -14,6 +14,7 @@
>> #include "llvm/MC/MCFixupKindInfo.h"
>> #include "llvm/MC/MCInst.h"
>> #include "llvm/MC/MCObjectWriter.h"
>> +#include "llvm/MC/MCSubtargetInfo.h"
>>
>> using namespace llvm;
>>
>> @@ -122,9 +123,10 @@ bool SystemZMCAsmBackend::writeNopData(u
>> }
>>
>> MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT,
>> StringRef CPU,
>> const MCTargetOptions
>> &Options) {
>> - uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
>> + uint8_t OSABI =
>> + MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
>> return new SystemZMCAsmBackend(OSABI);
>> }
>>
>> Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDe
>> sc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sy
>> stemZ/MCTargetDesc/SystemZMCTargetDesc.h?rev=321692&r1=
>> 321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
>> (original)
>> +++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h Wed
>> Jan 3 00:53:05 2018
>> @@ -89,8 +89,8 @@ MCCodeEmitter *createSystemZMCCodeEmitte
>> MCContext &Ctx);
>>
>> MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> const MCTargetOptions &Options);
>>
>> std::unique_ptr<MCObjectWriter> createSystemZObjectWriter(raw_pwrite_stream
>> &OS,
>>
>> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X8
>> 6/MCTargetDesc/X86AsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Wed Jan 3
>> 00:53:05 2018
>> @@ -843,10 +843,12 @@ public:
>> } // end anonymous namespace
>>
>> MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TheTriple,
>> - StringRef CPU,
>> const MCTargetOptions
>> &Options) {
>> + const Triple &TheTriple = STI.getTargetTriple();
>> + StringRef CPU = STI.getCPU();
>> + llvm::errs() << "create x86-32 backend with CPU: " << CPU << "\n";
>> if (TheTriple.isOSBinFormatMachO())
>> return new DarwinX86_32AsmBackend(T, MRI, CPU);
>>
>> @@ -862,10 +864,11 @@ MCAsmBackend *llvm::createX86_32AsmBacke
>> }
>>
>> MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> const MCRegisterInfo &MRI,
>> - const Triple &TheTriple,
>> - StringRef CPU,
>> const MCTargetOptions
>> &Options) {
>> + const Triple &TheTriple = STI.getTargetTriple();
>> + StringRef CPU = STI.getCPU();
>> if (TheTriple.isOSBinFormatMachO()) {
>> MachO::CPUSubTypeX86 CS =
>> StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
>>
>> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X8
>> 6/MCTargetDesc/X86MCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original)
>> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Wed Jan 3
>> 00:53:05 2018
>> @@ -70,11 +70,13 @@ MCCodeEmitter *createX86MCCodeEmitter(co
>> const MCRegisterInfo &MRI,
>> MCContext &Ctx);
>>
>> -MCAsmBackend *createX86_32AsmBackend(const Target &T, const
>> MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createX86_32AsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>> -MCAsmBackend *createX86_64AsmBackend(const Target &T, const
>> MCRegisterInfo &MRI,
>> - const Triple &TT, StringRef CPU,
>> +MCAsmBackend *createX86_64AsmBackend(const Target &T,
>> + const MCSubtargetInfo &STI,
>> + const MCRegisterInfo &MRI,
>> const MCTargetOptions &Options);
>>
>> /// Implements X86-only directives for assembly emission.
>>
>> Modified: llvm/trunk/tools/dsymutil/DwarfLinker.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/dsymuti
>> l/DwarfLinker.cpp?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/tools/dsymutil/DwarfLinker.cpp (original)
>> +++ llvm/trunk/tools/dsymutil/DwarfLinker.cpp Wed Jan 3 00:53:05 2018
>> @@ -672,8 +672,12 @@ bool DwarfStreamer::init(Triple TheTripl
>> MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
>> MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, *MC);
>>
>> + MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
>> + if (!MSTI)
>> + return error("no subtarget info for target " + TripleName, Context);
>> +
>> MCTargetOptions Options;
>> - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", Options);
>> + MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, Options);
>> if (!MAB)
>> return error("no asm backend for target " + TripleName, Context);
>>
>> @@ -681,10 +685,6 @@ bool DwarfStreamer::init(Triple TheTripl
>> if (!MII)
>> return error("no instr info info for target " + TripleName, Context);
>>
>> - MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
>> - if (!MSTI)
>> - return error("no subtarget info for target " + TripleName, Context);
>> -
>> MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
>> if (!MCE)
>> return error("no code emitter for target " + TripleName, Context);
>>
>> Modified: llvm/trunk/tools/llvm-dwp/llvm-dwp.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dw
>> p/llvm-dwp.cpp?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/tools/llvm-dwp/llvm-dwp.cpp (original)
>> +++ llvm/trunk/tools/llvm-dwp/llvm-dwp.cpp Wed Jan 3 00:53:05 2018
>> @@ -673,8 +673,13 @@ int main(int argc, char **argv) {
>> MCContext MC(MAI.get(), MRI.get(), &MOFI);
>> MOFI.InitMCObjectFileInfo(TheTriple, /*PIC*/ false, MC);
>>
>> + std::unique_ptr<MCSubtargetInfo> MSTI(
>> + TheTarget->createMCSubtargetInfo(TripleName, "", ""));
>> + if (!MSTI)
>> + return error("no subtarget info for target " + TripleName, Context);
>> +
>> MCTargetOptions Options;
>> - auto MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "",
>> Options);
>> + auto MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, Options);
>> if (!MAB)
>> return error("no asm backend for target " + TripleName, Context);
>>
>> @@ -682,11 +687,6 @@ int main(int argc, char **argv) {
>> if (!MII)
>> return error("no instr info info for target " + TripleName, Context);
>>
>> - std::unique_ptr<MCSubtargetInfo> MSTI(
>> - TheTarget->createMCSubtargetInfo(TripleName, "", ""));
>> - if (!MSTI)
>> - return error("no subtarget info for target " + TripleName, Context);
>> -
>> MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, MC);
>> if (!MCE)
>> return error("no code emitter for target " + TripleName, Context);
>>
>> Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc
>> /llvm-mc.cpp?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
>> +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Jan 3 00:53:05 2018
>> @@ -567,7 +567,7 @@ int main(int argc, char **argv) {
>> MCAsmBackend *MAB = nullptr;
>> if (ShowEncoding) {
>> CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
>> - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU,
>> MCOptions);
>> + MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
>> }
>> auto FOut = llvm::make_unique<formatted_raw_ostream>(*OS);
>> Str.reset(TheTarget->createAsmStreamer(
>> @@ -588,8 +588,7 @@ int main(int argc, char **argv) {
>> }
>>
>> MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI,
>> Ctx);
>> - MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName,
>> MCPU,
>> - MCOptions);
>> + MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI,
>> MCOptions);
>> Str.reset(TheTarget->createMCObjectStreamer(
>> TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB), *OS,
>> std::unique_ptr<MCCodeEmitter>(CE), *STI, MCOptions.MCRelaxAll,
>>
>> Modified: llvm/trunk/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Deb
>> ugInfo/DWARF/DwarfGenerator.cpp?rev=321692&r1=321691&r2=321692&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/unittests/DebugInfo/DWARF/DwarfGenerator.cpp (original)
>> +++ llvm/trunk/unittests/DebugInfo/DWARF/DwarfGenerator.cpp Wed Jan 3
>> 00:53:05 2018
>> @@ -152,8 +152,13 @@ llvm::Error dwarfgen::Generator::init(Tr
>> MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
>> MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, *MC);
>>
>> + MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
>> + if (!MSTI)
>> + return make_error<StringError>("no subtarget info for target " +
>> TripleName,
>> + inconvertibleErrorCode());
>> +
>> MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
>> - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", MCOptions);
>> + MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, MCOptions);
>> if (!MAB)
>> return make_error<StringError>("no asm backend for target " +
>> TripleName,
>> inconvertibleErrorCode());
>> @@ -164,11 +169,6 @@ llvm::Error dwarfgen::Generator::init(Tr
>> TripleName,
>> inconvertibleErrorCode());
>>
>> - MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
>> - if (!MSTI)
>> - return make_error<StringError>("no subtarget info for target " +
>> TripleName,
>> - inconvertibleErrorCode());
>> -
>> MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
>> if (!MCE)
>> return make_error<StringError>("no code emitter for target " +
>> TripleName,
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>>
>
>
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