<div dir="ltr">Ah, just saw r321696. Thank you!</div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jan 3, 2018 at 10:14 AM, Daniel Jasper <span dir="ltr"><<a href="mailto:djasper@google.com" target="_blank">djasper@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi Alex,<div><br></div><div>I see you already fixed cc1as. Can you also fix the WebAssembly backend? The call is in: lib/Target/WebAssembly/<wbr>MCTargetDesc/<wbr>WebAssemblyMCTargetDesc.cpp:<wbr>119</div><div><br></div><div>Thanks,<br>Daniel</div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jan 3, 2018 at 9:53 AM, Alex Bradbury via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: asb<br>
Date: Wed Jan 3 00:53:05 2018<br>
New Revision: 321692<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=321692&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=321692&view=rev</a><br>
Log:<br>
Thread MCSubtargetInfo through Target::createMCAsmBackend<br>
<br>
Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend.<br>
D20830 threaded an MCSubtargetInfo reference through<br>
MCAsmBackend::relaxInstruction<wbr>, but this isn't the only function that would<br>
benefit from access. This patch removes the Triple and CPUString arguments<br>
from createMCAsmBackend and replaces them with MCSubtargetInfo.<br>
<br>
This patch just changes the interface without making any intentional<br>
functional changes. Once in, several cleanups are possible:<br>
* Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend<br>
* Support 16-bit instructions when valid in MipsAsmBackend::writeNopData<br>
* Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl<br>
* Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221)<br>
<br>
This change initially exposed PR35686, which has since been resolved in r321026.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D41349" rel="noreferrer" target="_blank">https://reviews.llvm.org/D4134<wbr>9</a><br>
<br>
Modified:<br>
llvm/trunk/include/llvm/Suppor<wbr>t/TargetRegistry.h<br>
llvm/trunk/lib/CodeGen/LLVMTar<wbr>getMachine.cpp<br>
llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64AsmBackend<wbr>.cpp<br>
llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64MCTargetDe<wbr>sc.h<br>
llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUAsmBackend.c<wbr>pp<br>
llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUMCTargetDesc<wbr>.h<br>
llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.cpp<br>
llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMMCTargetDesc.h<br>
llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFAsmBackend.cpp<br>
llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFMCTargetDesc.h<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCTargetDe<wbr>sc.h<br>
llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiAsmBackend.cpp<br>
llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiMCTargetDesc.h<br>
llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.cpp<br>
llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsMCTargetDesc.h<br>
llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCAsmBackend.cpp<br>
llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCMCTargetDesc.h<br>
llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVAsmBackend.cpp<br>
llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVMCTargetDesc.h<br>
llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcAsmBackend.cpp<br>
llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcMCTargetDesc.h<br>
llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCAsmBacke<wbr>nd.cpp<br>
llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCTargetDe<wbr>sc.h<br>
llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86AsmBackend.cpp<br>
llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86MCTargetDesc.h<br>
llvm/trunk/tools/dsymutil/Dwar<wbr>fLinker.cpp<br>
llvm/trunk/tools/llvm-dwp/llvm<wbr>-dwp.cpp<br>
llvm/trunk/tools/llvm-mc/llvm-<wbr>mc.cpp<br>
llvm/trunk/unittests/DebugInfo<wbr>/DWARF/DwarfGenerator.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/Suppor<wbr>t/TargetRegistry.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetRegistry.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/include/llvm/<wbr>Support/TargetRegistry.h?rev=<wbr>321692&r1=321691&r2=321692&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/Suppor<wbr>t/TargetRegistry.h (original)<br>
+++ llvm/trunk/include/llvm/Suppor<wbr>t/TargetRegistry.h Wed Jan 3 00:53:05 2018<br>
@@ -123,8 +123,8 @@ public:<br>
using AsmPrinterCtorTy = AsmPrinter *(*)(<br>
TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);<br>
using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options);<br>
using MCAsmParserCtorTy = MCTargetAsmParser *(*)(<br>
const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,<br>
@@ -383,13 +383,12 @@ public:<br>
/// createMCAsmBackend - Create a target specific assembly parser.<br>
///<br>
/// \param TheTriple The target triple string.<br>
- MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,<br>
- StringRef TheTriple, StringRef CPU,<br>
- const MCTargetOptions &Options)<br>
- const {<br>
+ MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
+ const MCTargetOptions &Options) const {<br>
if (!MCAsmBackendCtorFn)<br>
return nullptr;<br>
- return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU, Options);<br>
+ return MCAsmBackendCtorFn(*this, STI, MRI, Options);<br>
}<br>
<br>
/// createMCAsmParser - Create a target specific assembly parser.<br>
@@ -1106,10 +1105,10 @@ template <class MCAsmBackendImpl> struct<br>
}<br>
<br>
private:<br>
- static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TheTriple, StringRef CPU,<br>
+ static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options) {<br>
- return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);<br>
+ return new MCAsmBackendImpl(T, STI, MRI);<br>
}<br>
};<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/LLVMTar<wbr>getMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/CodeGen/<wbr>LLVMTargetMachine.cpp?rev=<wbr>321692&r1=321691&r2=321692&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/LLVMTar<wbr>getMachine.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/LLVMTar<wbr>getMachine.cpp Wed Jan 3 00:53:05 2018<br>
@@ -136,8 +136,7 @@ bool LLVMTargetMachine::addAsmPrint<wbr>er(Pa<br>
MCE = getTarget().createMCCodeEmitte<wbr>r(MII, MRI, Context);<br>
<br>
MCAsmBackend *MAB =<br>
- getTarget().createMCAsmBackend<wbr>(MRI, getTargetTriple().str(), TargetCPU,<br>
- Options.MCOptions);<br>
+ getTarget().createMCAsmBackend<wbr>(STI, MRI, Options.MCOptions);<br>
auto FOut = llvm::make_unique<formatted_ra<wbr>w_ostream>(Out);<br>
MCStreamer *S = getTarget().createAsmStreamer(<br>
Context, std::move(FOut), Options.MCOptions.AsmVerbose,<br>
@@ -151,8 +150,7 @@ bool LLVMTargetMachine::addAsmPrint<wbr>er(Pa<br>
// emission fails.<br>
MCCodeEmitter *MCE = getTarget().createMCCodeEmitte<wbr>r(MII, MRI, Context);<br>
MCAsmBackend *MAB =<br>
- getTarget().createMCAsmBackend<wbr>(MRI, getTargetTriple().str(), TargetCPU,<br>
- Options.MCOptions);<br>
+ getTarget().createMCAsmBackend<wbr>(STI, MRI, Options.MCOptions);<br>
if (!MCE || !MAB)<br>
return true;<br>
<br>
@@ -225,17 +223,16 @@ bool LLVMTargetMachine::addPassesTo<wbr>EmitM<br>
<br>
// Create the code emitter for the target if it exists. If not, .o file<br>
// emission fails.<br>
+ const MCSubtargetInfo &STI = *getMCSubtargetInfo();<br>
const MCRegisterInfo &MRI = *getMCRegisterInfo();<br>
MCCodeEmitter *MCE =<br>
getTarget().createMCCodeEmitt<wbr>er(*getMCInstrInfo(), MRI, *Ctx);<br>
MCAsmBackend *MAB =<br>
- getTarget().createMCAsmBackend<wbr>(MRI, getTargetTriple().str(), TargetCPU,<br>
- Options.MCOptions);<br>
+ getTarget().createMCAsmBackend<wbr>(STI, MRI, Options.MCOptions);<br>
if (!MCE || !MAB)<br>
return true;<br>
<br>
const Triple &T = getTargetTriple();<br>
- const MCSubtargetInfo &STI = *getMCSubtargetInfo();<br>
std::unique_ptr<MCStreamer> AsmStreamer(getTarget().create<wbr>MCObjectStreamer(<br>
T, *Ctx, std::unique_ptr<MCAsmBackend>(<wbr>MAB), Out,<br>
std::unique_ptr<<wbr>MCCodeEmitter>(MCE), STI, Options.MCOptions.MCRelaxAll,<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64AsmBackend<wbr>.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AA<wbr>rch64/MCTargetDesc/AArch64AsmB<wbr>ackend.cpp?rev=321692&r1=<wbr>321691&r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64AsmBackend<wbr>.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64AsmBackend<wbr>.cpp Wed Jan 3 00:53:05 2018<br>
@@ -605,10 +605,10 @@ public:<br>
}<br>
<br>
MCAsmBackend *llvm::createAArch64leAsmBacke<wbr>nd(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TheTriple,<br>
- StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
+ const Triple &TheTriple = STI.getTargetTriple();<br>
if (TheTriple.isOSBinFormatMachO(<wbr>))<br>
return new DarwinAArch64AsmBackend(T, TheTriple, MRI);<br>
<br>
@@ -624,10 +624,10 @@ MCAsmBackend *llvm::createAArch64leAsmBa<br>
}<br>
<br>
MCAsmBackend *llvm::createAArch64beAsmBacke<wbr>nd(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TheTriple,<br>
- StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
+ const Triple &TheTriple = STI.getTargetTriple();<br>
assert(TheTriple.isOSBinForma<wbr>tELF() &&<br>
"Big endian is only supported for ELF targets!");<br>
uint8_t OSABI = MCELFObjectTargetWriter::getOS<wbr>ABI(TheTriple.getOS());<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64MCTargetDe<wbr>sc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AA<wbr>rch64/MCTargetDesc/AArch64MCTa<wbr>rgetDesc.h?rev=321692&r1=<wbr>321691&r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64MCTargetDe<wbr>sc.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64MCTargetDe<wbr>sc.h Wed Jan 3 00:53:05 2018<br>
@@ -45,12 +45,12 @@ MCCodeEmitter *createAArch64MCCodeEmitte<br>
const MCRegisterInfo &MRI,<br>
MCContext &Ctx);<br>
MCAsmBackend *createAArch64leAsmBackend(con<wbr>st Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options);<br>
MCAsmBackend *createAArch64beAsmBackend(con<wbr>st Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options);<br>
<br>
std::unique_ptr<MCObjectWrite<wbr>r><br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUAsmBackend.c<wbr>pp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AM<wbr>DGPU/MCTargetDesc/AMDGPUAsmBac<wbr>kend.cpp?rev=321692&r1=321691&<wbr>r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUAsmBackend.c<wbr>pp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUAsmBackend.c<wbr>pp Wed Jan 3 00:53:05 2018<br>
@@ -198,9 +198,9 @@ public:<br>
} // end anonymous namespace<br>
<br>
MCAsmBackend *llvm::createAMDGPUAsmBackend(<wbr>const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
// Use 64-bit ELF for amdgcn<br>
- return new ELFAMDGPUAsmBackend(T, TT);<br>
+ return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple());<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUMCTargetDesc<wbr>.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AM<wbr>DGPU/MCTargetDesc/AMDGPUMCTarg<wbr>etDesc.h?rev=321692&r1=321691&<wbr>r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUMCTargetDesc<wbr>.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUMCTargetDesc<wbr>.h Wed Jan 3 00:53:05 2018<br>
@@ -45,8 +45,9 @@ MCCodeEmitter *createSIMCCodeEmitter(con<br>
const MCRegisterInfo &MRI,<br>
MCContext &Ctx);<br>
<br>
-MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createAMDGPUAsmBackend(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
<br>
std::unique_ptr<MCObjectWrite<wbr>r><br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AR<wbr>M/MCTargetDesc/ARMAsmBackend.<wbr>cpp?rev=321692&r1=321691&r2=<wbr>321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.cpp Wed Jan 3 00:53:05 2018<br>
@@ -1176,29 +1176,33 @@ MCAsmBackend *llvm::createARMAsmBackend(<br>
}<br>
<br>
MCAsmBackend *llvm::createARMLEAsmBackend(c<wbr>onst Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
- return createARMAsmBackend(T, MRI, TT, CPU, Options, true);<br>
+ return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),<br>
+ Options, true);<br>
}<br>
<br>
MCAsmBackend *llvm::createARMBEAsmBackend(c<wbr>onst Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
- return createARMAsmBackend(T, MRI, TT, CPU, Options, false);<br>
+ return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),<br>
+ Options, false);<br>
}<br>
<br>
MCAsmBackend *llvm::createThumbLEAsmBackend<wbr>(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
- return createARMAsmBackend(T, MRI, TT, CPU, Options, true);<br>
+ return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),<br>
+ Options, true);<br>
}<br>
<br>
MCAsmBackend *llvm::createThumbBEAsmBackend<wbr>(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
- return createARMAsmBackend(T, MRI, TT, CPU, Options, false);<br>
+ return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),<br>
+ Options, false);<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMMCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AR<wbr>M/MCTargetDesc/ARMMCTargetDesc<wbr>.h?rev=321692&r1=321691&r2=<wbr>321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMMCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMMCTargetDesc.h Wed Jan 3 00:53:05 2018<br>
@@ -73,22 +73,22 @@ MCAsmBackend *createARMAsmBackend(const<br>
const MCTargetOptions &Options,<br>
bool IsLittleEndian);<br>
<br>
-MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
<br>
-MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
<br>
MCAsmBackend *createThumbLEAsmBackend(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options);<br>
<br>
MCAsmBackend *createThumbBEAsmBackend(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options);<br>
<br>
// Construct a PE/COFF machine code streamer which will generate a PE/COFF<br>
<br>
Modified: llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/BP<wbr>F/MCTargetDesc/BPFAsmBackend.<wbr>cpp?rev=321692&r1=321691&r2=<wbr>321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFAsmBackend.cpp Wed Jan 3 00:53:05 2018<br>
@@ -104,15 +104,15 @@ BPFAsmBackend::createObjectWri<wbr>ter(raw_pw<br>
}<br>
<br>
MCAsmBackend *llvm::createBPFAsmBackend(con<wbr>st Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
- const MCTargetOptions&) {<br>
+ const MCTargetOptions &) {<br>
return new BPFAsmBackend(/*IsLittleEndian<wbr>=*/true);<br>
}<br>
<br>
MCAsmBackend *llvm::createBPFbeAsmBackend(c<wbr>onst Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
- const MCTargetOptions&) {<br>
+ const MCTargetOptions &) {<br>
return new BPFAsmBackend(/*IsLittleEndian<wbr>=*/false);<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFMCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/BP<wbr>F/MCTargetDesc/BPFMCTargetDesc<wbr>.h?rev=321692&r1=321691&r2=<wbr>321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFMCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFMCTargetDesc.h Wed Jan 3 00:53:05 2018<br>
@@ -45,11 +45,11 @@ MCCodeEmitter *createBPFbeMCCodeEmitter(<br>
const MCRegisterInfo &MRI,<br>
MCContext &Ctx);<br>
<br>
-MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
-MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
<br>
std::unique_ptr<MCObjectWrite<wbr>r> createBPFELFObjectWriter(raw_p<wbr>write_stream &OS,<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonAsmB<wbr>ackend.cpp?rev=321692&r1=<wbr>321691&r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp Wed Jan 3 00:53:05 2018<br>
@@ -765,11 +765,12 @@ public:<br>
<br>
// MCAsmBackend<br>
MCAsmBackend *llvm::createHexagonAsmBackend<wbr>(Target const &T,<br>
- MCRegisterInfo const & /*MRI*/,<br>
- const Triple &TT, StringRef CPU,<br>
- const MCTargetOptions &Options) {<br>
+ const MCSubtargetInfo &STI,<br>
+ MCRegisterInfo const & /*MRI*/,<br>
+ const MCTargetOptions &Options) {<br>
+ const Triple &TT = STI.getTargetTriple();<br>
uint8_t OSABI = MCELFObjectTargetWriter::getOS<wbr>ABI(TT.getOS());<br>
<br>
- StringRef CPUString = Hexagon_MC::selectHexagonCPU(C<wbr>PU);<br>
+ StringRef CPUString = Hexagon_MC::selectHexagonCPU(S<wbr>TI.getCPU());<br>
return new HexagonAsmBackend(T, TT, OSABI, CPUString);<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCTargetDe<wbr>sc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonMCTa<wbr>rgetDesc.h?rev=321692&r1=<wbr>321691&r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCTargetDe<wbr>sc.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCTargetDe<wbr>sc.h Wed Jan 3 00:53:05 2018<br>
@@ -61,8 +61,8 @@ MCCodeEmitter *createHexagonMCCodeEmitte<br>
MCContext &MCT);<br>
<br>
MCAsmBackend *createHexagonAsmBackend(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options);<br>
<br>
std::unique_ptr<MCObjectWrite<wbr>r><br>
<br>
Modified: llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/La<wbr>nai/MCTargetDesc/LanaiAsmBacke<wbr>nd.cpp?rev=321692&r1=321691&<wbr>r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiAsmBackend.cpp Wed Jan 3 00:53:05 2018<br>
@@ -165,9 +165,10 @@ LanaiAsmBackend::getFixupKindI<wbr>nfo(MCFixu<br>
} // namespace<br>
<br>
MCAsmBackend *llvm::createLanaiAsmBackend(c<wbr>onst Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo & /*MRI*/,<br>
- const Triple &TT, StringRef /*CPU*/,<br>
const MCTargetOptions & /*Options*/) {<br>
+ const Triple &TT = STI.getTargetTriple();<br>
if (!TT.isOSBinFormatELF())<br>
llvm_unreachable("OS not supported");<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiMCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/La<wbr>nai/MCTargetDesc/LanaiMCTarget<wbr>Desc.h?rev=321692&r1=321691&<wbr>r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiMCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiMCTargetDesc.h Wed Jan 3 00:53:05 2018<br>
@@ -38,8 +38,8 @@ MCCodeEmitter *createLanaiMCCodeEmitter(<br>
const MCRegisterInfo &MRI,<br>
MCContext &Ctx);<br>
<br>
-MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TheTriple, StringRef CPU,<br>
+MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
<br>
std::unique_ptr<MCObjectWrite<wbr>r><br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Mi<wbr>ps/MCTargetDesc/MipsAsmBackend<wbr>.cpp?rev=321692&r1=321691&r2=<wbr>321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.cpp Wed Jan 3 00:53:05 2018<br>
@@ -476,8 +476,9 @@ bool MipsAsmBackend::writeNopData(u<wbr>int64<br>
}<br>
<br>
MCAsmBackend *llvm::createMipsAsmBackend(co<wbr>nst Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
- return new MipsAsmBackend(T, MRI, TT, CPU, Options.ABIName == "n32");<br>
+ return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),<br>
+ Options.ABIName == "n32");<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsMCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Mi<wbr>ps/MCTargetDesc/MipsMCTargetDe<wbr>sc.h?rev=321692&r1=321691&r2=<wbr>321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsMCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsMCTargetDesc.h Wed Jan 3 00:53:05 2018<br>
@@ -45,8 +45,8 @@ MCCodeEmitter *createMipsMCCodeEmitterEL<br>
const MCRegisterInfo &MRI,<br>
MCContext &Ctx);<br>
<br>
-MCAsmBackend *createMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
<br>
std::unique_ptr<MCObjectWrite<wbr>r><br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Po<wbr>werPC/MCTargetDesc/PPCAsmBacke<wbr>nd.cpp?rev=321692&r1=321691&<wbr>r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCAsmBackend.cpp Wed Jan 3 00:53:05 2018<br>
@@ -18,6 +18,7 @@<br>
#include "llvm/MC/MCMachObjectWriter.h"<br>
#include "llvm/MC/MCObjectWriter.h"<br>
#include "llvm/MC/MCSectionMachO.h"<br>
+#include "llvm/MC/MCSubtargetInfo.h"<br>
#include "llvm/MC/MCSymbolELF.h"<br>
#include "llvm/MC/MCValue.h"<br>
#include "llvm/Support/ErrorHandling.h"<br>
@@ -231,9 +232,10 @@ namespace {<br>
} // end anonymous namespace<br>
<br>
MCAsmBackend *llvm::createPPCAsmBackend(con<wbr>st Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
+ const Triple &TT = STI.getTargetTriple();<br>
if (TT.isOSDarwin())<br>
return new DarwinPPCAsmBackend(T);<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCMCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Po<wbr>werPC/MCTargetDesc/PPCMCTarget<wbr>Desc.h?rev=321692&r1=321691&<wbr>r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCMCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCMCTargetDesc.h Wed Jan 3 00:53:05 2018<br>
@@ -29,6 +29,7 @@ class MCContext;<br>
class MCInstrInfo;<br>
class MCObjectWriter;<br>
class MCRegisterInfo;<br>
+class MCSubtargetInfo;<br>
class MCTargetOptions;<br>
class Target;<br>
class Triple;<br>
@@ -43,8 +44,8 @@ MCCodeEmitter *createPPCMCCodeEmitter(co<br>
const MCRegisterInfo &MRI,<br>
MCContext &Ctx);<br>
<br>
-MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
<br>
/// Construct an PPC ELF object writer.<br>
<br>
Modified: llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/RI<wbr>SCV/MCTargetDesc/RISCVAsmBacke<wbr>nd.cpp?rev=321692&r1=321691&<wbr>r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVAsmBackend.cpp Wed Jan 3 00:53:05 2018<br>
@@ -230,9 +230,10 @@ RISCVAsmBackend::createObjectW<wbr>riter(raw_<br>
} // end anonymous namespace<br>
<br>
MCAsmBackend *llvm::createRISCVAsmBackend(c<wbr>onst Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
+ const Triple &TT = STI.getTargetTriple();<br>
uint8_t OSABI = MCELFObjectTargetWriter::getOS<wbr>ABI(TT.getOS());<br>
return new RISCVAsmBackend(OSABI, TT.isArch64Bit());<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVMCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/RI<wbr>SCV/MCTargetDesc/RISCVMCTarget<wbr>Desc.h?rev=321692&r1=321691&<wbr>r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVMCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVMCTargetDesc.h Wed Jan 3 00:53:05 2018<br>
@@ -40,8 +40,8 @@ MCCodeEmitter *createRISCVMCCodeEmitter(<br>
const MCRegisterInfo &MRI,<br>
MCContext &Ctx);<br>
<br>
-MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
<br>
std::unique_ptr<MCObjectWrite<wbr>r><br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Sp<wbr>arc/MCTargetDesc/SparcAsmBacke<wbr>nd.cpp?rev=321692&r1=321691&<wbr>r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcAsmBackend.cpp Wed Jan 3 00:53:05 2018<br>
@@ -14,6 +14,7 @@<br>
#include "llvm/MC/MCExpr.h"<br>
#include "llvm/MC/MCFixupKindInfo.h"<br>
#include "llvm/MC/MCObjectWriter.h"<br>
+#include "llvm/MC/MCSubtargetInfo.h"<br>
#include "llvm/MC/MCValue.h"<br>
#include "llvm/Support/TargetRegistry.h<wbr>"<br>
<br>
@@ -301,8 +302,8 @@ namespace {<br>
} // end anonymous namespace<br>
<br>
MCAsmBackend *llvm::createSparcAsmBackend(c<wbr>onst Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
- return new ELFSparcAsmBackend(T, TT.getOS());<br>
+ return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS())<wbr>;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcMCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Sp<wbr>arc/MCTargetDesc/SparcMCTarget<wbr>Desc.h?rev=321692&r1=321691&<wbr>r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcMCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcMCTargetDesc.h Wed Jan 3 00:53:05 2018<br>
@@ -40,8 +40,8 @@ Target &getTheSparcelTarget();<br>
MCCodeEmitter *createSparcMCCodeEmitter(cons<wbr>t MCInstrInfo &MCII,<br>
const MCRegisterInfo &MRI,<br>
MCContext &Ctx);<br>
-MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
std::unique_ptr<MCObjectWrite<wbr>r><br>
createSparcELFObjectWriter(ra<wbr>w_pwrite_stream &OS, bool Is64Bit,<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCAsmBacke<wbr>nd.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Sy<wbr>stemZ/MCTargetDesc/SystemZMCAs<wbr>mBackend.cpp?rev=321692&r1=<wbr>321691&r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCAsmBacke<wbr>nd.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCAsmBacke<wbr>nd.cpp Wed Jan 3 00:53:05 2018<br>
@@ -14,6 +14,7 @@<br>
#include "llvm/MC/MCFixupKindInfo.h"<br>
#include "llvm/MC/MCInst.h"<br>
#include "llvm/MC/MCObjectWriter.h"<br>
+#include "llvm/MC/MCSubtargetInfo.h"<br>
<br>
using namespace llvm;<br>
<br>
@@ -122,9 +123,10 @@ bool SystemZMCAsmBackend::writeNopD<wbr>ata(u<br>
}<br>
<br>
MCAsmBackend *llvm::createSystemZMCAsmBacke<wbr>nd(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
- uint8_t OSABI = MCELFObjectTargetWriter::getOS<wbr>ABI(TT.getOS());<br>
+ uint8_t OSABI =<br>
+ MCELFObjectTargetWriter::getOS<wbr>ABI(STI.getTargetTriple().<wbr>getOS());<br>
return new SystemZMCAsmBackend(OSABI);<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCTargetDe<wbr>sc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Sy<wbr>stemZ/MCTargetDesc/SystemZMCTa<wbr>rgetDesc.h?rev=321692&r1=<wbr>321691&r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCTargetDe<wbr>sc.h (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCTargetDe<wbr>sc.h Wed Jan 3 00:53:05 2018<br>
@@ -89,8 +89,8 @@ MCCodeEmitter *createSystemZMCCodeEmitte<br>
MCContext &Ctx);<br>
<br>
MCAsmBackend *createSystemZMCAsmBackend(con<wbr>st Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
const MCTargetOptions &Options);<br>
<br>
std::unique_ptr<MCObjectWrite<wbr>r> createSystemZObjectWriter(raw_<wbr>pwrite_stream &OS,<br>
<br>
Modified: llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86AsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/MCTargetDesc/X86AsmBackend.<wbr>cpp?rev=321692&r1=321691&r2=<wbr>321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86AsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86AsmBackend.cpp Wed Jan 3 00:53:05 2018<br>
@@ -843,10 +843,12 @@ public:<br>
} // end anonymous namespace<br>
<br>
MCAsmBackend *llvm::createX86_32AsmBackend(<wbr>const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TheTriple,<br>
- StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
+ const Triple &TheTriple = STI.getTargetTriple();<br>
+ StringRef CPU = STI.getCPU();<br>
+ llvm::errs() << "create x86-32 backend with CPU: " << CPU << "\n";<br>
if (TheTriple.isOSBinFormatMachO(<wbr>))<br>
return new DarwinX86_32AsmBackend(T, MRI, CPU);<br>
<br>
@@ -862,10 +864,11 @@ MCAsmBackend *llvm::createX86_32AsmBacke<br>
}<br>
<br>
MCAsmBackend *llvm::createX86_64AsmBackend(<wbr>const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
const MCRegisterInfo &MRI,<br>
- const Triple &TheTriple,<br>
- StringRef CPU,<br>
const MCTargetOptions &Options) {<br>
+ const Triple &TheTriple = STI.getTargetTriple();<br>
+ StringRef CPU = STI.getCPU();<br>
if (TheTriple.isOSBinFormatMachO(<wbr>)) {<br>
MachO::CPUSubTypeX86 CS =<br>
StringSwitch<MachO::CPUSubTyp<wbr>eX86>(TheTriple.getArchName())<br>
<br>
Modified: llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86MCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/MCTargetDesc/X86MCTargetDesc<wbr>.h?rev=321692&r1=321691&r2=<wbr>321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86MCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86MCTargetDesc.h Wed Jan 3 00:53:05 2018<br>
@@ -70,11 +70,13 @@ MCCodeEmitter *createX86MCCodeEmitter(co<br>
const MCRegisterInfo &MRI,<br>
MCContext &Ctx);<br>
<br>
-MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createX86_32AsmBackend(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
-MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,<br>
- const Triple &TT, StringRef CPU,<br>
+MCAsmBackend *createX86_64AsmBackend(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
+ const MCRegisterInfo &MRI,<br>
const MCTargetOptions &Options);<br>
<br>
/// Implements X86-only directives for assembly emission.<br>
<br>
Modified: llvm/trunk/tools/dsymutil/Dwar<wbr>fLinker.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/dsymutil/DwarfLinker.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/tools/dsymuti<wbr>l/DwarfLinker.cpp?rev=321692&<wbr>r1=321691&r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/tools/dsymutil/Dwar<wbr>fLinker.cpp (original)<br>
+++ llvm/trunk/tools/dsymutil/Dwar<wbr>fLinker.cpp Wed Jan 3 00:53:05 2018<br>
@@ -672,8 +672,12 @@ bool DwarfStreamer::init(Triple TheTripl<br>
MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));<br>
MOFI->InitMCObjectFileInfo(Th<wbr>eTriple, /*PIC*/ false, *MC);<br>
<br>
+ MSTI.reset(TheTarget->createMC<wbr>SubtargetInfo(TripleName, "", ""));<br>
+ if (!MSTI)<br>
+ return error("no subtarget info for target " + TripleName, Context);<br>
+<br>
MCTargetOptions Options;<br>
- MAB = TheTarget->createMCAsmBackend(<wbr>*MRI, TripleName, "", Options);<br>
+ MAB = TheTarget->createMCAsmBackend(<wbr>*MSTI, *MRI, Options);<br>
if (!MAB)<br>
return error("no asm backend for target " + TripleName, Context);<br>
<br>
@@ -681,10 +685,6 @@ bool DwarfStreamer::init(Triple TheTripl<br>
if (!MII)<br>
return error("no instr info info for target " + TripleName, Context);<br>
<br>
- MSTI.reset(TheTarget->createMC<wbr>SubtargetInfo(TripleName, "", ""));<br>
- if (!MSTI)<br>
- return error("no subtarget info for target " + TripleName, Context);<br>
-<br>
MCE = TheTarget->createMCCodeEmitter<wbr>(*MII, *MRI, *MC);<br>
if (!MCE)<br>
return error("no code emitter for target " + TripleName, Context);<br>
<br>
Modified: llvm/trunk/tools/llvm-dwp/llvm<wbr>-dwp.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dwp/llvm-dwp.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/tools/llvm-dw<wbr>p/llvm-dwp.cpp?rev=321692&r1=<wbr>321691&r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/tools/llvm-dwp/llvm<wbr>-dwp.cpp (original)<br>
+++ llvm/trunk/tools/llvm-dwp/llvm<wbr>-dwp.cpp Wed Jan 3 00:53:05 2018<br>
@@ -673,8 +673,13 @@ int main(int argc, char **argv) {<br>
MCContext MC(MAI.get(), MRI.get(), &MOFI);<br>
MOFI.InitMCObjectFileInfo(The<wbr>Triple, /*PIC*/ false, MC);<br>
<br>
+ std::unique_ptr<MCSubtargetInf<wbr>o> MSTI(<br>
+ TheTarget->createMCSubtargetIn<wbr>fo(TripleName, "", ""));<br>
+ if (!MSTI)<br>
+ return error("no subtarget info for target " + TripleName, Context);<br>
+<br>
MCTargetOptions Options;<br>
- auto MAB = TheTarget->createMCAsmBackend(<wbr>*MRI, TripleName, "", Options);<br>
+ auto MAB = TheTarget->createMCAsmBackend(<wbr>*MSTI, *MRI, Options);<br>
if (!MAB)<br>
return error("no asm backend for target " + TripleName, Context);<br>
<br>
@@ -682,11 +687,6 @@ int main(int argc, char **argv) {<br>
if (!MII)<br>
return error("no instr info info for target " + TripleName, Context);<br>
<br>
- std::unique_ptr<MCSubtargetInf<wbr>o> MSTI(<br>
- TheTarget->createMCSubtargetIn<wbr>fo(TripleName, "", ""));<br>
- if (!MSTI)<br>
- return error("no subtarget info for target " + TripleName, Context);<br>
-<br>
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter<wbr>(*MII, *MRI, MC);<br>
if (!MCE)<br>
return error("no code emitter for target " + TripleName, Context);<br>
<br>
Modified: llvm/trunk/tools/llvm-mc/llvm-<wbr>mc.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/tools/llvm-mc<wbr>/llvm-mc.cpp?rev=321692&r1=321<wbr>691&r2=321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/tools/llvm-mc/llvm-<wbr>mc.cpp (original)<br>
+++ llvm/trunk/tools/llvm-mc/llvm-<wbr>mc.cpp Wed Jan 3 00:53:05 2018<br>
@@ -567,7 +567,7 @@ int main(int argc, char **argv) {<br>
MCAsmBackend *MAB = nullptr;<br>
if (ShowEncoding) {<br>
CE = TheTarget->createMCCodeEmitter<wbr>(*MCII, *MRI, Ctx);<br>
- MAB = TheTarget->createMCAsmBackend(<wbr>*MRI, TripleName, MCPU, MCOptions);<br>
+ MAB = TheTarget->createMCAsmBackend(<wbr>*STI, *MRI, MCOptions);<br>
}<br>
auto FOut = llvm::make_unique<formatted_ra<wbr>w_ostream>(*OS);<br>
Str.reset(TheTarget->createAs<wbr>mStreamer(<br>
@@ -588,8 +588,7 @@ int main(int argc, char **argv) {<br>
}<br>
<br>
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter<wbr>(*MCII, *MRI, Ctx);<br>
- MCAsmBackend *MAB = TheTarget->createMCAsmBackend(<wbr>*MRI, TripleName, MCPU,<br>
- MCOptions);<br>
+ MCAsmBackend *MAB = TheTarget->createMCAsmBackend(<wbr>*STI, *MRI, MCOptions);<br>
Str.reset(TheTarget->createMC<wbr>ObjectStreamer(<br>
TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(<wbr>MAB), *OS,<br>
std::unique_ptr<<wbr>MCCodeEmitter>(CE), *STI, MCOptions.MCRelaxAll,<br>
<br>
Modified: llvm/trunk/unittests/DebugInfo<wbr>/DWARF/DwarfGenerator.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/DebugInfo/DWARF/DwarfGenerator.cpp?rev=321692&r1=321691&r2=321692&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/unittests/Deb<wbr>ugInfo/DWARF/DwarfGenerator.<wbr>cpp?rev=321692&r1=321691&r2=<wbr>321692&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/unittests/DebugInfo<wbr>/DWARF/DwarfGenerator.cpp (original)<br>
+++ llvm/trunk/unittests/DebugInfo<wbr>/DWARF/DwarfGenerator.cpp Wed Jan 3 00:53:05 2018<br>
@@ -152,8 +152,13 @@ llvm::Error dwarfgen::Generator::init(Tr<br>
MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));<br>
MOFI->InitMCObjectFileInfo(Th<wbr>eTriple, /*PIC*/ false, *MC);<br>
<br>
+ MSTI.reset(TheTarget->createMC<wbr>SubtargetInfo(TripleName, "", ""));<br>
+ if (!MSTI)<br>
+ return make_error<StringError>("no subtarget info for target " + TripleName,<br>
+ inconvertibleErrorCode());<br>
+<br>
MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags()<wbr>;<br>
- MAB = TheTarget->createMCAsmBackend(<wbr>*MRI, TripleName, "", MCOptions);<br>
+ MAB = TheTarget->createMCAsmBackend(<wbr>*MSTI, *MRI, MCOptions);<br>
if (!MAB)<br>
return make_error<StringError>("no asm backend for target " + TripleName,<br>
inconvertibleErrorCode());<br>
@@ -164,11 +169,6 @@ llvm::Error dwarfgen::Generator::init(Tr<br>
TripleName,<br>
inconvertibleErrorCode());<br>
<br>
- MSTI.reset(TheTarget->createMC<wbr>SubtargetInfo(TripleName, "", ""));<br>
- if (!MSTI)<br>
- return make_error<StringError>("no subtarget info for target " + TripleName,<br>
- inconvertibleErrorCode());<br>
-<br>
MCE = TheTarget->createMCCodeEmitter<wbr>(*MII, *MRI, *MC);<br>
if (!MCE)<br>
return make_error<StringError>("no code emitter for target " + TripleName,<br>
<br>
<br>
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</blockquote></div><br></div>
</div></div></blockquote></div><br></div>