[PATCH] D41441: [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: rengolin, mcrosier, evandro, fhahn, echristo.
Herald added subscribers: kristof.beyls, tschuett, javed.absar, aemerson.

Add a register class for SVE predicate operands that can only be p0-p7 (as opposed to p0-p15)

Patch [1/3] in a series to add predicated ADD/SUB instructions for SVE.


https://reviews.llvm.org/D41441

Files:
  lib/Target/AArch64/AArch64RegisterInfo.td
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

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