[PATCH] D41382: [AArch64] Asm: Fix parsing of register aliases that have a name starting with 'z'
Sander de Smalen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 19 05:59:29 PST 2017
sdesmalen updated this revision to Diff 127513.
sdesmalen added a comment.
Fixed issue where matchRegisterNameAlias(..., RegKind::Scalar) also matched non-scalar identifiers.
https://reviews.llvm.org/D41382
Files:
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
test/MC/AArch64/SVE/dot-req.s
test/MC/AArch64/dot-req.s
Index: test/MC/AArch64/dot-req.s
===================================================================
--- test/MC/AArch64/dot-req.s
+++ test/MC/AArch64/dot-req.s
@@ -42,3 +42,8 @@
add peter, x0, x0
.unreq peter
// CHECK: add x6, x0, x0
+
+ zoe .req x6
+ add zoe, x0, x0
+ .unreq zoe
+// CHECK: add x6, x0, x0
Index: test/MC/AArch64/SVE/dot-req.s
===================================================================
--- /dev/null
+++ test/MC/AArch64/SVE/dot-req.s
@@ -0,0 +1,6 @@
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sve -show-encoding < %s 2>&1 | FileCheck %s
+
+foo:
+// CHECK: add z0.s, z1.s, z2.s
+ zbar .req z1
+ add z0.s, zbar.s, z2.s
Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1936,10 +1936,6 @@
.Default(false);
}
-static bool isSVEDataVectorRegister(StringRef Name) {
- return Name[0] == 'z';
-}
-
static void parseValidVectorKind(StringRef Name, unsigned &NumElements,
char &ElementKind) {
assert(isValidVectorKind(Name));
@@ -1969,18 +1965,16 @@
// Matches a register name or register alias previously defined by '.req'
unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
RegKind Kind) {
- unsigned RegNum;
- switch (Kind) {
- case RegKind::Scalar:
- RegNum = MatchRegisterName(Name);
- break;
- case RegKind::NeonVector:
- RegNum = MatchNeonVectorRegName(Name);
- break;
- case RegKind::SVEDataVector:
- RegNum = matchSVEDataVectorRegName(Name);
- break;
- }
+ unsigned RegNum = 0;
+ if ((RegNum = matchSVEDataVectorRegName(Name)))
+ return Kind == RegKind::SVEDataVector ? RegNum : 0;
+
+ if ((RegNum = MatchNeonVectorRegName(Name)))
+ return Kind == RegKind::NeonVector ? RegNum : 0;
+
+ // The parsed register must be of RegKind Scalar
+ if ((RegNum = MatchRegisterName(Name)))
+ return Kind == RegKind::Scalar ? RegNum : 0;
if (!RegNum) {
// Check for aliases registered via .req. Canonicalize to lower case.
@@ -2007,10 +2001,8 @@
return -1;
std::string lowerCase = Tok.getString().lower();
- if (isSVEDataVectorRegister(lowerCase))
- return -1;
-
unsigned RegNum = matchRegisterNameAlias(lowerCase, RegKind::Scalar);
+
// Also handle a few aliases of registers.
if (RegNum == 0)
RegNum = StringSwitch<unsigned>(lowerCase)
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