[PATCH] D41350: [DAGCombine] Improve ReduceLoadWidth for SRL

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
samparker added reviewers: niravd, RKSimon.
Herald added a subscriber: javed.absar.

If the SRL node is only used by an AND, we may be able to set the ExtVT to the width of the mask, making the AND redundant. To support this, another check has been added in isLegalNarrowLoad which queries whether the load is valid.

I've had to change a couple of X86 codegen tests, but I really don't know if they're correct. @RKSimon, if you could check these that would be great.


https://reviews.llvm.org/D41350

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/shift-combine.ll
  test/CodeGen/X86/2009-06-05-VZextByteShort.ll
  test/CodeGen/X86/h-registers-1.ll

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