[PATCH] D41126: [SelectionDAG] Fixed f16-from-vector promotion problem

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:1977
 // STORE promotion handlers.
 SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {
+  // If the bitcast is between scalar and v1 (in either direction), we need to
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I don't think here should be encountering a v1* anything. i.e. getTypeAction(v1f16) should not be a TypePromoteFloat?


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Comment at: lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:1979
+  // If the bitcast is between scalar and v1 (in either direction), we need to
+  // keep a bitcast between i16 and v1i16.
   EVT VT = N->getValueType(0);
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Shouldn't this be v1f16?


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Comment at: test/CodeGen/AMDGPU/unpack-half.ll:9
+
+define amdgpu_gs void @main(i32 inreg) local_unnamed_addr #0 {
+.entry:
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instnamer and check something


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Comment at: test/CodeGen/AMDGPU/unpack-half.ll:20
+  %7 = extractelement <2 x i32> %bc, i32 1
+  call void @llvm.amdgcn.tbuffer.store.i32(i32 %7, <4 x i32> undef, i32 0, i32 4, i32 %0, i32 0, i32 4, i32 4, i1 true, i1 true) #0
+  ret void
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You can probably replace the intrinsics with a regular load and store


https://reviews.llvm.org/D41126