[PATCH] D41126: [SelectionDAG] Fixed f16-from-vector promotion problem

[Tim Renouf via Phabricator via llvm-commits]

tpr created this revision.
tpr added reviewers: srhines, t.p.northover.
Herald added a subscriber: nhaehnle.

In the case of an fp_extend of v1f16 to v1f32 where the v1f16 is the
result of a bitcast from i16, avoid creating an illegal fp16_to_fp where
the input is not a vector and the result is a v1f32.


https://reviews.llvm.org/D41126

Files:
  lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
  test/CodeGen/AMDGPU/unpack-half.ll


Index: test/CodeGen/AMDGPU/unpack-half.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/unpack-half.ll
@@ -0,0 +1,30 @@
+; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+
+; On gfx6 and gfx7, this test shows a bug in SelectionDAG where scalarizing the
+; extension of a vector of f16 generates an illegal node that errors later.
+
+; FUNC-LABEL: {{^}}main:
+
+define amdgpu_gs void @main(i32 inreg) local_unnamed_addr #0 {
+.entry:
+  %1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 0, i32 undef, i1 true, i1 true) #1
+  %2 = bitcast float %1 to i32
+  %im0.i = lshr i32 %2, 16
+  %3 = insertelement <2 x i32> undef, i32 %im0.i, i32 1
+  %4 = trunc <2 x i32> %3 to <2 x i16>
+  %5 = bitcast <2 x i16> %4 to <2 x half>
+  %6 = fpext <2 x half> %5 to <2 x float>
+  %bc = bitcast <2 x float> %6 to <2 x i32>
+  %7 = extractelement <2 x i32> %bc, i32 1
+  call void @llvm.amdgcn.tbuffer.store.i32(i32 %7, <4 x i32> undef, i32 0, i32 4, i32 %0, i32 0, i32 4, i32 4, i1 true, i1 true) #0
+  ret void
+}
+
+declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #1
+
+declare void @llvm.amdgcn.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #0
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly }
+
Index: lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1975,10 +1975,20 @@
 // point at a higher precision.  Some of these cases are handled by FP_EXTEND,
 // STORE promotion handlers.
 SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {
+  // If the bitcast is between scalar and v1 (in either direction), we need to
+  // keep a bitcast between i16 and v1i16.
   EVT VT = N->getValueType(0);
+  auto Opnd = N->getOperand(0);
+  EVT OpndVT = Opnd->getValueType(0);
+  if (VT.isVector() != OpndVT.isVector()) {
+    EVT BitcastVT = OpndVT.getScalarType();
+    if (VT.isVector())
+      BitcastVT = EVT::getVectorVT(*DAG.getContext(), BitcastVT, 1);
+    Opnd = DAG.getNode(ISD::BITCAST, SDLoc(Opnd), BitcastVT, Opnd);
+  }
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
   return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT,
-                     N->getOperand(0));
+                     Opnd);
 }
 
 SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) {


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