[llvm] r320301 - [X86] Tag SSE4A instructions as SSE INTALU scheduler classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 10 04:08:04 PST 2017
Author: rksimon
Date: Sun Dec 10 04:08:04 2017
New Revision: 320301
URL: http://llvm.org/viewvc/llvm-project?rev=320301&view=rev
Log:
[X86] Tag SSE4A instructions as SSE INTALU scheduler classes
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=320301&r1=320300&r2=320301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Dec 10 04:08:04 2017
@@ -7448,23 +7448,27 @@ def EXTRQI : Ii8<0x78, MRMXr, (outs VR12
(ins VR128:$src, u8imm:$len, u8imm:$idx),
"extrq\t{$idx, $len, $src|$src, $len, $idx}",
[(set VR128:$dst, (X86extrqi VR128:$src, imm:$len,
- imm:$idx))]>, PD;
+ imm:$idx))], IIC_SSE_INTALU_P_RR>,
+ PD, Sched<[WriteVecALU]>;
def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src, VR128:$mask),
"extrq\t{$mask, $src|$src, $mask}",
[(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
- VR128:$mask))]>, PD;
+ VR128:$mask))], IIC_SSE_INTALU_P_RR>,
+ PD, Sched<[WriteVecALU]>;
def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
"insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
[(set VR128:$dst, (X86insertqi VR128:$src, VR128:$src2,
- imm:$len, imm:$idx))]>, XD;
+ imm:$len, imm:$idx))], IIC_SSE_INTALU_P_RR>,
+ XD, Sched<[WriteVecALU]>;
def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src, VR128:$mask),
"insertq\t{$mask, $src|$src, $mask}",
[(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
- VR128:$mask))]>, XD;
+ VR128:$mask))], IIC_SSE_INTALU_P_RR>,
+ XD, Sched<[WriteVecALU]>;
}
} // ExeDomain = SSEPackedInt
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