[llvm] r320300 - [X86] Flag BTVER2 scheduler model as complete

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Dec 10 03:51:29 2017
New Revision: 320300

URL: http://llvm.org/viewvc/llvm-project?rev=320300&view=rev
Log:
[X86] Flag BTVER2 scheduler model as complete

We just have to locally tag COPY as WriteMove

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=320300&r1=320299&r2=320300&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Sun Dec 10 03:51:29 2017
@@ -22,10 +22,6 @@ def BtVer2Model : SchedMachineModel {
   let HighLatency = 25;
   let MispredictPenalty = 14; // Minimum branch misdirection penalty
   let PostRAScheduler = 1;
-
-  // FIXME: SSE4/AVX is unimplemented. This flag is set to allow
-  // the scheduler to assign a default model to unrecognized opcodes.
-  let CompleteModel = 0;
 }
 
 let SchedModel = BtVer2Model in {
@@ -168,6 +164,9 @@ def : WriteRes<WriteLoad,  [JLAGU]> { le
 def : WriteRes<WriteStore, [JSAGU]>;
 def : WriteRes<WriteMove,  [JALU01]>;
 
+// Treat misc copies as a move.
+def : InstRW<[WriteMove], (instrs COPY)>;
+
 ////////////////////////////////////////////////////////////////////////////////
 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 // These can often bypass execution ports completely.