[llvm] r320261 - [X86] Tag frame pointer XORs instruction scheduler classes

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat Dec  9 11:56:39 2017
New Revision: 320261

URL: http://llvm.org/viewvc/llvm-project?rev=320261&view=rev
Log:
[X86] Tag frame pointer XORs instruction scheduler classes

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=320261&r1=320260&r2=320261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Sat Dec  9 11:56:39 2017
@@ -147,9 +147,11 @@ def WIN_ALLOCA_64 : I<0, Pseudo, (outs),
 // frame register after register allocation.
 let Constraints = "$src = $dst", isPseudo = 1, Defs = [EFLAGS] in {
   def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
-                  "xorl\t$$FP, $src", []>, Requires<[NotLP64]>;
+                  "xorl\t$$FP, $src", [], IIC_BIN_NONMEM>,
+                  Requires<[NotLP64]>, Sched<[WriteALU]>;
   def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src),
-                  "xorq\t$$FP $src", []>, Requires<[In64BitMode]>;
+                  "xorq\t$$FP $src", [], IIC_BIN_NONMEM>,
+                  Requires<[In64BitMode]>, Sched<[WriteALU]>;
 }
 
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