[PATCH] D40756: MachineVerifier: undef PHI args do not need to be alive

[Matthias Braun via Phabricator via llvm-commits]

MatzeB created this revision.
Herald added subscribers: wdng, mcrosier.

Undef phi operands don't need to be live.

I found this while manually crafting .mir tests, I haven't seen it in practical cases yet. Anyway it's the right thing to do.


Repository:
  rL LLVM

https://reviews.llvm.org/D40756

Files:
  lib/CodeGen/MachineVerifier.cpp
  test/CodeGen/X86/verifier-phi-fail0.mir
  test/CodeGen/X86/verifier-phi.mir


Index: test/CodeGen/X86/verifier-phi.mir
===================================================================
--- /dev/null
+++ test/CodeGen/X86/verifier-phi.mir
@@ -0,0 +1,34 @@
+# RUN: llc -o - %s -verify-machineinstrs -run-pass=none | FileCheck %s
+# This should cleanly pass the machine verifier
+---
+# CHECK-LABEL: name: func0
+# CHECK: %0:gr32 = PHI undef %1:gr32, %bb.0, undef %1:gr32, %bb.1
+name: func0
+tracksRegLiveness: true
+body: |
+  bb.0:
+    JE_1 %bb.1, implicit undef %eflags
+    JMP_1 %bb.2
+
+  bb.1:
+
+  bb.2:
+    %0 : gr32 = PHI undef %1 : gr32, %bb.0, undef %1 : gr32, %bb.1
+...
+---
+# CHECK-LABEL: name: func1
+# CHECK: %2:gr32 = PHI %0, %bb.0, %1, %bb.1
+name: func1
+tracksRegLiveness: true
+body: |
+  bb.0:
+    %0 : gr32 = IMPLICIT_DEF
+    JE_1 %bb.1, implicit undef %eflags
+    JMP_1 %bb.2
+
+  bb.1:
+    %1 : gr32 = IMPLICIT_DEF
+
+  bb.2:
+    %2 : gr32 = PHI %0, %bb.0, %1, %bb.1
+...
Index: test/CodeGen/X86/verifier-phi-fail0.mir
===================================================================
--- /dev/null
+++ test/CodeGen/X86/verifier-phi-fail0.mir
@@ -0,0 +1,30 @@
+# RUN: not llc -o - %s -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s
+---
+# CHECK: Bad machine code: PHI operand is not live-out from predecessor
+# CHECK: - function:    func0
+# CHECK: - basic block: BB#3
+# CHECK: - instruction: %vreg0<def> = PHI
+# CHECK: - operand 1:   %vreg1
+#
+# CHECK: Bad machine code: PHI operand is not live-out from predecessor
+# CHECK: - function:    func0
+# CHECK: - basic block: BB#3
+# CHECK: - instruction: %vreg0<def> = PHI
+# CHECK: - operand 3:   %vreg0
+name: func0
+tracksRegLiveness: true
+body: |
+  bb.0:
+    JE_1 %bb.1, implicit undef %eflags
+    JMP_1 %bb.2
+
+  bb.1:
+    %0:gr32 = IMPLICIT_DEF
+    JMP_1 %bb.3
+
+  bb.2:
+    %1:gr32 = IMPLICIT_DEF
+
+  bb.3:
+    %0:gr32 = PHI %1, %bb.1, %0, %bb.2
+...
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -1653,7 +1653,8 @@
       if (MInfo.reachable) {
         seen.insert(&Pre);
         BBInfo &PrInfo = MBBInfoMap[&Pre];
-        if (PrInfo.reachable && !PrInfo.isLiveOut(MO0.getReg()))
+        if (!MO0.isUndef() && PrInfo.reachable &&
+            !PrInfo.isLiveOut(MO0.getReg()))
           report("PHI operand is not live-out from predecessor", &MO0, I);
       }
     }


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