[llvm] r319308 - [X86][SSE] Merged sse2_pack and sse2_pack_y PACKSS/PACKUS instruction templates. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 29 03:35:45 PST 2017
Author: rksimon
Date: Wed Nov 29 03:35:45 2017
New Revision: 319308
URL: http://llvm.org/viewvc/llvm-project?rev=319308&view=rev
Log:
[X86][SSE] Merged sse2_pack and sse2_pack_y PACKSS/PACKUS instruction templates. NFCI.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=319308&r1=319307&r2=319308&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Nov 29 03:35:45 2017
@@ -3946,126 +3946,94 @@ defm PSHUFLW : sse2_pshuffle<"pshuflw",
let ExeDomain = SSEPackedInt in {
multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
- ValueType ArgVT, SDNode OpNode, OpndItins itins,
- PatFrag ld_frag, bit Is2Addr = 1> {
+ ValueType ArgVT, SDNode OpNode, RegisterClass RC,
+ X86MemOperand x86memop, OpndItins itins, PatFrag ld_frag,
+ bit Is2Addr = 1> {
def rr : PDI<opc, MRMSrcReg,
- (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+ (outs RC:$dst), (ins RC:$src1, RC:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst,
- (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))],
+ [(set RC:$dst,
+ (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))],
itins.rr>, Sched<[itins.Sched]>;
def rm : PDI<opc, MRMSrcMem,
- (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
+ (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst,
- (OutVT (OpNode (ArgVT VR128:$src1),
+ [(set RC:$dst,
+ (OutVT (OpNode (ArgVT RC:$src1),
(bitconvert (ld_frag addr:$src2)))))],
itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
}
-multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
- ValueType ArgVT, SDNode OpNode, OpndItins itins> {
- def Yrr : PDI<opc, MRMSrcReg,
- (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set VR256:$dst,
- (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))],
- itins.rr>, Sched<[itins.Sched]>;
- def Yrm : PDI<opc, MRMSrcMem,
- (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set VR256:$dst,
- (OutVT (OpNode (ArgVT VR256:$src1),
- (bitconvert (loadv4i64 addr:$src2)))))],
- itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
-}
-
multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
- ValueType ArgVT, SDNode OpNode, OpndItins itins,
- PatFrag ld_frag, bit Is2Addr = 1> {
+ ValueType ArgVT, SDNode OpNode, RegisterClass RC,
+ X86MemOperand x86memop, OpndItins itins, PatFrag ld_frag,
+ bit Is2Addr = 1> {
def rr : SS48I<opc, MRMSrcReg,
- (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+ (outs RC:$dst), (ins RC:$src1, RC:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst,
- (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))],
+ [(set RC:$dst,
+ (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))],
itins.rr>, Sched<[itins.Sched]>;
def rm : SS48I<opc, MRMSrcMem,
- (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
+ (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst,
- (OutVT (OpNode (ArgVT VR128:$src1),
+ [(set RC:$dst,
+ (OutVT (OpNode (ArgVT RC:$src1),
(bitconvert (ld_frag addr:$src2)))))],
itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
}
-multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
- ValueType ArgVT, SDNode OpNode, OpndItins itins> {
- def Yrr : SS48I<opc, MRMSrcReg,
- (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set VR256:$dst,
- (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))],
- itins.rr>, Sched<[itins.Sched]>;
- def Yrm : SS48I<opc, MRMSrcMem,
- (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set VR256:$dst,
- (OutVT (OpNode (ArgVT VR256:$src1),
- (bitconvert (loadv4i64 addr:$src2)))))],
- itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
-}
-
let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
- defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
- SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
- defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
- SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
-
- defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
- SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
- defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
- SSE_PACK, loadv2i64, 0>, VEX_4V;
+ defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss, VR128,
+ i128mem, SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
+ defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss, VR128,
+ i128mem, SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
+
+ defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus, VR128,
+ i128mem, SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
+ defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus, VR128,
+ i128mem, SSE_PACK, loadv2i64, 0>, VEX_4V;
}
let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
- defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss, SSE_PACK>,
- VEX_4V, VEX_L, VEX_WIG;
- defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss, SSE_PACK>,
- VEX_4V, VEX_L, VEX_WIG;
-
- defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus, SSE_PACK>,
- VEX_4V, VEX_L, VEX_WIG;
- defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus, SSE_PACK>,
- VEX_4V, VEX_L;
+ defm VPACKSSWBY : sse2_pack<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
+ VR256, i256mem, SSE_PACK, loadv4i64, 0>,
+ VEX_4V, VEX_L, VEX_WIG;
+ defm VPACKSSDWY : sse2_pack<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
+ VR256, i256mem, SSE_PACK, loadv4i64, 0>,
+ VEX_4V, VEX_L, VEX_WIG;
+
+ defm VPACKUSWBY : sse2_pack<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
+ VR256,i256mem, SSE_PACK, loadv4i64, 0>,
+ VEX_4V, VEX_L, VEX_WIG;
+ defm VPACKUSDWY : sse4_pack<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
+ VR256, i256mem, SSE_PACK, loadv4i64, 0>,
+ VEX_4V, VEX_L;
}
let Constraints = "$src1 = $dst" in {
- defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss, SSE_PACK,
- memopv2i64>;
- defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss, SSE_PACK,
- memopv2i64>;
+ defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss, VR128,
+ i128mem, SSE_PACK, memopv2i64>;
+ defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss, VR128,
+ i128mem, SSE_PACK, memopv2i64>;
- defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus, SSE_PACK,
- memopv2i64>;
+ defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus, VR128,
+ i128mem, SSE_PACK, memopv2i64>;
- defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus, SSE_PACK,
- memopv2i64>;
+ defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus, VR128,
+ i128mem, SSE_PACK, memopv2i64>;
}
} // ExeDomain = SSEPackedInt
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