[llvm] r319187 - [CodeGen] Print register names in lowercase in both MIR and debug output
Francis Visoiu Mistrih via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 28 09:15:10 PST 2017
Author: thegameg
Date: Tue Nov 28 09:15:09 2017
New Revision: 319187
URL: http://llvm.org/viewvc/llvm-project?rev=319187&view=rev
Log:
[CodeGen] Print register names in lowercase in both MIR and debug output
As part of the unification of the debug format and the MIR format,
always print registers as lowercase.
* Only debug printing is affected. It now follows MIR.
Differential Revision: https://reviews.llvm.org/D40417
Modified:
llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h
llvm/trunk/include/llvm/CodeGen/MachineOperand.h
llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp
llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/MachineCSE.cpp
llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp
llvm/trunk/lib/CodeGen/MachineSink.cpp
llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
llvm/trunk/lib/CodeGen/README.txt
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td
llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td
llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp
llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp
llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp
llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp
llvm/trunk/lib/Target/X86/README-SSE.txt
llvm/trunk/lib/Target/X86/README-X86-64.txt
llvm/trunk/lib/Target/X86/X86CallingConv.td
llvm/trunk/lib/Target/X86/X86FastISel.cpp
llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp
llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
llvm/trunk/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll
llvm/trunk/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll
llvm/trunk/test/CodeGen/AArch64/loh.mir
llvm/trunk/test/CodeGen/AArch64/machine-copy-prop.ll
llvm/trunk/test/CodeGen/AArch64/phi-dbg.ll
llvm/trunk/test/CodeGen/AArch64/scheduledag-constreg.mir
llvm/trunk/test/CodeGen/AMDGPU/lds-output-queue.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.dbg.value.ll
llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure.mir
llvm/trunk/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll
llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll
llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll
llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir
llvm/trunk/test/CodeGen/BPF/sockex2.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll
llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll
llvm/trunk/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll
llvm/trunk/test/CodeGen/PowerPC/fp64-to-int16.ll
llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
llvm/trunk/test/CodeGen/PowerPC/quadint-return.ll
llvm/trunk/test/CodeGen/SystemZ/int-div-01.ll
llvm/trunk/test/CodeGen/SystemZ/int-div-02.ll
llvm/trunk/test/CodeGen/SystemZ/int-div-03.ll
llvm/trunk/test/CodeGen/SystemZ/int-div-04.ll
llvm/trunk/test/CodeGen/SystemZ/int-div-05.ll
llvm/trunk/test/CodeGen/SystemZ/int-div-06.ll
llvm/trunk/test/CodeGen/SystemZ/int-mul-08.ll
llvm/trunk/test/CodeGen/SystemZ/int-mul-10.ll
llvm/trunk/test/CodeGen/SystemZ/pr32505.ll
llvm/trunk/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll
llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
llvm/trunk/test/CodeGen/X86/2010-05-12-FastAllocKills.ll
llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll
llvm/trunk/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/ext.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/gep.ll
llvm/trunk/test/CodeGen/X86/add-sub-nsw-nuw.ll
llvm/trunk/test/CodeGen/X86/add.ll
llvm/trunk/test/CodeGen/X86/addcarry.ll
llvm/trunk/test/CodeGen/X86/anyext.ll
llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll
llvm/trunk/test/CodeGen/X86/avx-cast.ll
llvm/trunk/test/CodeGen/X86/avx-cmp.ll
llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx-load-store.ll
llvm/trunk/test/CodeGen/X86/avx-splat.ll
llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll
llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll
llvm/trunk/test/CodeGen/X86/avx2-conversions.ll
llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/avx2-masked-gather.ll
llvm/trunk/test/CodeGen/X86/avx2-shift.ll
llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll
llvm/trunk/test/CodeGen/X86/avx512-arith.ll
llvm/trunk/test/CodeGen/X86/avx512-build-vector.ll
llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll
llvm/trunk/test/CodeGen/X86/avx512-cmp-kor-sequence.ll
llvm/trunk/test/CodeGen/X86/avx512-cvt.ll
llvm/trunk/test/CodeGen/X86/avx512-ext.ll
llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll
llvm/trunk/test/CodeGen/X86/avx512-hadd-hsub.ll
llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll
llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll
llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll
llvm/trunk/test/CodeGen/X86/avx512-memfold.ll
llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll
llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll
llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
llvm/trunk/test/CodeGen/X86/avx512-select.ll
llvm/trunk/test/CodeGen/X86/avx512-shift.ll
llvm/trunk/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
llvm/trunk/test/CodeGen/X86/avx512-trunc.ll
llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll
llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll
llvm/trunk/test/CodeGen/X86/avx512-vec3-crash.ll
llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512bw-mov.ll
llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll
llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512dq-mask-op.ll
llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512f-vec-test-testn.ll
llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll
llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
llvm/trunk/test/CodeGen/X86/avx512vl-vec-test-testn.ll
llvm/trunk/test/CodeGen/X86/base-pointer-and-cmpxchg.ll
llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-128.ll
llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll
llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll
llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector.ll
llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll
llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll
llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll
llvm/trunk/test/CodeGen/X86/bitreverse.ll
llvm/trunk/test/CodeGen/X86/bmi-schedule.ll
llvm/trunk/test/CodeGen/X86/bmi.ll
llvm/trunk/test/CodeGen/X86/bool-simplify.ll
llvm/trunk/test/CodeGen/X86/bool-vector.ll
llvm/trunk/test/CodeGen/X86/broadcastm-lowering.ll
llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll
llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll
llvm/trunk/test/CodeGen/X86/clz.ll
llvm/trunk/test/CodeGen/X86/cmov-into-branch.ll
llvm/trunk/test/CodeGen/X86/cmov-promotion.ll
llvm/trunk/test/CodeGen/X86/cmov.ll
llvm/trunk/test/CodeGen/X86/coalescer-dce.ll
llvm/trunk/test/CodeGen/X86/combine-abs.ll
llvm/trunk/test/CodeGen/X86/compress_expand.ll
llvm/trunk/test/CodeGen/X86/critical-edge-split-2.ll
llvm/trunk/test/CodeGen/X86/ctpop-combine.ll
llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll
llvm/trunk/test/CodeGen/X86/divide-by-constant.ll
llvm/trunk/test/CodeGen/X86/divrem.ll
llvm/trunk/test/CodeGen/X86/divrem8_ext.ll
llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir
llvm/trunk/test/CodeGen/X86/extractelement-index.ll
llvm/trunk/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/fast-isel-cmp.ll
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llvm/trunk/test/CodeGen/X86/fast-isel-sext-zext.ll
llvm/trunk/test/CodeGen/X86/fast-isel-shift.ll
llvm/trunk/test/CodeGen/X86/fixup-bw-copy.ll
llvm/trunk/test/CodeGen/X86/fp_load_cast_fold.ll
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llvm/trunk/test/CodeGen/X86/handle-move.ll
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llvm/trunk/test/CodeGen/X86/iabs.ll
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llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll
llvm/trunk/test/CodeGen/X86/inline-asm-stack-realign.ll
llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll
llvm/trunk/test/CodeGen/X86/lea-3.ll
llvm/trunk/test/CodeGen/X86/lea-opt-cse3.ll
llvm/trunk/test/CodeGen/X86/lea32-schedule.ll
llvm/trunk/test/CodeGen/X86/loop-search.ll
llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll
llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll
llvm/trunk/test/CodeGen/X86/machine-cse.ll
llvm/trunk/test/CodeGen/X86/machine-outliner-tailcalls.ll
llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll
llvm/trunk/test/CodeGen/X86/masked_memop.ll
llvm/trunk/test/CodeGen/X86/maskmovdqu.ll
llvm/trunk/test/CodeGen/X86/misched-copy.ll
llvm/trunk/test/CodeGen/X86/movmsk.ll
llvm/trunk/test/CodeGen/X86/mul-constant-i16.ll
llvm/trunk/test/CodeGen/X86/mul-constant-i32.ll
llvm/trunk/test/CodeGen/X86/mul-constant-result.ll
llvm/trunk/test/CodeGen/X86/negate-i1.ll
llvm/trunk/test/CodeGen/X86/norex-subreg.ll
llvm/trunk/test/CodeGen/X86/oddshuffles.ll
llvm/trunk/test/CodeGen/X86/or-lea.ll
llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-3.ll
llvm/trunk/test/CodeGen/X86/pmul.ll
llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll
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llvm/trunk/test/CodeGen/X86/pr22970.ll
llvm/trunk/test/CodeGen/X86/pr26870.ll
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llvm/trunk/test/CodeGen/X86/vector-shuffle-variable-128.ll
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llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll
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llvm/trunk/test/CodeGen/X86/vector-tzcnt-128.ll
llvm/trunk/test/CodeGen/X86/vector-tzcnt-256.ll
llvm/trunk/test/CodeGen/X86/vpshufbitqbm-intrinsics.ll
llvm/trunk/test/CodeGen/X86/vselect-pcmp.ll
llvm/trunk/test/CodeGen/X86/widen_bitops-0.ll
llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll
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llvm/trunk/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
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llvm/trunk/test/DebugInfo/X86/dbg-value-frame-index.ll
llvm/trunk/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
llvm/trunk/test/DebugInfo/X86/dbg-value-transfer-order.ll
llvm/trunk/test/DebugInfo/X86/debug-loc-asan.ll
llvm/trunk/test/DebugInfo/X86/live-debug-values.ll
llvm/trunk/test/DebugInfo/X86/live-debug-vars-dse.mir
llvm/trunk/test/DebugInfo/X86/op_deref.ll
llvm/trunk/test/DebugInfo/X86/pieces-4.ll
llvm/trunk/test/DebugInfo/X86/sdag-split-arg.ll
llvm/trunk/test/DebugInfo/X86/spill-indirect-nrvo.ll
llvm/trunk/test/DebugInfo/X86/spill-nontrivial-param.ll
llvm/trunk/test/DebugInfo/X86/spill-nospill.ll
llvm/trunk/test/DebugInfo/X86/vla.ll
llvm/trunk/test/MC/COFF/cv-def-range.s
llvm/trunk/test/MC/X86/x86-64.s
Modified: llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h Tue Nov 28 09:15:09 2017
@@ -20,11 +20,11 @@
/// register.
///
/// X86 Example:
-/// %YMM0<def> = ...
-/// %XMM0<def> = ... (Kills %XMM0, all %XMM0s sub-registers, and %YMM0)
+/// %ymm0<def> = ...
+/// %xmm0<def> = ... (Kills %xmm0, all %xmm0s sub-registers, and %ymm0)
///
-/// %YMM0<def> = ...
-/// %XMM0<def> = ..., %YMM0<imp-use> (%YMM0 and all its sub-registers are alive)
+/// %ymm0<def> = ...
+/// %xmm0<def> = ..., %ymm0<imp-use> (%ymm0 and all its sub-registers are alive)
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_LIVEPHYSREGS_H
Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Tue Nov 28 09:15:09 2017
@@ -371,7 +371,7 @@ public:
/// substPhysReg - Substitute the current register with the physical register
/// Reg, taking any existing SubReg into account. For instance,
- /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL.
+ /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
///
void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
Modified: llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h Tue Nov 28 09:15:09 2017
@@ -1140,7 +1140,7 @@ struct VirtReg2IndexFunctor {
/// %noreg - NoRegister
/// %vreg5 - a virtual register.
/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
-/// %EAX - a physical register
+/// %eax - a physical register
/// %physreg17 - a physical register when no TRI instance given.
///
/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
@@ -1151,8 +1151,8 @@ Printable printReg(unsigned Reg, const T
///
/// Register units are named after their root registers:
///
-/// AL - Single root.
-/// FP0~ST7 - Dual roots.
+/// al - Single root.
+/// fp0~st7 - Dual roots.
///
/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Tue Nov 28 09:15:09 2017
@@ -448,11 +448,11 @@ void AggressiveAntiDepBreaker::ScanInstr
// FIXME: The issue with predicated instruction is more complex. We are being
// conservatively here because the kill markers cannot be trusted after
// if-conversion:
- // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
+ // %r6<def> = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
// ...
- // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
- // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
- // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
+ // STR %r0, %r6<kill>, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395]
+ // %r6<def> = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12]
+ // STR %r0, %r6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
//
// The first R6 kill is not really a kill since it's killed by a predicated
// instruction which may not be executed. The second R6 def may or may not
Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Tue Nov 28 09:15:09 2017
@@ -170,11 +170,11 @@ void CriticalAntiDepBreaker::PrescanInst
// FIXME: The issue with predicated instruction is more complex. We are being
// conservative here because the kill markers cannot be trusted after
// if-conversion:
- // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
+ // %r6<def> = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
// ...
- // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
- // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
- // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
+ // STR %r0, %r6<kill>, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395]
+ // %r6<def> = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12]
+ // STR %r0, %r6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
//
// The first R6 kill is not really a kill since it's killed by a predicated
// instruction which may not be executed. The second R6 def may or may not
Modified: llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp Tue Nov 28 09:15:09 2017
@@ -104,8 +104,8 @@ bool ExpandPostRA::LowerSubregToReg(Mach
if (DstSubReg == InsReg) {
// No need to insert an identity copy instruction.
// Watch out for case like this:
- // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
- // We must leave %RAX live.
+ // %rax<def> = SUBREG_TO_REG 0, %eax<kill>, 3
+ // We must leave %rax live.
if (DstReg != InsReg) {
MI->setDesc(TII->get(TargetOpcode::KILL));
MI->RemoveOperand(3); // SubIdx
Modified: llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp (original)
+++ llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp Tue Nov 28 09:15:09 2017
@@ -498,7 +498,7 @@ bool ImplicitNullChecks::analyzeBlockFor
// Starting with a code fragment like:
//
- // test %RAX, %RAX
+ // test %rax, %rax
// jne LblNotNull
//
// LblNull:
@@ -508,13 +508,13 @@ bool ImplicitNullChecks::analyzeBlockFor
// Inst0
// Inst1
// ...
- // Def = Load (%RAX + <offset>)
+ // Def = Load (%rax + <offset>)
// ...
//
//
// we want to end up with
//
- // Def = FaultingLoad (%RAX + <offset>), LblNull
+ // Def = FaultingLoad (%rax + <offset>), LblNull
// jmp LblNotNull ;; explicit or fallthrough
//
// LblNotNull:
@@ -528,11 +528,11 @@ bool ImplicitNullChecks::analyzeBlockFor
//
// To see why this is legal, consider the two possibilities:
//
- // 1. %RAX is null: since we constrain <offset> to be less than PageSize, the
+ // 1. %rax is null: since we constrain <offset> to be less than PageSize, the
// load instruction dereferences the null page, causing a segmentation
// fault.
//
- // 2. %RAX is not null: in this case we know that the load cannot fault, as
+ // 2. %rax is not null: in this case we know that the load cannot fault, as
// otherwise the load would've faulted in the original program too and the
// original program would've been undefined.
//
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Tue Nov 28 09:15:09 2017
@@ -698,11 +698,11 @@ void LiveIntervals::addKillFlags(const V
// Check if any of the regunits are live beyond the end of RI. That could
// happen when a physreg is defined as a copy of a virtreg:
//
- // %EAX = COPY %vreg5
- // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
- // BAR %EAX<kill>
+ // %eax = COPY %vreg5
+ // FOO %vreg5 <--- MI, cancel kill because %eax is live.
+ // BAR %eax<kill>
//
- // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
+ // There should be no kill flag on FOO when %vreg5 is rewritten as %eax.
for (auto &RUP : RU) {
const LiveRange &RURange = *RUP.first;
LiveRange::const_iterator &I = RUP.second;
Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Tue Nov 28 09:15:09 2017
@@ -623,12 +623,12 @@ bool MachineCSE::ProcessBlock(MachineBas
// Go through implicit defs of CSMI and MI, and clear the kill flags on
// their uses in all the instructions between CSMI and MI.
// We might have made some of the kill flags redundant, consider:
- // subs ... %NZCV<imp-def> <- CSMI
- // csinc ... %NZCV<imp-use,kill> <- this kill flag isn't valid anymore
- // subs ... %NZCV<imp-def> <- MI, to be eliminated
- // csinc ... %NZCV<imp-use,kill>
+ // subs ... %nzcv<imp-def> <- CSMI
+ // csinc ... %nzcv<imp-use,kill> <- this kill flag isn't valid anymore
+ // subs ... %nzcv<imp-def> <- MI, to be eliminated
+ // csinc ... %nzcv<imp-use,kill>
// Since we eliminated MI, and reused a register imp-def'd by CSMI
- // (here %NZCV), that register, if it was killed before MI, should have
+ // (here %nzcv), that register, if it was killed before MI, should have
// that kill flag removed, because it's lifetime was extended.
if (CSMI->getParent() == MI->getParent()) {
for (MachineBasicBlock::iterator II = CSMI, IE = MI; II != IE; ++II)
Modified: llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp Tue Nov 28 09:15:09 2017
@@ -226,19 +226,19 @@ void MachineCopyPropagation::CopyPropaga
// The two copies cancel out and the source of the first copy
// hasn't been overridden, eliminate the second one. e.g.
- // %ECX<def> = COPY %EAX
- // ... nothing clobbered EAX.
- // %EAX<def> = COPY %ECX
+ // %ecx<def> = COPY %eax
+ // ... nothing clobbered eax.
+ // %eax<def> = COPY %ecx
// =>
- // %ECX<def> = COPY %EAX
+ // %ecx<def> = COPY %eax
//
// or
//
- // %ECX<def> = COPY %EAX
- // ... nothing clobbered EAX.
- // %ECX<def> = COPY %EAX
+ // %ecx<def> = COPY %eax
+ // ... nothing clobbered eax.
+ // %ecx<def> = COPY %eax
// =>
- // %ECX<def> = COPY %EAX
+ // %ecx<def> = COPY %eax
if (eraseIfRedundant(*MI, Def, Src) || eraseIfRedundant(*MI, Src, Def))
continue;
Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Tue Nov 28 09:15:09 2017
@@ -246,9 +246,9 @@ MachineSinking::AllUsesDominatedByBlock(
// BB#1: derived from LLVM BB %bb4.preheader
// Predecessors according to CFG: BB#0
// ...
- // %reg16385<def> = DEC64_32r %reg16437, %EFLAGS<imp-def,dead>
+ // %reg16385<def> = DEC64_32r %reg16437, %eflags<imp-def,dead>
// ...
- // JE_4 <BB#37>, %EFLAGS<imp-use>
+ // JE_4 <BB#37>, %eflags<imp-use>
// Successors according to CFG: BB#37 BB#2
//
// BB#2: derived from LLVM BB %bb.nph
Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Tue Nov 28 09:15:09 2017
@@ -1516,7 +1516,7 @@ bool PeepholeOptimizer::foldRedundantNAP
unsigned DstReg = MI->getOperand(0).getReg();
unsigned SrcReg = MI->getOperand(1).getReg();
if (isNAPhysCopy(SrcReg) && TargetRegisterInfo::isVirtualRegister(DstReg)) {
- // %vreg = COPY %PHYSREG
+ // %vreg = COPY %physreg
// Avoid using a datastructure which can track multiple live non-allocatable
// phys->virt copies since LLVM doesn't seem to do this.
NAPhysToVirtMIs.insert({SrcReg, MI});
@@ -1526,7 +1526,7 @@ bool PeepholeOptimizer::foldRedundantNAP
if (!(TargetRegisterInfo::isVirtualRegister(SrcReg) && isNAPhysCopy(DstReg)))
return false;
- // %PHYSREG = COPY %vreg
+ // %physreg = COPY %vreg
auto PrevCopy = NAPhysToVirtMIs.find(DstReg);
if (PrevCopy == NAPhysToVirtMIs.end()) {
// We can't remove the copy: there was an intervening clobber of the
@@ -1696,8 +1696,8 @@ bool PeepholeOptimizer::runOnMachineFunc
// Track when a non-allocatable physical register is copied to a virtual
// register so that useless moves can be removed.
//
- // %PHYSREG is the map index; MI is the last valid `%vreg = COPY %PHYSREG`
- // without any intervening re-definition of %PHYSREG.
+ // %physreg is the map index; MI is the last valid `%vreg = COPY %physreg`
+ // without any intervening re-definition of %physreg.
DenseMap<unsigned, MachineInstr *> NAPhysToVirtMIs;
// Set of virtual registers that are copied from.
Modified: llvm/trunk/lib/CodeGen/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/README.txt?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/README.txt (original)
+++ llvm/trunk/lib/CodeGen/README.txt Tue Nov 28 09:15:09 2017
@@ -33,7 +33,7 @@ It also increase the likelihood the stor
bb27 ...
...
%reg1037 = ADDri %reg1039, 1
- %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
+ %reg1038 = ADDrs %reg1032, %reg1039, %noreg, 10
Successors according to CFG: 0x8b03bf0 (#5)
bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Nov 28 09:15:09 2017
@@ -1820,20 +1820,20 @@ bool RegisterCoalescer::joinReservedPhys
MachineInstr *CopyMI;
if (CP.isFlipped()) {
// Physreg is copied into vreg
- // %vregY = COPY %X
- // ... //< no other def of %X here
+ // %vregY = COPY %x
+ // ... //< no other def of %x here
// use %vregY
// =>
// ...
- // use %X
+ // use %x
CopyMI = MRI->getVRegDef(SrcReg);
} else {
// VReg is copied into physreg:
// %vregX = def
- // ... //< no other def or use of %Y here
- // %Y = COPY %vregX
+ // ... //< no other def or use of %y here
+ // %y = COPY %vregX
// =>
- // %Y = def
+ // %y = def
// ...
if (!MRI->hasOneNonDBGUse(SrcReg)) {
DEBUG(dbgs() << "\t\tMultiple vreg uses!\n");
Modified: llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp Tue Nov 28 09:15:09 2017
@@ -15,6 +15,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringExtras.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -93,9 +94,10 @@ Printable printReg(unsigned Reg, const T
OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
else if (TargetRegisterInfo::isVirtualRegister(Reg))
OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
- else if (TRI && Reg < TRI->getNumRegs())
- OS << '%' << TRI->getName(Reg);
- else
+ else if (TRI && Reg < TRI->getNumRegs()) {
+ OS << '%';
+ printLowerCase(TRI->getName(Reg), OS);
+ } else
OS << "%physreg" << Reg;
if (SubIdx) {
if (TRI)
Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Nov 28 09:15:09 2017
@@ -589,23 +589,23 @@ isProfitableToCommute(unsigned regA, uns
// e.g.
// %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
// %reg1029<def> = MOV8rr %reg1028
- // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
+ // %reg1029<def> = SHR8ri %reg1029, 7, %eflags<imp-def,dead>
// insert => %reg1030<def> = MOV8rr %reg1028
- // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
+ // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %eflags<imp-def,dead>
// In this case, it might not be possible to coalesce the second MOV8rr
// instruction if the first one is coalesced. So it would be profitable to
// commute it:
// %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
// %reg1029<def> = MOV8rr %reg1028
- // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
+ // %reg1029<def> = SHR8ri %reg1029, 7, %eflags<imp-def,dead>
// insert => %reg1030<def> = MOV8rr %reg1029
- // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
+ // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %eflags<imp-def,dead>
if (!isPlainlyKilled(MI, regC, LIS))
return false;
// Ok, we have something like:
- // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
+ // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %eflags<imp-def,dead>
// let's see if it's worth commuting it.
// Look for situations like this:
Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Tue Nov 28 09:15:09 2017
@@ -380,8 +380,8 @@ void VirtRegRewriter::handleIdentityCopy
++NumIdCopies;
// Copies like:
- // %R0 = COPY %R0<undef>
- // %AL = COPY %AL, %EAX<imp-def>
+ // %r0 = COPY %r0<undef>
+ // %al = COPY %al, %eax<imp-def>
// give us additional liveness information: The target (super-)register
// must not be valid before this point. Replace the COPY with a KILL
// instruction to maintain this information.
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Tue Nov 28 09:15:09 2017
@@ -2801,11 +2801,11 @@ MachineInstr *AArch64InstrInfo::foldMemo
LiveIntervals *LIS) const {
// This is a bit of a hack. Consider this instruction:
//
- // %vreg0<def> = COPY %SP; GPR64all:%vreg0
+ // %vreg0<def> = COPY %sp; GPR64all:%vreg0
//
// We explicitly chose GPR64all for the virtual register so such a copy might
// be eliminated by RegisterCoalescer. However, that may not be possible, and
- // %vreg0 may even spill. We can't spill %SP, and since it is in the GPR64all
+ // %vreg0 may even spill. We can't spill %sp, and since it is in the GPR64all
// register class, TargetInstrInfo::foldMemoryOperand() is going to try.
//
// To prevent that, we are going to constrain the %vreg0 register class here.
@@ -2830,12 +2830,12 @@ MachineInstr *AArch64InstrInfo::foldMemo
// Handle the case where a copy is being spilled or filled but the source
// and destination register class don't match. For example:
//
- // %vreg0<def> = COPY %XZR; GPR64common:%vreg0
+ // %vreg0<def> = COPY %xzr; GPR64common:%vreg0
//
// In this case we can still safely fold away the COPY and generate the
// following spill code:
//
- // STRXui %XZR, <fi#0>
+ // STRXui %xzr, <fi#0>
//
// This also eliminates spilled cross register class COPYs (e.g. between x and
// d regs) of the same size. For example:
@@ -2886,12 +2886,12 @@ MachineInstr *AArch64InstrInfo::foldMemo
// Handle cases like spilling def of:
//
- // %vreg0:sub_32<def,read-undef> = COPY %WZR; GPR64common:%vreg0
+ // %vreg0:sub_32<def,read-undef> = COPY %wzr; GPR64common:%vreg0
//
// where the physical register source can be widened and stored to the full
// virtual reg destination stack slot, in this case producing:
//
- // STRXui %XZR, <fi#0>
+ // STRXui %xzr, <fi#0>
//
if (IsSpill && DstMO.isUndef() &&
TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
Modified: llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp Tue Nov 28 09:15:09 2017
@@ -830,8 +830,8 @@ AArch64LoadStoreOpt::mergePairedInsns(Ma
if (SExtIdx != -1) {
// Generate the sign extension for the proper result of the ldp.
// I.e., with X1, that would be:
- // %W1<def> = KILL %W1, %X1<imp-def>
- // %X1<def> = SBFMXri %X1<kill>, 0, 31
+ // %w1<def> = KILL %w1, %x1<imp-def>
+ // %x1<def> = SBFMXri %x1<kill>, 0, 31
MachineOperand &DstMO = MIB->getOperand(SExtIdx);
// Right now, DstMO has the extended register, since it comes from an
// extended opcode.
Modified: llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td Tue Nov 28 09:15:09 2017
@@ -144,8 +144,8 @@ def VTX_READ_32_cm
// to be caused by ALU instructions in the next instruction group that wrote
// to the $src_gpr registers of the VTX_READ.
// e.g.
- // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
- // %T2_X<def> = MOV %ZERO
+ // %t3_x<def> = VTX_READ_PARAM_32_eg %t2_x<kill>, 24
+ // %t2_x<def> = MOV %zero
//Adding this constraint prevents this from happening.
let Constraints = "$src_gpr.ptr = $dst_gpr";
}
Modified: llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td Tue Nov 28 09:15:09 2017
@@ -212,8 +212,8 @@ def VTX_READ_32_eg
// to be caused by ALU instructions in the next instruction group that wrote
// to the $src_gpr registers of the VTX_READ.
// e.g.
- // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
- // %T2_X<def> = MOV %ZERO
+ // %t3_x<def> = VTX_READ_PARAM_32_eg %t2_x<kill>, 24
+ // %t2_x<def> = MOV %zero
//Adding this constraint prevents this from happening.
let Constraints = "$src_gpr.ptr = $dst_gpr";
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp Tue Nov 28 09:15:09 2017
@@ -971,9 +971,9 @@ bool SIFoldOperands::runOnMachineFunctio
// Prevent folding operands backwards in the function. For example,
// the COPY opcode must not be replaced by 1 in this example:
//
- // %vreg3<def> = COPY %VGPR0; VGPR_32:%vreg3
+ // %vreg3<def> = COPY %vgpr0; VGPR_32:%vreg3
// ...
- // %VGPR0<def> = V_MOV_B32_e32 1, %EXEC<imp-use>
+ // %vgpr0<def> = V_MOV_B32_e32 1, %exec<imp-use>
MachineOperand &Dst = MI.getOperand(0);
if (Dst.isReg() &&
!TargetRegisterInfo::isVirtualRegister(Dst.getReg()))
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Tue Nov 28 09:15:09 2017
@@ -6600,7 +6600,7 @@ void SITargetLowering::adjustWritemask(M
I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
return;
- // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
+ // Lane means which subreg of %vgpra_vgprb_vgprc_vgprd is used.
// Note that subregs are packed, i.e. Lane==0 is the first bit set
// in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
// set, etc.
Modified: llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp Tue Nov 28 09:15:09 2017
@@ -21,31 +21,31 @@
/// EXEC to update the predicates.
///
/// For example:
-/// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
-/// %SGPR0 = SI_IF %VCC
-/// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
-/// %SGPR0 = SI_ELSE %SGPR0
-/// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
-/// SI_END_CF %SGPR0
+/// %vcc = V_CMP_GT_F32 %vgpr1, %vgpr2
+/// %sgpr0 = SI_IF %vcc
+/// %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0
+/// %sgpr0 = SI_ELSE %sgpr0
+/// %vgpr0 = V_SUB_F32 %vgpr0, %vgpr0
+/// SI_END_CF %sgpr0
///
/// becomes:
///
-/// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
-/// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
+/// %sgpr0 = S_AND_SAVEEXEC_B64 %vcc // Save and update the exec mask
+/// %sgpr0 = S_XOR_B64 %sgpr0, %exec // Clear live bits from saved exec mask
/// S_CBRANCH_EXECZ label0 // This instruction is an optional
/// // optimization which allows us to
/// // branch if all the bits of
/// // EXEC are zero.
-/// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
+/// %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0 // Do the IF block of the branch
///
/// label0:
-/// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
-/// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
+/// %sgpr0 = S_OR_SAVEEXEC_B64 %exec // Restore the exec mask for the Then block
+/// %exec = S_XOR_B64 %sgpr0, %exec // Clear live bits from saved exec mask
/// S_BRANCH_EXECZ label1 // Use our branch optimization
/// // instruction again.
-/// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
+/// %vgpr0 = V_SUB_F32 %vgpr0, %vgpr // Do the THEN block
/// label1:
-/// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
+/// %exec = S_OR_B64 %exec, %sgpr0 // Re-enable saved exec mask bits
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Tue Nov 28 09:15:09 2017
@@ -1832,12 +1832,12 @@ void ARMFrameLowering::determineCalleeSa
if (!HasFP) {
if (SavedRegs.test(ARM::R7)) {
--RegDeficit;
- DEBUG(dbgs() << "%R7 is saved low register, RegDeficit = "
+ DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = "
<< RegDeficit << "\n");
} else {
AvailableRegs.push_back(ARM::R7);
DEBUG(dbgs()
- << "%R7 is non-saved low register, adding to AvailableRegs\n");
+ << "%r7 is non-saved low register, adding to AvailableRegs\n");
}
}
@@ -1859,11 +1859,11 @@ void ARMFrameLowering::determineCalleeSa
MF.getFrameInfo().isReturnAddressTaken())) {
if (SavedRegs.test(ARM::LR)) {
--RegDeficit;
- DEBUG(dbgs() << "%LR is saved register, RegDeficit = " << RegDeficit
+ DEBUG(dbgs() << "%lr is saved register, RegDeficit = " << RegDeficit
<< "\n");
} else {
AvailableRegs.push_back(ARM::LR);
- DEBUG(dbgs() << "%LR is not saved, adding to AvailableRegs\n");
+ DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n");
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Nov 28 09:15:09 2017
@@ -1697,7 +1697,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairO
if (OddReg == EvenReg && EvenDeadKill) {
// If the two source operands are the same, the kill marker is
// probably on the first one. e.g.
- // t2STRDi8 %R5<kill>, %R5, %R9<kill>, 0, 14, %reg0
+ // t2STRDi8 %r5<kill>, %r5, %r9<kill>, 0, 14, %reg0
EvenDeadKill = false;
OddDeadKill = true;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp Tue Nov 28 09:15:09 2017
@@ -368,7 +368,7 @@ void HexagonBlockRanges::computeInitialL
}
}
// Defs and clobbers can overlap, e.g.
- // %D0<def,dead> = COPY %vreg5, %R0<imp-def>, %R1<imp-def>
+ // %d0<def,dead> = COPY %vreg5, %r0<imp-def>, %r1<imp-def>
for (RegisterRef R : Defs)
Clobbers.erase(R);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp Tue Nov 28 09:15:09 2017
@@ -1974,7 +1974,7 @@ bool HexagonConstEvaluator::evaluate(con
{
const MachineOperand &VO = MI.getOperand(1);
// The operand of CONST32 can be a blockaddress, e.g.
- // %vreg0<def> = CONST32 <blockaddress(@eat, %L)>
+ // %vreg0<def> = CONST32 <blockaddress(@eat, %l)>
// Do this check for all instructions for safety.
if (!VO.isImm())
return false;
@@ -3144,7 +3144,7 @@ bool HexagonConstEvaluator::rewriteHexBr
BrI.setDesc(JD);
while (BrI.getNumOperands() > 0)
BrI.RemoveOperand(0);
- // This ensures that all implicit operands (e.g. %R31<imp-def>, etc)
+ // This ensures that all implicit operands (e.g. %r31<imp-def>, etc)
// are present in the rewritten branch.
for (auto &Op : NI->operands())
BrI.addOperand(Op);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp Tue Nov 28 09:15:09 2017
@@ -351,11 +351,11 @@ bool HexagonCopyToCombine::isSafeToMoveT
// kill flag for a register (a removeRegisterKilled() analogous to
// addRegisterKilled) that handles aliased register correctly.
// * or has a killed aliased register use of I1's use reg
- // %D4<def> = A2_tfrpi 16
- // %R6<def> = A2_tfr %R9
- // %R8<def> = KILL %R8, %D4<imp-use,kill>
+ // %d4<def> = A2_tfrpi 16
+ // %r6<def> = A2_tfr %r9
+ // %r8<def> = KILL %r8, %d4<imp-use,kill>
// If we want to move R6 = across the KILL instruction we would have
- // to remove the %D4<imp-use,kill> operand. For now, we are
+ // to remove the %d4<imp-use,kill> operand. For now, we are
// conservative and disallow the move.
// we can't move I1 across it.
if (MI.isDebugValue()) {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp Tue Nov 28 09:15:09 2017
@@ -27,8 +27,8 @@
//
// %vreg40<def> = L2_loadrub_io %vreg39<kill>, 1
// %vreg41<def> = S2_tstbit_i %vreg40<kill>, 0
-// J2_jumpt %vreg41<kill>, <BB#5>, %PC<imp-def,dead>
-// J2_jump <BB#4>, %PC<imp-def,dead>
+// J2_jumpt %vreg41<kill>, <BB#5>, %pc<imp-def,dead>
+// J2_jump <BB#4>, %pc<imp-def,dead>
// Successors according to CFG: BB#4(62) BB#5(62)
//
// BB#4: derived from LLVM BB %if.then
@@ -42,8 +42,8 @@
// %vreg12<def> = PHI %vreg6, <BB#3>, %vreg11, <BB#4>
// %vreg13<def> = A2_addp %vreg7, %vreg12
// %vreg42<def> = C2_cmpeqi %vreg9, 10
-// J2_jumpf %vreg42<kill>, <BB#3>, %PC<imp-def,dead>
-// J2_jump <BB#6>, %PC<imp-def,dead>
+// J2_jumpf %vreg42<kill>, <BB#3>, %pc<imp-def,dead>
+// J2_jump <BB#6>, %pc<imp-def,dead>
// Successors according to CFG: BB#6(4) BB#3(124)
//
// would become:
@@ -55,8 +55,8 @@
// %vreg46<def> = PS_pselect %vreg41, %vreg6, %vreg11
// %vreg13<def> = A2_addp %vreg7, %vreg46
// %vreg42<def> = C2_cmpeqi %vreg9, 10
-// J2_jumpf %vreg42<kill>, <BB#3>, %PC<imp-def,dead>
-// J2_jump <BB#6>, %PC<imp-def,dead>
+// J2_jumpf %vreg42<kill>, <BB#3>, %pc<imp-def,dead>
+// J2_jump <BB#6>, %pc<imp-def,dead>
// Successors according to CFG: BB#6 BB#3
#include "Hexagon.h"
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp Tue Nov 28 09:15:09 2017
@@ -1720,7 +1720,7 @@ bool HexagonHardwareLoops::fixupInductio
MachineOperand &MO = PredDef->getOperand(i);
if (MO.isReg()) {
// Skip all implicit references. In one case there was:
- // %vreg140<def> = FCMPUGT32_rr %vreg138, %vreg139, %USR<imp-use>
+ // %vreg140<def> = FCMPUGT32_rr %vreg138, %vreg139, %usr<imp-use>
if (MO.isImplicit())
continue;
if (MO.isUse()) {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Tue Nov 28 09:15:09 2017
@@ -1616,8 +1616,8 @@ DFAPacketizer *HexagonInstrInfo::CreateT
}
// Inspired by this pair:
-// %R13<def> = L2_loadri_io %R29, 136; mem:LD4[FixedStack0]
-// S2_storeri_io %R29, 132, %R1<kill>; flags: mem:ST4[FixedStack1]
+// %r13<def> = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
+// S2_storeri_io %r29, 132, %r1<kill>; flags: mem:ST4[FixedStack1]
// Currently AA considers the addresses in these instructions to be aliasing.
bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
@@ -3516,7 +3516,7 @@ HexagonII::SubInstructionGroup HexagonIn
case Hexagon::EH_RETURN_JMPR:
case Hexagon::PS_jmpret:
// jumpr r31
- // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
+ // Actual form JMPR %pc<imp-def>, %r31<imp-use>, %r0<imp-use,internal>.
DstReg = MI.getOperand(0).getReg();
if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
return HexagonII::HSIG_L2;
@@ -3706,7 +3706,7 @@ HexagonII::SubInstructionGroup HexagonIn
case Hexagon::C2_cmovenewif:
// if ([!]P0[.new]) Rd = #0
// Actual form:
- // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
+ // %r16<def> = C2_cmovenewit %p0<internal>, 0, %r16<imp-use,undef>;
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
if (isIntRegForSubInst(DstReg) &&
Modified: llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp Tue Nov 28 09:15:09 2017
@@ -129,9 +129,9 @@ static bool canBeFeederToNewValueJump(co
// using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
// before the callsite of this function
// But we can not as it comes in the following fashion.
- // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
- // %R0<def> = KILL %R0, %D0<imp-use,kill>
- // %P0<def> = CMPEQri %R0<kill>, 0
+ // %d0<def> = Hexagon_S2_lsr_r_p %d0<kill>, %r2<kill>
+ // %r0<def> = KILL %r0, %d0<imp-use,kill>
+ // %p0<def> = CMPEQri %r0<kill>, 0
// Hence, we need to check if it's a KILL instruction.
if (II->getOpcode() == TargetOpcode::KILL)
return false;
@@ -193,9 +193,9 @@ static bool commonChecksToProhibitNewVal
// to new value jump. If they are in the path, bail out.
// KILL sets kill flag on the opcode. It also sets up a
// single register, out of pair.
- // %D0<def> = S2_lsr_r_p %D0<kill>, %R2<kill>
- // %R0<def> = KILL %R0, %D0<imp-use,kill>
- // %P0<def> = C2_cmpeqi %R0<kill>, 0
+ // %d0<def> = S2_lsr_r_p %d0<kill>, %r2<kill>
+ // %r0<def> = KILL %r0, %d0<imp-use,kill>
+ // %p0<def> = C2_cmpeqi %r0<kill>, 0
// PHI can be anything after RA.
// COPY can remateriaze things in between feeder, compare and nvj.
if (MII->getOpcode() == TargetOpcode::KILL ||
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp Tue Nov 28 09:15:09 2017
@@ -20,12 +20,12 @@
// ...
// %vreg16<def> = NOT_p %vreg15<kill>
// ...
-// JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
+// JMP_c %vreg16<kill>, <BB#1>, %pc<imp-def,dead>
//
// Into
// %vreg15<def> = CMPGTrr %vreg6, %vreg2;
// ...
-// JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
+// JMP_cNot %vreg15<kill>, <BB#1>, %pc<imp-def,dead>;
//
// Note: The peephole pass makes the instrucstions like
// %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Tue Nov 28 09:15:09 2017
@@ -220,21 +220,21 @@ void HexagonSubtarget::CallMutation::app
shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
DAG->SUnits[su].addPred(SDep(&DAG->SUnits[su-1], SDep::Barrier));
// Prevent redundant register copies between two calls, which are caused by
- // both the return value and the argument for the next call being in %R0.
+ // both the return value and the argument for the next call being in %r0.
// Example:
// 1: <call1>
- // 2: %VregX = COPY %R0
- // 3: <use of %VregX>
- // 4: %R0 = ...
+ // 2: %vregX = COPY %r0
+ // 3: <use of %vregX>
+ // 4: %r0 = ...
// 5: <call2>
// The scheduler would often swap 3 and 4, so an additional register is
// needed. This code inserts a Barrier dependence between 3 & 4 to prevent
- // this. The same applies for %D0 and %V0/%W0, which are also handled.
+ // this. The same applies for %d0 and %v0/%w0, which are also handled.
else if (SchedRetvalOptimization) {
const MachineInstr *MI = DAG->SUnits[su].getInstr();
if (MI->isCopy() && (MI->readsRegister(Hexagon::R0, &TRI) ||
MI->readsRegister(Hexagon::V0, &TRI))) {
- // %vregX = COPY %R0
+ // %vregX = COPY %r0
VRegHoldingRet = MI->getOperand(0).getReg();
RetRegister = MI->getOperand(1).getReg();
LastUseOfRet = nullptr;
@@ -242,7 +242,7 @@ void HexagonSubtarget::CallMutation::app
// <use of %vregX>
LastUseOfRet = &DAG->SUnits[su];
else if (LastUseOfRet && MI->definesRegister(RetRegister, &TRI))
- // %R0 = ...
+ // %r0 = ...
DAG->SUnits[su].addPred(SDep(LastUseOfRet, SDep::Barrier));
}
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Tue Nov 28 09:15:09 2017
@@ -772,8 +772,8 @@ bool HexagonPacketizerList::canPromoteTo
// If data definition is because of implicit definition of the register,
// do not newify the store. Eg.
- // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
- // S2_storerh_io %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
+ // %r9<def> = ZXTH %r12, %d6<imp-use>, %r12<imp-def>
+ // S2_storerh_io %r8, 2, %r12<kill>; mem:ST2[%scevgep343]
for (auto &MO : PacketMI.operands()) {
if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))
return false;
@@ -787,8 +787,8 @@ bool HexagonPacketizerList::canPromoteTo
// Handle imp-use of super reg case. There is a target independent side
// change that should prevent this situation but I am handling it for
// just-in-case. For example, we cannot newify R2 in the following case:
- // %R3<def> = A2_tfrsi 0;
- // S2_storeri_io %R0<kill>, 0, %R2<kill>, %D1<imp-use,kill>;
+ // %r3<def> = A2_tfrsi 0;
+ // S2_storeri_io %r0<kill>, 0, %r2<kill>, %d1<imp-use,kill>;
for (auto &MO : MI.operands()) {
if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
return false;
@@ -892,12 +892,12 @@ bool HexagonPacketizerList::canPromoteTo
// Go through the packet instructions and search for an anti dependency between
// them and DepReg from MI. Consider this case:
// Trying to add
-// a) %R1<def> = TFRI_cdNotPt %P3, 2
+// a) %r1<def> = TFRI_cdNotPt %p3, 2
// to this packet:
// {
-// b) %P0<def> = C2_or %P3<kill>, %P0<kill>
-// c) %P3<def> = C2_tfrrp %R23
-// d) %R1<def> = C2_cmovenewit %P3, 4
+// b) %p0<def> = C2_or %p3<kill>, %p0<kill>
+// c) %p3<def> = C2_tfrrp %r23
+// d) %r1<def> = C2_cmovenewit %p3, 4
// }
// The P3 from a) and d) will be complements after
// a)'s P3 is converted to .new form
@@ -962,11 +962,11 @@ bool HexagonPacketizerList::arePredicate
// One corner case deals with the following scenario:
// Trying to add
- // a) %R24<def> = A2_tfrt %P0, %R25
+ // a) %r24<def> = A2_tfrt %p0, %r25
// to this packet:
// {
- // b) %R25<def> = A2_tfrf %P0, %R24
- // c) %P0<def> = C2_cmpeqi %R26, 1
+ // b) %r25<def> = A2_tfrf %p0, %r24
+ // c) %p0<def> = C2_cmpeqi %r26, 1
// }
//
// On general check a) and b) are complements, but presence of c) will
@@ -1543,7 +1543,7 @@ bool HexagonPacketizerList::isLegalToPac
// There are certain anti-dependencies that cannot be ignored.
// Specifically:
- // J2_call ... %R0<imp-def> ; SUJ
+ // J2_call ... %r0<imp-def> ; SUJ
// R0 = ... ; SUI
// Those cannot be packetized together, since the call will observe
// the effect of the assignment to R0.
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp Tue Nov 28 09:15:09 2017
@@ -272,7 +272,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa
case Hexagon::J2_jumpr:
case Hexagon::PS_jmpret:
// jumpr r31
- // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
+ // Actual form JMPR %pc<imp-def>, %r31<imp-use>, %r0<imp-use,internal>.
DstReg = MCI.getOperand(0).getReg();
if (Hexagon::R31 == DstReg)
return HexagonII::HSIG_L2;
@@ -471,7 +471,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa
case Hexagon::C2_cmovenewif:
// if ([!]P0[.new]) Rd = #0
// Actual form:
- // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
+ // %r16<def> = C2_cmovenewit %p0<internal>, 0, %r16<imp-use,undef>;
DstReg = MCI.getOperand(0).getReg(); // Rd
PredReg = MCI.getOperand(1).getReg(); // P0
if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp Tue Nov 28 09:15:09 2017
@@ -113,9 +113,9 @@ bool llvm::HexagonMCShuffle(MCContext &C
if (!HexagonMCInstrInfo::bundleSize(MCB)) {
// There once was a bundle:
- // BUNDLE %D2<imp-def>, %R4<imp-def>, %R5<imp-def>, %D7<imp-def>, ...
- // * %D2<def> = IMPLICIT_DEF; flags:
- // * %D7<def> = IMPLICIT_DEF; flags:
+ // BUNDLE %d2<imp-def>, %r4<imp-def>, %r5<imp-def>, %d7<imp-def>, ...
+ // * %d2<def> = IMPLICIT_DEF; flags:
+ // * %d7<def> = IMPLICIT_DEF; flags:
// After the IMPLICIT_DEFs were removed by the asm printer, the bundle
// became empty.
DEBUG(dbgs() << "Skipping empty bundle");
@@ -137,9 +137,9 @@ llvm::HexagonMCShuffle(MCContext &Contex
if (!HexagonMCInstrInfo::bundleSize(MCB)) {
// There once was a bundle:
- // BUNDLE %D2<imp-def>, %R4<imp-def>, %R5<imp-def>, %D7<imp-def>, ...
- // * %D2<def> = IMPLICIT_DEF; flags:
- // * %D7<def> = IMPLICIT_DEF; flags:
+ // BUNDLE %d2<imp-def>, %r4<imp-def>, %r5<imp-def>, %d7<imp-def>, ...
+ // * %d2<def> = IMPLICIT_DEF; flags:
+ // * %d7<def> = IMPLICIT_DEF; flags:
// After the IMPLICIT_DEFs were removed by the asm printer, the bundle
// became empty.
DEBUG(dbgs() << "Skipping empty bundle");
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Tue Nov 28 09:15:09 2017
@@ -480,7 +480,7 @@ MipsInstrInfo::genInstrWithNewOpc(unsign
MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
// For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
- // immediate 0 as an operand and requires the removal of it's %RA<imp-def>
+ // immediate 0 as an operand and requires the removal of it's %ra<imp-def>
// implicit operand as copying the implicit operations of the instructio we're
// looking at will give us the correct flags.
if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue Nov 28 09:15:09 2017
@@ -521,7 +521,7 @@ void PPCAsmPrinter::EmitInstruction(cons
return LowerPATCHPOINT(SM, *MI);
case PPC::MoveGOTtoLR: {
- // Transform %LR = MoveGOTtoLR
+ // Transform %lr = MoveGOTtoLR
// Into this: bl _GLOBAL_OFFSET_TABLE_ at local-4
// _GLOBAL_OFFSET_TABLE_ at local-4 (instruction preceding
// _GLOBAL_OFFSET_TABLE_) has exactly one instruction:
@@ -542,7 +542,7 @@ void PPCAsmPrinter::EmitInstruction(cons
}
case PPC::MovePCtoLR:
case PPC::MovePCtoLR8: {
- // Transform %LR = MovePCtoLR
+ // Transform %lr = MovePCtoLR
// Into this, where the label is the PIC base:
// bl L1$pb
// L1$pb:
@@ -560,9 +560,9 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::UpdateGBR: {
- // Transform %Rd = UpdateGBR(%Rt, %Ri)
- // Into: lwz %Rt, .L0$poff - .L0$pb(%Ri)
- // add %Rd, %Rt, %Ri
+ // Transform %rd = UpdateGBR(%rt, %ri)
+ // Into: lwz %rt, .L0$poff - .L0$pb(%ri)
+ // add %rd, %rt, %ri
// Get the offset from the GOT Base Register to the GOT
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
MCSymbol *PICOffset =
@@ -577,7 +577,7 @@ void PPCAsmPrinter::EmitInstruction(cons
const MCOperand TR = TmpInst.getOperand(1);
const MCOperand PICR = TmpInst.getOperand(0);
- // Step 1: lwz %Rt, .L$poff - .L$pb(%Ri)
+ // Step 1: lwz %rt, .L$poff - .L$pb(%ri)
TmpInst.getOperand(1) =
MCOperand::createExpr(MCBinaryExpr::createSub(Exp, PB, OutContext));
TmpInst.getOperand(0) = TR;
@@ -592,7 +592,7 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::LWZtoc: {
- // Transform %R3 = LWZtoc <ga:@min1>, %R2
+ // Transform %r3 = LWZtoc <ga:@min1>, %r2
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
// Change the opcode to LWZ, and the global address operand to be a
@@ -636,7 +636,7 @@ void PPCAsmPrinter::EmitInstruction(cons
case PPC::LDtocCPT:
case PPC::LDtocBA:
case PPC::LDtoc: {
- // Transform %X3 = LDtoc <ga:@min1>, %X2
+ // Transform %x3 = LDtoc <ga:@min1>, %x2
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
// Change the opcode to LD, and the global address operand to be a
@@ -667,7 +667,7 @@ void PPCAsmPrinter::EmitInstruction(cons
}
case PPC::ADDIStocHA: {
- // Transform %Xd = ADDIStocHA %X2, <ga:@sym>
+ // Transform %xd = ADDIStocHA %x2, <ga:@sym>
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
// Change the opcode to ADDIS8. If the global address is external, has
@@ -714,7 +714,7 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::LDtocL: {
- // Transform %Xd = LDtocL <ga:@sym>, %Xs
+ // Transform %xd = LDtocL <ga:@sym>, %xs
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
// Change the opcode to LD. If the global address is external, has
@@ -757,7 +757,7 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::ADDItocL: {
- // Transform %Xd = ADDItocL %Xs, <ga:@sym>
+ // Transform %xd = ADDItocL %xs, <ga:@sym>
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
// Change the opcode to ADDI8. If the global address is external, then
@@ -788,8 +788,8 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::ADDISgotTprelHA: {
- // Transform: %Xd = ADDISgotTprelHA %X2, <ga:@sym>
- // Into: %Xd = ADDIS8 %X2, sym at got@tlsgd at ha
+ // Transform: %xd = ADDISgotTprelHA %x2, <ga:@sym>
+ // Into: %xd = ADDIS8 %x2, sym at got@tlsgd at ha
assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
@@ -805,7 +805,7 @@ void PPCAsmPrinter::EmitInstruction(cons
}
case PPC::LDgotTprelL:
case PPC::LDgotTprelL32: {
- // Transform %Xd = LDgotTprelL <ga:@sym>, %Xs
+ // Transform %xd = LDgotTprelL <ga:@sym>, %xs
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
// Change the opcode to LD.
@@ -866,8 +866,8 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::ADDIStlsgdHA: {
- // Transform: %Xd = ADDIStlsgdHA %X2, <ga:@sym>
- // Into: %Xd = ADDIS8 %X2, sym at got@tlsgd at ha
+ // Transform: %xd = ADDIStlsgdHA %x2, <ga:@sym>
+ // Into: %xd = ADDIS8 %x2, sym at got@tlsgd at ha
assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
@@ -882,11 +882,11 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::ADDItlsgdL:
- // Transform: %Xd = ADDItlsgdL %Xs, <ga:@sym>
- // Into: %Xd = ADDI8 %Xs, sym at got@tlsgd at l
+ // Transform: %xd = ADDItlsgdL %xs, <ga:@sym>
+ // Into: %xd = ADDI8 %xs, sym at got@tlsgd at l
case PPC::ADDItlsgdL32: {
- // Transform: %Rd = ADDItlsgdL32 %Rs, <ga:@sym>
- // Into: %Rd = ADDI %Rs, sym at got@tlsgd
+ // Transform: %rd = ADDItlsgdL32 %rs, <ga:@sym>
+ // Into: %rd = ADDI %rs, sym at got@tlsgd
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
@@ -902,17 +902,17 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::GETtlsADDR:
- // Transform: %X3 = GETtlsADDR %X3, <ga:@sym>
+ // Transform: %x3 = GETtlsADDR %x3, <ga:@sym>
// Into: BL8_NOP_TLS __tls_get_addr(sym at tlsgd)
case PPC::GETtlsADDR32: {
- // Transform: %R3 = GETtlsADDR32 %R3, <ga:@sym>
+ // Transform: %r3 = GETtlsADDR32 %r3, <ga:@sym>
// Into: BL_TLS __tls_get_addr(sym at tlsgd)@PLT
EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSGD);
return;
}
case PPC::ADDIStlsldHA: {
- // Transform: %Xd = ADDIStlsldHA %X2, <ga:@sym>
- // Into: %Xd = ADDIS8 %X2, sym at got@tlsld at ha
+ // Transform: %xd = ADDIStlsldHA %x2, <ga:@sym>
+ // Into: %xd = ADDIS8 %x2, sym at got@tlsld at ha
assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
@@ -927,11 +927,11 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::ADDItlsldL:
- // Transform: %Xd = ADDItlsldL %Xs, <ga:@sym>
- // Into: %Xd = ADDI8 %Xs, sym at got@tlsld at l
+ // Transform: %xd = ADDItlsldL %xs, <ga:@sym>
+ // Into: %xd = ADDI8 %xs, sym at got@tlsld at l
case PPC::ADDItlsldL32: {
- // Transform: %Rd = ADDItlsldL32 %Rs, <ga:@sym>
- // Into: %Rd = ADDI %Rs, sym at got@tlsld
+ // Transform: %rd = ADDItlsldL32 %rs, <ga:@sym>
+ // Into: %rd = ADDI %rs, sym at got@tlsld
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
@@ -947,20 +947,20 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::GETtlsldADDR:
- // Transform: %X3 = GETtlsldADDR %X3, <ga:@sym>
+ // Transform: %x3 = GETtlsldADDR %x3, <ga:@sym>
// Into: BL8_NOP_TLS __tls_get_addr(sym at tlsld)
case PPC::GETtlsldADDR32: {
- // Transform: %R3 = GETtlsldADDR32 %R3, <ga:@sym>
+ // Transform: %r3 = GETtlsldADDR32 %r3, <ga:@sym>
// Into: BL_TLS __tls_get_addr(sym at tlsld)@PLT
EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSLD);
return;
}
case PPC::ADDISdtprelHA:
- // Transform: %Xd = ADDISdtprelHA %Xs, <ga:@sym>
- // Into: %Xd = ADDIS8 %Xs, sym at dtprel@ha
+ // Transform: %xd = ADDISdtprelHA %xs, <ga:@sym>
+ // Into: %xd = ADDIS8 %xs, sym at dtprel@ha
case PPC::ADDISdtprelHA32: {
- // Transform: %Rd = ADDISdtprelHA32 %Rs, <ga:@sym>
- // Into: %Rd = ADDIS %Rs, sym at dtprel@ha
+ // Transform: %rd = ADDISdtprelHA32 %rs, <ga:@sym>
+ // Into: %rd = ADDIS %rs, sym at dtprel@ha
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
@@ -976,11 +976,11 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::ADDIdtprelL:
- // Transform: %Xd = ADDIdtprelL %Xs, <ga:@sym>
- // Into: %Xd = ADDI8 %Xs, sym at dtprel@l
+ // Transform: %xd = ADDIdtprelL %xs, <ga:@sym>
+ // Into: %xd = ADDI8 %xs, sym at dtprel@l
case PPC::ADDIdtprelL32: {
- // Transform: %Rd = ADDIdtprelL32 %Rs, <ga:@sym>
- // Into: %Rd = ADDI %Rs, sym at dtprel@l
+ // Transform: %rd = ADDIdtprelL32 %rs, <ga:@sym>
+ // Into: %rd = ADDI %rs, sym at dtprel@l
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
@@ -997,8 +997,8 @@ void PPCAsmPrinter::EmitInstruction(cons
case PPC::MFOCRF:
case PPC::MFOCRF8:
if (!Subtarget->hasMFOCRF()) {
- // Transform: %R3 = MFOCRF %CR7
- // Into: %R3 = MFCR ;; cr7
+ // Transform: %r3 = MFOCRF %cr7
+ // Into: %r3 = MFCR ;; cr7
unsigned NewOpcode =
MI->getOpcode() == PPC::MFOCRF ? PPC::MFCR : PPC::MFCR8;
OutStreamer->AddComment(PPCInstPrinter::
@@ -1011,8 +1011,8 @@ void PPCAsmPrinter::EmitInstruction(cons
case PPC::MTOCRF:
case PPC::MTOCRF8:
if (!Subtarget->hasMFOCRF()) {
- // Transform: %CR7 = MTOCRF %R3
- // Into: MTCRF mask, %R3 ;; cr7
+ // Transform: %cr7 = MTOCRF %r3
+ // Into: MTCRF mask, %r3 ;; cr7
unsigned NewOpcode =
MI->getOpcode() == PPC::MTOCRF ? PPC::MTCRF : PPC::MTCRF8;
unsigned Mask = 0x80 >> OutContext.getRegisterInfo()
Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp Tue Nov 28 09:15:09 2017
@@ -60,11 +60,11 @@ namespace llvm {
/// expands to the following machine code:
///
/// BB#0: derived from LLVM BB %entry
-/// Live Ins: %F1 %F3 %X6
+/// Live Ins: %f1 %f3 %x6
/// <SNIP1>
-/// %vreg0<def> = COPY %F1; F8RC:%vreg0
+/// %vreg0<def> = COPY %f1; F8RC:%vreg0
/// %vreg5<def> = CMPLWI %vreg4<kill>, 0; CRRC:%vreg5 GPRC:%vreg4
-/// %vreg8<def> = LXSDX %ZERO8, %vreg7<kill>, %RM<imp-use>;
+/// %vreg8<def> = LXSDX %zero8, %vreg7<kill>, %rm<imp-use>;
/// mem:LD8[ConstantPool] F8RC:%vreg8 G8RC:%vreg7
/// BCC 76, %vreg5, <BB#2>; CRRC:%vreg5
/// Successors according to CFG: BB#1(?%) BB#2(?%)
@@ -90,7 +90,7 @@ namespace llvm {
/// %vreg13<def> = PHI %vreg12, <BB#3>, %vreg2, <BB#2>;
/// F8RC:%vreg13,%vreg12,%vreg2
/// <SNIP3>
-/// BLR8 %LR8<imp-use>, %RM<imp-use>, %F1<imp-use>
+/// BLR8 %lr8<imp-use>, %rm<imp-use>, %f1<imp-use>
///
/// When this pattern is detected, branch coalescing will try to collapse
/// it by moving code in BB#2 to BB#0 and/or BB#4 and removing BB#3.
@@ -98,11 +98,11 @@ namespace llvm {
/// If all conditions are meet, IR should collapse to:
///
/// BB#0: derived from LLVM BB %entry
-/// Live Ins: %F1 %F3 %X6
+/// Live Ins: %f1 %f3 %x6
/// <SNIP1>
-/// %vreg0<def> = COPY %F1; F8RC:%vreg0
+/// %vreg0<def> = COPY %f1; F8RC:%vreg0
/// %vreg5<def> = CMPLWI %vreg4<kill>, 0; CRRC:%vreg5 GPRC:%vreg4
-/// %vreg8<def> = LXSDX %ZERO8, %vreg7<kill>, %RM<imp-use>;
+/// %vreg8<def> = LXSDX %zero8, %vreg7<kill>, %rm<imp-use>;
/// mem:LD8[ConstantPool] F8RC:%vreg8 G8RC:%vreg7
/// <SNIP2>
/// BCC 76, %vreg5, <BB#4>; CRRC:%vreg5
@@ -120,7 +120,7 @@ namespace llvm {
/// %vreg13<def> = PHI %vreg12, <BB#1>, %vreg2, <BB#0>;
/// F8RC:%vreg13,%vreg12,%vreg2
/// <SNIP3>
-/// BLR8 %LR8<imp-use>, %RM<imp-use>, %F1<imp-use>
+/// BLR8 %lr8<imp-use>, %rm<imp-use>, %f1<imp-use>
///
/// Branch Coalescing does not split blocks, it moves everything in the same
/// direction ensuring it does not break use/definition semantics.
Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Tue Nov 28 09:15:09 2017
@@ -1991,9 +1991,9 @@ unsigned PPCFastISel::PPCMaterializeGV(c
// or externally available linkage, a non-local function address, or a
// jump table address (not yet needed), or if we are generating code
// for large code model, we generate:
- // LDtocL(GV, ADDIStocHA(%X2, GV))
+ // LDtocL(GV, ADDIStocHA(%x2, GV))
// Otherwise we generate:
- // ADDItocL(ADDIStocHA(%X2, GV), GV)
+ // ADDItocL(ADDIStocHA(%x2, GV), GV)
// Either way, start with the ADDIStocHA:
unsigned HighPartReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Nov 28 09:15:09 2017
@@ -3218,9 +3218,9 @@ void PPCDAGToDAGISel::Select(SDNode *N)
// The first source operand is a TargetGlobalAddress or a TargetJumpTable.
// If it must be toc-referenced according to PPCSubTarget, we generate:
- // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
+ // LDtocL(<ga:@sym>, ADDIStocHA(%x2, <ga:@sym>))
// Otherwise we generate:
- // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
+ // ADDItocL(ADDIStocHA(%x2, <ga:@sym>), <ga:@sym>)
SDValue GA = N->getOperand(0);
SDValue TOCbase = N->getOperand(1);
SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Tue Nov 28 09:15:09 2017
@@ -262,7 +262,7 @@ namespace llvm {
/// local dynamic TLS on PPC32.
PPC32_PICGOT,
- /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
+ /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
/// TLS model, produces an ADDIS8 instruction that adds the GOT
/// base to sym\@got\@tprel\@ha.
ADDIS_GOT_TPREL_HA,
@@ -281,18 +281,18 @@ namespace llvm {
/// TLS sequence.
ADD_TLS,
- /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
+ /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
/// model, produces an ADDIS8 instruction that adds the GOT base
/// register to sym\@got\@tlsgd\@ha.
ADDIS_TLSGD_HA,
- /// %X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
+ /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
/// model, produces an ADDI8 instruction that adds G8RReg to
/// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
/// ADDIS_TLSGD_L_ADDR until after register assignment.
ADDI_TLSGD_L,
- /// %X3 = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
+ /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
/// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
/// ADDIS_TLSGD_L_ADDR until after register assignment.
GET_TLS_ADDR,
@@ -302,18 +302,18 @@ namespace llvm {
/// register assignment.
ADDI_TLSGD_L_ADDR,
- /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
+ /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
/// model, produces an ADDIS8 instruction that adds the GOT base
/// register to sym\@got\@tlsld\@ha.
ADDIS_TLSLD_HA,
- /// %X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
+ /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
/// model, produces an ADDI8 instruction that adds G8RReg to
/// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
/// ADDIS_TLSLD_L_ADDR until after register assignment.
ADDI_TLSLD_L,
- /// %X3 = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
+ /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
/// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
/// ADDIS_TLSLD_L_ADDR until after register assignment.
GET_TLSLD_ADDR,
@@ -323,7 +323,7 @@ namespace llvm {
/// following register assignment.
ADDI_TLSLD_L_ADDR,
- /// G8RC = ADDIS_DTPREL_HA %X3, Symbol - For the local-dynamic TLS
+ /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
/// model, produces an ADDIS8 instruction that adds X3 to
/// sym\@dtprel\@ha.
ADDIS_DTPREL_HA,
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Nov 28 09:15:09 2017
@@ -2315,10 +2315,10 @@ PPCInstrInfo::isSignOrZeroExtended(const
// For a method return value, we check the ZExt/SExt flags in attribute.
// We assume the following code sequence for method call.
- // ADJCALLSTACKDOWN 32, %R1<imp-def,dead>, %R1<imp-use>
+ // ADJCALLSTACKDOWN 32, %r1<imp-def,dead>, %r1<imp-use>
// BL8_NOP <ga:@func>,...
- // ADJCALLSTACKUP 32, 0, %R1<imp-def,dead>, %R1<imp-use>
- // %vreg5<def> = COPY %X3; G8RC:%vreg5
+ // ADJCALLSTACKUP 32, 0, %r1<imp-def,dead>, %r1<imp-use>
+ // %vreg5<def> = COPY %x3; G8RC:%vreg5
if (SrcReg == PPC::X3) {
const MachineBasicBlock *MBB = MI.getParent();
MachineBasicBlock::const_instr_iterator II =
Modified: llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp Tue Nov 28 09:15:09 2017
@@ -79,8 +79,8 @@ bool PPCQPXLoadSplat::runOnMachineFuncti
}
// We're looking for a sequence like this:
- // %F0<def> = LFD 0, %X3<kill>, %QF0<imp-def>; mem:LD8[%a](tbaa=!2)
- // %QF1<def> = QVESPLATI %QF0<kill>, 0, %RM<imp-use>
+ // %f0<def> = LFD 0, %x3<kill>, %qf0<imp-def>; mem:LD8[%a](tbaa=!2)
+ // %qf1<def> = QVESPLATI %qf0<kill>, 0, %rm<imp-use>
for (auto SI = Splats.begin(); SI != Splats.end();) {
MachineInstr *SMI = *SI;
Modified: llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp Tue Nov 28 09:15:09 2017
@@ -92,18 +92,18 @@ protected:
// ...
// %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
// %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
- // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
+ // %rm<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
// ...
// %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19,
- // %RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19
+ // %rm<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19
// ...
// Where we can eliminate the copy by changing from the A-type to the
// M-type instruction. Specifically, for this example, this means:
// %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
- // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
+ // %rm<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
// is replaced by:
// %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9,
- // %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9
+ // %rm<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9
// and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
@@ -150,7 +150,7 @@ protected:
// walking the MIs we may as well test liveness here.
//
// FIXME: There is a case that occurs in practice, like this:
- // %vreg9<def> = COPY %F1; VSSRC:%vreg9
+ // %vreg9<def> = COPY %f1; VSSRC:%vreg9
// ...
// %vreg6<def> = COPY %vreg9; VSSRC:%vreg6,%vreg9
// %vreg7<def> = COPY %vreg9; VSSRC:%vreg7,%vreg9
Modified: llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp Tue Nov 28 09:15:09 2017
@@ -306,8 +306,8 @@ bool SparcFrameLowering::isLeafProc(Mach
return !(MFI.hasCalls() // has calls
|| MRI.isPhysRegUsed(SP::L0) // Too many registers needed
- || MRI.isPhysRegUsed(SP::O6) // %SP is used
- || hasFP(MF)); // need %FP
+ || MRI.isPhysRegUsed(SP::O6) // %sp is used
+ || hasFP(MF)); // need %fp
}
void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
Modified: llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp Tue Nov 28 09:15:09 2017
@@ -436,8 +436,8 @@ bool SystemZElimCompare::optimizeCompare
// Also do a forward search to handle cases where an instruction after the
// compare can be converted like
//
- // LTEBRCompare %F0S, %F0S, %CC<imp-def> LTEBRCompare %F0S, %F0S, %CC<imp-def>
- // %F2S<def> = LER %F0S
+ // LTEBRCompare %f0s, %f0s, %cc<imp-def> LTEBRCompare %f0s, %f0s, %cc<imp-def>
+ // %f2s<def> = LER %f0s
//
MBBI = Compare, MBBE = MBB.end();
while (++MBBI != MBBE) {
Modified: llvm/trunk/lib/Target/X86/README-SSE.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/README-SSE.txt (original)
+++ llvm/trunk/lib/Target/X86/README-SSE.txt Tue Nov 28 09:15:09 2017
@@ -145,15 +145,15 @@ This is the llvm code after instruction
cond_next140 (0xa910740, LLVM BB @0xa90beb0):
%reg1078 = MOV32ri -3
- %reg1079 = ADD32rm %reg1078, %reg1068, 1, %NOREG, 0
- %reg1037 = MOV32rm %reg1024, 1, %NOREG, 40
+ %reg1079 = ADD32rm %reg1078, %reg1068, 1, %noreg, 0
+ %reg1037 = MOV32rm %reg1024, 1, %noreg, 40
%reg1080 = IMUL32rr %reg1079, %reg1037
- %reg1081 = MOV32rm %reg1058, 1, %NOREG, 0
+ %reg1081 = MOV32rm %reg1058, 1, %noreg, 0
%reg1038 = LEA32r %reg1081, 1, %reg1080, -3
- %reg1036 = MOV32rm %reg1024, 1, %NOREG, 32
+ %reg1036 = MOV32rm %reg1024, 1, %noreg, 32
%reg1082 = SHL32ri %reg1038, 4
%reg1039 = ADD32rr %reg1036, %reg1082
- %reg1083 = MOVAPSrm %reg1059, 1, %NOREG, 0
+ %reg1083 = MOVAPSrm %reg1059, 1, %noreg, 0
%reg1034 = SHUFPSrr %reg1083, %reg1083, 170
%reg1032 = SHUFPSrr %reg1083, %reg1083, 0
%reg1035 = SHUFPSrr %reg1083, %reg1083, 255
@@ -166,32 +166,32 @@ cond_next140 (0xa910740, LLVM BB @0xa90b
Still ok. After register allocation:
cond_next140 (0xa910740, LLVM BB @0xa90beb0):
- %EAX = MOV32ri -3
- %EDX = MOV32rm <fi#3>, 1, %NOREG, 0
- ADD32rm %EAX<def&use>, %EDX, 1, %NOREG, 0
- %EDX = MOV32rm <fi#7>, 1, %NOREG, 0
- %EDX = MOV32rm %EDX, 1, %NOREG, 40
- IMUL32rr %EAX<def&use>, %EDX
- %ESI = MOV32rm <fi#5>, 1, %NOREG, 0
- %ESI = MOV32rm %ESI, 1, %NOREG, 0
- MOV32mr <fi#4>, 1, %NOREG, 0, %ESI
- %EAX = LEA32r %ESI, 1, %EAX, -3
- %ESI = MOV32rm <fi#7>, 1, %NOREG, 0
- %ESI = MOV32rm %ESI, 1, %NOREG, 32
- %EDI = MOV32rr %EAX
- SHL32ri %EDI<def&use>, 4
- ADD32rr %EDI<def&use>, %ESI
- %XMM0 = MOVAPSrm %ECX, 1, %NOREG, 0
- %XMM1 = MOVAPSrr %XMM0
- SHUFPSrr %XMM1<def&use>, %XMM1, 170
- %XMM2 = MOVAPSrr %XMM0
- SHUFPSrr %XMM2<def&use>, %XMM2, 0
- %XMM3 = MOVAPSrr %XMM0
- SHUFPSrr %XMM3<def&use>, %XMM3, 255
- SHUFPSrr %XMM0<def&use>, %XMM0, 85
- %EBX = MOV32rr %EDI
- AND32ri8 %EBX<def&use>, 15
- CMP32ri8 %EBX, 0
+ %eax = MOV32ri -3
+ %edx = MOV32rm <fi#3>, 1, %noreg, 0
+ ADD32rm %eax<def&use>, %edx, 1, %noreg, 0
+ %edx = MOV32rm <fi#7>, 1, %noreg, 0
+ %edx = MOV32rm %edx, 1, %noreg, 40
+ IMUL32rr %eax<def&use>, %edx
+ %esi = MOV32rm <fi#5>, 1, %noreg, 0
+ %esi = MOV32rm %esi, 1, %noreg, 0
+ MOV32mr <fi#4>, 1, %noreg, 0, %esi
+ %eax = LEA32r %esi, 1, %eax, -3
+ %esi = MOV32rm <fi#7>, 1, %noreg, 0
+ %esi = MOV32rm %esi, 1, %noreg, 32
+ %edi = MOV32rr %eax
+ SHL32ri %edi<def&use>, 4
+ ADD32rr %edi<def&use>, %esi
+ %xmm0 = MOVAPSrm %ecx, 1, %noreg, 0
+ %xmm1 = MOVAPSrr %xmm0
+ SHUFPSrr %xmm1<def&use>, %xmm1, 170
+ %xmm2 = MOVAPSrr %xmm0
+ SHUFPSrr %xmm2<def&use>, %xmm2, 0
+ %xmm3 = MOVAPSrr %xmm0
+ SHUFPSrr %xmm3<def&use>, %xmm3, 255
+ SHUFPSrr %xmm0<def&use>, %xmm0, 85
+ %ebx = MOV32rr %edi
+ AND32ri8 %ebx<def&use>, 15
+ CMP32ri8 %ebx, 0
JE mbb<cond_next204,0xa914d30>
This looks really bad. The problem is shufps is a destructive opcode. Since it
Modified: llvm/trunk/lib/Target/X86/README-X86-64.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-X86-64.txt?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/README-X86-64.txt (original)
+++ llvm/trunk/lib/Target/X86/README-X86-64.txt Tue Nov 28 09:15:09 2017
@@ -103,13 +103,13 @@ LBB1_3: ## bb
Before regalloc, we have:
- %reg1025<def> = IMUL32rri8 %reg1024, 45, %EFLAGS<imp-def>
+ %reg1025<def> = IMUL32rri8 %reg1024, 45, %eflags<imp-def>
JMP mbb<bb2,0x203afb0>
Successors according to CFG: 0x203afb0 (#3)
bb1: 0x203af60, LLVM BB @0x1e02310, ID#2:
Predecessors according to CFG: 0x203aec0 (#0)
- %reg1026<def> = IMUL32rri8 %reg1024, 78, %EFLAGS<imp-def>
+ %reg1026<def> = IMUL32rri8 %reg1024, 78, %eflags<imp-def>
Successors according to CFG: 0x203afb0 (#3)
bb2: 0x203afb0, LLVM BB @0x1e02340, ID#3:
Modified: llvm/trunk/lib/Target/X86/X86CallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CallingConv.td (original)
+++ llvm/trunk/lib/Target/X86/X86CallingConv.td Tue Nov 28 09:15:09 2017
@@ -500,7 +500,7 @@ def CC_X86_64_C : CallingConv<[
// A SwiftError is passed in R12.
CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
- // For Swift Calling Convention, pass sret in %RAX.
+ // For Swift Calling Convention, pass sret in %rax.
CCIfCC<"CallingConv::Swift",
CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>,
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Nov 28 09:15:09 2017
@@ -1976,9 +1976,9 @@ bool X86FastISel::X86SelectDivRem(const
// Generate the DIV/IDIV instruction.
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(OpEntry.OpDivRem)).addReg(Op1Reg);
- // For i8 remainder, we can't reference AH directly, as we'll end
- // up with bogus copies like %R9B = COPY %AH. Reference AX
- // instead to prevent AH references in a REX instruction.
+ // For i8 remainder, we can't reference ah directly, as we'll end
+ // up with bogus copies like %r9b = COPY %ah. Reference ax
+ // instead to prevent ah references in a rex instruction.
//
// The current assumption of the fast register allocator is that isel
// won't generate explicit references to the GR8_NOREX registers. If
Modified: llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp Tue Nov 28 09:15:09 2017
@@ -189,17 +189,17 @@ bool FixupBWInstPass::runOnMachineFuncti
/// So, it handles pattern like this:
///
/// BB#2: derived from LLVM BB %if.then
-/// Live Ins: %RDI
+/// Live Ins: %rdi
/// Predecessors according to CFG: BB#0
-/// %AX<def> = MOV16rm %RDI<kill>, 1, %noreg, 0, %noreg, %EAX<imp-def>; mem:LD2[%p]
-/// No %EAX<imp-use>
+/// %ax<def> = MOV16rm %rdi<kill>, 1, %noreg, 0, %noreg, %eax<imp-def>; mem:LD2[%p]
+/// No %eax<imp-use>
/// Successors according to CFG: BB#3(?%)
///
/// BB#3: derived from LLVM BB %if.end
-/// Live Ins: %EAX Only %AX is actually live
+/// Live Ins: %eax Only %ax is actually live
/// Predecessors according to CFG: BB#2 BB#1
-/// %AX<def> = KILL %AX, %EAX<imp-use,kill>
-/// RET 0, %AX
+/// %ax<def> = KILL %ax, %eax<imp-use,kill>
+/// RET 0, %ax
static bool isLive(const MachineInstr &MI,
const LivePhysRegs &LiveRegs,
const TargetRegisterInfo *TRI,
Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Tue Nov 28 09:15:09 2017
@@ -516,7 +516,7 @@ void FPS::setupBlockStack() {
// Push the fixed live-in registers.
for (unsigned i = Bundle.FixCount; i > 0; --i) {
- DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
+ DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %fp"
<< unsigned(Bundle.FixStack[i-1]) << '\n');
pushReg(Bundle.FixStack[i-1]);
}
@@ -893,7 +893,7 @@ void FPS::adjustLiveRegs(unsigned Mask,
while (Kills && Defs) {
unsigned KReg = countTrailingZeros(Kills);
unsigned DReg = countTrailingZeros(Defs);
- DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
+ DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg << "\n");
std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
std::swap(RegMap[KReg], RegMap[DReg]);
Kills &= ~(1 << KReg);
@@ -907,7 +907,7 @@ void FPS::adjustLiveRegs(unsigned Mask,
unsigned KReg = getStackEntry(0);
if (!(Kills & (1 << KReg)))
break;
- DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
+ DEBUG(dbgs() << "Popping %fp" << KReg << "\n");
popStackAfter(I2);
Kills &= ~(1 << KReg);
}
@@ -916,7 +916,7 @@ void FPS::adjustLiveRegs(unsigned Mask,
// Manually kill the rest.
while (Kills) {
unsigned KReg = countTrailingZeros(Kills);
- DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
+ DEBUG(dbgs() << "Killing %fp" << KReg << "\n");
freeStackSlotBefore(I, KReg);
Kills &= ~(1 << KReg);
}
@@ -924,7 +924,7 @@ void FPS::adjustLiveRegs(unsigned Mask,
// Load zeros for all the imp-defs.
while(Defs) {
unsigned DReg = countTrailingZeros(Defs);
- DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
+ DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n");
BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
pushReg(DReg);
Defs &= ~(1 << DReg);
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Nov 28 09:15:09 2017
@@ -10879,7 +10879,7 @@ X86InstrInfo::getOutliningType(MachineIn
// FIXME: There are instructions which are being manually built without
// explicit uses/defs so we also have to check the MCInstrDesc. We should be
// able to remove the extra checks once those are fixed up. For example,
- // sometimes we might get something like %RAX<def> = POP64r 1. This won't be
+ // sometimes we might get something like %rax<def> = POP64r 1. This won't be
// caught by modifiesRegister or readsRegister even though the instruction
// really ought to be formed so that modifiesRegister/readsRegister would
// catch it.
Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Tue Nov 28 09:15:09 2017
@@ -961,7 +961,7 @@ void X86AsmPrinter::LowerPATCHABLE_OP(co
// This is an optimization that lets us get away without emitting a nop in
// many cases.
//
- // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %R9) takes two
+ // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two
// bytes too, so the check on MinSize is important.
MCI.setOpcode(X86::PUSH64rmr);
} else {
Modified: llvm/trunk/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll Tue Nov 28 09:15:09 2017
@@ -296,7 +296,7 @@ declare double @hh(double) #1
; Check that we correctly deal with repeated operands.
; The following testcase creates:
-; %D1<def> = FADDDrr %D0<kill>, %D0
+; %d1<def> = FADDDrr %d0<kill>, %d0
; We'll get a crash if we naively look at the first operand, remove it
; from the substitution list then look at the second operand.
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll Tue Nov 28 09:15:09 2017
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm64-apple-ios -verify-machineinstrs | FileCheck %s
; LdStOpt bug created illegal instruction:
-; %D1<def>, %D2<def> = LDPSi %X0, 1
+; %d1<def>, %d2<def> = LDPSi %x0, 1
; rdar://11512047
%0 = type opaque
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll Tue Nov 28 09:15:09 2017
@@ -10,8 +10,8 @@
;
; CHECK: Before post-MI-sched:
; CHECK-LABEL: # Machine code for function test1:
-; CHECK: SU(2): STRWui %WZR
-; CHECK: SU(3): %X21<def>, %X20<def> = LDPXi %SP
+; CHECK: SU(2): STRWui %wzr
+; CHECK: SU(3): %x21<def>, %x20<def> = LDPXi %sp
; CHECK: Predecessors:
; CHECK-NEXT: SU(0): Out
; CHECK-NEXT: SU(0): Out
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll Tue Nov 28 09:15:09 2017
@@ -3,7 +3,7 @@
; Check that the dead register definition pass is considering implicit defs.
; When rematerializing through truncates, the coalescer may produce instructions
; with dead defs, but live implicit-defs of subregs:
-; E.g. %X1<def, dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32
+; E.g. %x1<def, dead> = MOVi64imm 2, %w1<imp-def>; %x1:GPR64, %w1:GPR32
; These instructions are live, and their definitions should not be rewritten.
;
; <rdar://problem/16492408>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll Tue Nov 28 09:15:09 2017
@@ -9,11 +9,11 @@
; CHECK: Successors:
; CHECK-NEXT: SU(5): Data Latency=4 Reg=%vreg2
; CHECK-NEXT: SU(4): Ord Latency=0
-; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
+; CHECK: SU(3): STRWui %wzr, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
; CHECK: Successors:
; CHECK: SU(4): Ord Latency=0
-; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
-; CHECK: SU(5): %W0<def> = COPY %vreg2; GPR32:%vreg2
+; CHECK: SU(4): STRWui %wzr, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
+; CHECK: SU(5): %w0<def> = COPY %vreg2; GPR32:%vreg2
; CHECK: ** ScheduleDAGMI::schedule picking next node
define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
entry:
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll Tue Nov 28 09:15:09 2017
@@ -8,11 +8,11 @@
; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
;
; CHECK-LABEL: # Machine code for function foo:
-; CHECK: SU(2): %W{{[0-9]+}}<def>, %W{{[0-9]+}}<def> = LDPWi
+; CHECK: SU(2): %w{{[0-9]+}}<def>, %w{{[0-9]+}}<def> = LDPWi
; CHECK: Successors:
; CHECK-NOT: ch SU(4)
; CHECK: SU(3)
-; CHECK: SU(4): STRWui %WZR, %X{{[0-9]+}}
+; CHECK: SU(4): STRWui %wzr, %x{{[0-9]+}}
define i32 @foo() {
entry:
%0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4
Modified: llvm/trunk/test/CodeGen/AArch64/loh.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/loh.mir?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/loh.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/loh.mir Tue Nov 28 09:15:09 2017
@@ -22,14 +22,14 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK: Adding MCLOH_AdrpAdrp:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3>
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4>
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g4>
; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g2>
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g2>
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
- ; CHECK-NEXT: %X0<def> = ADRP <ga:@g0>
- ; CHECK-NEXT: %X0<def> = ADRP <ga:@g1>
+ ; CHECK-NEXT: %x0<def> = ADRP <ga:@g0>
+ ; CHECK-NEXT: %x0<def> = ADRP <ga:@g1>
%x0 = ADRP target-flags(aarch64-page) @g0
%x0 = ADRP target-flags(aarch64-page) @g1
%x1 = ADRP target-flags(aarch64-page) @g2
@@ -38,11 +38,11 @@ body: |
bb.1:
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
- ; CHECK-NEXT: %X20<def> = ADRP <ga:@g0>
- ; CHECK-NEXT: %X3<def> = ADDXri %X20, <ga:@g0>
+ ; CHECK-NEXT: %x20<def> = ADRP <ga:@g0>
+ ; CHECK-NEXT: %x3<def> = ADDXri %x20, <ga:@g0>
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g0>
- ; CHECK-NEXT: %X1<def> = ADDXri %X1, <ga:@g0>
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g0>
+ ; CHECK-NEXT: %x1<def> = ADDXri %x1, <ga:@g0>
%x1 = ADRP target-flags(aarch64-page) @g0
%x9 = SUBXri undef %x11, 5, 0 ; should not affect MCLOH formation
%x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0, 0
@@ -73,11 +73,11 @@ body: |
bb.5:
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
- ; CHECK-NEXT: %X5<def> = ADRP <ga:@g2>
- ; CHECK-NEXT: %S6<def> = LDRSui %X5, <ga:@g2>
+ ; CHECK-NEXT: %x5<def> = ADRP <ga:@g2>
+ ; CHECK-NEXT: %s6<def> = LDRSui %x5, <ga:@g2>
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
- ; CHECK-NEXT: %X4<def> = ADRP <ga:@g2>
- ; CHECK-NEXT: %X4<def> = LDRXui %X4, <ga:@g2>
+ ; CHECK-NEXT: %x4<def> = ADRP <ga:@g2>
+ ; CHECK-NEXT: %x4<def> = LDRXui %x4, <ga:@g2>
%x4 = ADRP target-flags(aarch64-page) @g2
%x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
%x5 = ADRP target-flags(aarch64-page) @g2
@@ -85,11 +85,11 @@ body: |
bb.6:
; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
- ; CHECK-NEXT: %X5<def> = ADRP <ga:@g2>
- ; CHECK-NEXT: %X6<def> = LDRXui %X5, <ga:@g2>
+ ; CHECK-NEXT: %x5<def> = ADRP <ga:@g2>
+ ; CHECK-NEXT: %x6<def> = LDRXui %x5, <ga:@g2>
; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
- ; CHECK-NEXT: %X4<def> = ADRP <ga:@g2>
- ; CHECK-NEXT: %X4<def> = LDRXui %X4, <ga:@g2>
+ ; CHECK-NEXT: %x4<def> = ADRP <ga:@g2>
+ ; CHECK-NEXT: %x4<def> = LDRXui %x4, <ga:@g2>
%x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
%x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
%x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
@@ -104,24 +104,24 @@ body: |
bb.8:
; CHECK-NEXT: Adding MCLOH_AdrpAddLdr:
- ; CHECK-NEXT: %X7<def> = ADRP <ga:@g3>[TF=1]
- ; CHECK-NEXT: %X8<def> = ADDXri %X7, <ga:@g3>
- ; CHECK-NEXT: %D1<def> = LDRDui %X8, 8
+ ; CHECK-NEXT: %x7<def> = ADRP <ga:@g3>[TF=1]
+ ; CHECK-NEXT: %x8<def> = ADDXri %x7, <ga:@g3>
+ ; CHECK-NEXT: %d1<def> = LDRDui %x8, 8
%x7 = ADRP target-flags(aarch64-page) @g3
%x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3, 0
%d1 = LDRDui %x8, 8
bb.9:
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
- ; CHECK-NEXT: %X3<def> = ADRP <ga:@g3>
- ; CHECK-NEXT: %X3<def> = ADDXri %X3, <ga:@g3>
+ ; CHECK-NEXT: %x3<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x3<def> = ADDXri %x3, <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
- ; CHECK-NEXT: %X5<def> = ADRP <ga:@g3>
- ; CHECK-NEXT: %X2<def> = ADDXri %X5, <ga:@g3>
+ ; CHECK-NEXT: %x5<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x2<def> = ADDXri %x5, <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpAddStr:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3>
- ; CHECK-NEXT: %X1<def> = ADDXri %X1, <ga:@g3>
- ; CHECK-NEXT: STRXui %XZR, %X1, 16
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x1<def> = ADDXri %x1, <ga:@g3>
+ ; CHECK-NEXT: STRXui %xzr, %x1, 16
%x1 = ADRP target-flags(aarch64-page) @g3
%x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3, 0
STRXui %xzr, %x1, 16
@@ -138,12 +138,12 @@ body: |
bb.10:
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
- ; CHECK-NEXT: %X2<def> = ADRP <ga:@g3>
- ; CHECK-NEXT: %X2<def> = LDRXui %X2, <ga:@g3>
+ ; CHECK-NEXT: %x2<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x2<def> = LDRXui %x2, <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpLdrGotLdr:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4>
- ; CHECK-NEXT: %X1<def> = LDRXui %X1, <ga:@g4>
- ; CHECK-NEXT: %X1<def> = LDRXui %X1, 24
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g4>
+ ; CHECK-NEXT: %x1<def> = LDRXui %x1, <ga:@g4>
+ ; CHECK-NEXT: %x1<def> = LDRXui %x1, 24
%x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
%x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
%x1 = LDRXui %x1, 24
@@ -154,12 +154,12 @@ body: |
bb.11:
; CHECK-NEXT: Adding MCLOH_AdrpLdr
- ; CHECK-NEXT: %X5<def> = ADRP <ga:@g1>
- ; CHECK-NEXT: %X5<def> = LDRXui %X5, <ga:@g1>
+ ; CHECK-NEXT: %x5<def> = ADRP <ga:@g1>
+ ; CHECK-NEXT: %x5<def> = LDRXui %x5, <ga:@g1>
; CHECK-NEXT: Adding MCLOH_AdrpLdrGotStr:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4>
- ; CHECK-NEXT: %X1<def> = LDRXui %X1, <ga:@g4>
- ; CHECK-NEXT: STRXui %XZR, %X1, 32
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g4>
+ ; CHECK-NEXT: %x1<def> = LDRXui %x1, <ga:@g4>
+ ; CHECK-NEXT: STRXui %xzr, %x1, 32
%x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
%x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
STRXui %xzr, %x1, 32
@@ -171,9 +171,9 @@ body: |
bb.12:
; CHECK-NOT: MCLOH_AdrpAdrp
; CHECK: Adding MCLOH_AdrpAddLdr
- ; %X9<def> = ADRP <ga:@g4>
- ; %X9<def> = ADDXri %X9, <ga:@g4>
- ; %X5<def> = LDRXui %X9, 0
+ ; %x9<def> = ADRP <ga:@g4>
+ ; %x9<def> = ADDXri %x9, <ga:@g4>
+ ; %x5<def> = LDRXui %x9, 0
%x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4
%x9 = ADDXri %x9, target-flags(aarch64-pageoff, aarch64-got) @g4, 0
%x5 = LDRXui %x9, 0
Modified: llvm/trunk/test/CodeGen/AArch64/machine-copy-prop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/machine-copy-prop.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/machine-copy-prop.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/machine-copy-prop.ll Tue Nov 28 09:15:09 2017
@@ -2,12 +2,12 @@
; This file check a bug in MachineCopyPropagation pass. The last COPY will be
; incorrectly removed if the machine instructions are as follows:
-; %Q5_Q6<def> = COPY %Q2_Q3
-; %D5<def> =
-; %D3<def> =
-; %D3<def> = COPY %D6
+; %q5_q6<def> = COPY %q2_q3
+; %d5<def> =
+; %d3<def> =
+; %d3<def> = COPY %d6
; This is caused by a bug in function SourceNoLongerAvailable(), which fails to
-; remove the relationship of D6 and "%Q5_Q6<def> = COPY %Q2_Q3".
+; remove the relationship of D6 and "%q5_q6<def> = COPY %q2_q3".
@failed = internal unnamed_addr global i1 false
Modified: llvm/trunk/test/CodeGen/AArch64/phi-dbg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/phi-dbg.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/phi-dbg.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/phi-dbg.ll Tue Nov 28 09:15:09 2017
@@ -30,7 +30,7 @@ define i32 @func(i32) #0 !dbg !8 {
; CHECK: ldr w[[REG:[0-9]+]], [sp, #8]
; CHECK-NEXT: .Ltmp
call void @llvm.dbg.value(metadata i32 %.0, i64 0, metadata !15, metadata !13), !dbg !16
-; CHECK-NEXT: //DEBUG_VALUE: func:c <- %W[[REG]]
+; CHECK-NEXT: //DEBUG_VALUE: func:c <- %w[[REG]]
%5 = add nsw i32 %.0, %0, !dbg !22
call void @llvm.dbg.value(metadata i32 %5, i64 0, metadata !15, metadata !13), !dbg !16
ret i32 %5, !dbg !23
Modified: llvm/trunk/test/CodeGen/AArch64/scheduledag-constreg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/scheduledag-constreg.mir?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/scheduledag-constreg.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/scheduledag-constreg.mir Tue Nov 28 09:15:09 2017
@@ -7,16 +7,16 @@
# Check that the instructions are not dependent on each other, even though
# they all read/write to the zero register.
# CHECK-LABEL: MI Scheduling
-# CHECK: SU(0): %WZR<def,dead> = SUBSWri %W1, 0, 0, %NZCV<imp-def,dead>
+# CHECK: SU(0): %wzr<def,dead> = SUBSWri %w1, 0, 0, %nzcv<imp-def,dead>
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
-# CHECK: SU(1): %W2<def> = COPY %WZR
+# CHECK: SU(1): %w2<def> = COPY %wzr
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
-# CHECK: SU(2): %WZR<def,dead> = SUBSWri %W3, 0, 0, %NZCV<imp-def,dead>
+# CHECK: SU(2): %wzr<def,dead> = SUBSWri %w3, 0, 0, %nzcv<imp-def,dead>
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
-# CHECK: SU(3): %W4<def> = COPY %WZR
+# CHECK: SU(3): %w4<def> = COPY %wzr
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
name: func
Modified: llvm/trunk/test/CodeGen/AMDGPU/lds-output-queue.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/lds-output-queue.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/lds-output-queue.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/lds-output-queue.ll Tue Nov 28 09:15:09 2017
@@ -45,20 +45,20 @@ declare void @llvm.r600.group.barrier()
; %2 = load i32, i32 addrspace(1)* %in
;
; The instruction selection phase will generate ISA that looks like this:
-; %OQAP = LDS_READ_RET
-; %vreg0 = MOV %OQAP
+; %oqap = LDS_READ_RET
+; %vreg0 = MOV %oqap
; %vreg1 = VTX_READ_32
; %vreg2 = ADD_INT %vreg1, %vreg0
;
; The bottom scheduler will schedule the two ALU instructions first:
;
; UNSCHEDULED:
-; %OQAP = LDS_READ_RET
+; %oqap = LDS_READ_RET
; %vreg1 = VTX_READ_32
;
; SCHEDULED:
;
-; vreg0 = MOV %OQAP
+; vreg0 = MOV %oqap
; vreg2 = ADD_INT %vreg1, %vreg2
;
; The lack of proper aliasing results in the local memory read (LDS_READ_RET)
@@ -67,14 +67,14 @@ declare void @llvm.r600.group.barrier()
; final program which looks like this:
;
; Alu clause:
-; %OQAP = LDS_READ_RET
+; %oqap = LDS_READ_RET
; VTX clause:
; %vreg1 = VTX_READ_32
; Alu clause:
-; vreg0 = MOV %OQAP
+; vreg0 = MOV %oqap
; vreg2 = ADD_INT %vreg1, %vreg2
;
-; This is an illegal program because the OQAP def and use know occur in
+; This is an illegal program because the oqap def and use know occur in
; different ALU clauses.
;
; This test checks this scenario and makes sure it doesn't result in an
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.dbg.value.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.dbg.value.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.dbg.value.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.dbg.value.ll Tue Nov 28 09:15:09 2017
@@ -4,7 +4,7 @@
; CHECK: s_load_dwordx2 s[4:5]
; FIXME: Why is the SGPR4_SGPR5 reference being removed from DBG_VALUE?
-; CHECK: ; kill: %SGPR4_SGPR5<def> %SGPR4_SGPR5<kill>
+; CHECK: ; kill: %sgpr4_sgpr5<def> %sgpr4_sgpr5<kill>
; CHECK-NEXT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- undef
; CHECK: buffer_store_dword
Modified: llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure.mir?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure.mir Tue Nov 28 09:15:09 2017
@@ -4,7 +4,7 @@
# Check there is no SReg_32 pressure created by DS_* instructions because of M0 use
# CHECK: ScheduleDAGMILive::schedule starting
-# CHECK: SU({{.*}} = DS_READ_B32 {{.*}} %M0<imp-use>, %EXEC<imp-use>
+# CHECK: SU({{.*}} = DS_READ_B32 {{.*}} %m0<imp-use>, %exec<imp-use>
# CHECK: Pressure Diff : {{$}}
# CHECK: SU({{.*}} DS_WRITE_B32
Modified: llvm/trunk/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll Tue Nov 28 09:15:09 2017
@@ -4,7 +4,7 @@
define void @vst(i8* %m, [4 x i64] %v) {
entry:
; CHECK: vst:
-; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,kill>
+; CHECK: VST1d64Q %r{{[0-9]+}}<kill>, 8, %d{{[0-9]+}}, pred:14, pred:%noreg, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use,kill>
%v0 = extractvalue [4 x i64] %v, 0
%v1 = extractvalue [4 x i64] %v, 1
@@ -37,7 +37,7 @@ entry:
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
; CHECK: vtbx4:
-; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
+; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use>
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
Modified: llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll Tue Nov 28 09:15:09 2017
@@ -9,5 +9,5 @@ entry:
ret void
}
-; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %LR<imp-def>, %SP<imp-use>, %R4<imp-use,kill>, %R4<imp-def>, %R12<imp-def,dead>, %CPSR<imp-def,dead>
+; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %lr<imp-def>, %sp<imp-use>, %r4<imp-use,kill>, %r4<imp-def>, %r12<imp-def,dead>, %cpsr<imp-def,dead>
Modified: llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll Tue Nov 28 09:15:09 2017
@@ -11,7 +11,7 @@ define void @foo(%struct.tag_s* nocaptur
tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, metadata !13, metadata !DIExpression()), !dbg !21
tail call void @llvm.dbg.value(metadata i64 %x, metadata !14, metadata !DIExpression()), !dbg !22
tail call void @llvm.dbg.value(metadata i64 %y, metadata !17, metadata !DIExpression()), !dbg !23
-;CHECK: @DEBUG_VALUE: foo:y <- [DW_OP_plus_uconst 8] [%R7+0]
+;CHECK: @DEBUG_VALUE: foo:y <- [DW_OP_plus_uconst 8] [%r7+0]
tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, metadata !18, metadata !DIExpression()), !dbg !24
tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, metadata !19, metadata !DIExpression()), !dbg !25
%1 = icmp eq %struct.tag_s* %c, null, !dbg !26
Modified: llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll Tue Nov 28 09:15:09 2017
@@ -5,8 +5,8 @@ target triple = "thumbv7-apple-macosx10.
;CHECK: vadd.f32 q4, q8, q8
;CHECK-NEXT: LBB0_1
-;CHECK: @DEBUG_VALUE: x <- %Q4{{$}}
-;CHECK-NEXT: @DEBUG_VALUE: y <- %Q4{{$}}
+;CHECK: @DEBUG_VALUE: x <- %q4{{$}}
+;CHECK-NEXT: @DEBUG_VALUE: y <- %q4{{$}}
;CHECK: beq LBB0_1
Modified: llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir Tue Nov 28 09:15:09 2017
@@ -32,9 +32,9 @@
; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or
; hopefully, triggering an assert).
- ; CHECK: BUNDLE %ITSTATE<imp-def,dead>
- ; CHECK: * DBG_VALUE %R1, %noreg, !"u"
- ; CHECK-NOT: * DBG_VALUE %R1<kill>, %noreg, !"u"
+ ; CHECK: BUNDLE %itstate<imp-def,dead>
+ ; CHECK: * DBG_VALUE %r1, %noreg, !"u"
+ ; CHECK-NOT: * DBG_VALUE %r1<kill>, %noreg, !"u"
declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1
Modified: llvm/trunk/test/CodeGen/BPF/sockex2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/sockex2.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/sockex2.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/sockex2.ll Tue Nov 28 09:15:09 2017
@@ -311,7 +311,7 @@ flow_dissector.exit.thread:
; CHECK-LABEL: bpf_prog2:
; CHECK: r0 = *(u16 *)skb[12] # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00]
; CHECK: r0 = *(u16 *)skb[16] # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00]
-; CHECK: implicit-def: %R1
+; CHECK: implicit-def: %r1
; CHECK: r1 =
; CHECK: call 1 # encoding: [0x85,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
; CHECK: call 2 # encoding: [0x85,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll Tue Nov 28 09:15:09 2017
@@ -161,8 +161,8 @@ declare hidden void @undef_double(i32 %t
define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 {
; ALL-LABEL: thunk_undef_double:
-; O32: # implicit-def: %A2
-; O32: # implicit-def: %A3
+; O32: # implicit-def: %a2
+; O32: # implicit-def: %a3
; NOT-R6C: jr $[[TGT]]
; R6C: jrc $[[TGT]]
Modified: llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll Tue Nov 28 09:15:09 2017
@@ -23,7 +23,7 @@ define void @bn_mul_comba8(i64* nocaptur
; CHECK-NEXT: cmpld 7, 4, 5
; CHECK-NEXT: mfocrf 10, 1
; CHECK-NEXT: rlwinm 10, 10, 29, 31, 31
-; CHECK-NEXT: # implicit-def: %X4
+; CHECK-NEXT: # implicit-def: %x4
; CHECK-NEXT: mr 4, 10
; CHECK-NEXT: clrldi 4, 4, 32
; CHECK-NEXT: std 4, 0(3)
Modified: llvm/trunk/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll Tue Nov 28 09:15:09 2017
@@ -10,7 +10,7 @@ entry:
lnext:
%elementArray = load i32*, i32** %elementArrayPtr, align 8
; CHECK: lwz [[LDREG:[0-9]+]], 124(1) # 4-byte Folded Reload
-; CHECK: # implicit-def: %X[[TEMPREG:[0-9]+]]
+; CHECK: # implicit-def: %x[[TEMPREG:[0-9]+]]
%element = load i32, i32* %elementArray, align 4
; CHECK: mr [[TEMPREG]], [[LDREG]]
; CHECK: clrldi 4, [[TEMPREG]], 32
Modified: llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll Tue Nov 28 09:15:09 2017
@@ -13,5 +13,5 @@ entry:
; Make sure that the MMO on the store has no offset from the byval
; variable itself (we used to have mem:ST8[%v+64]).
-; CHECK: STD %X5<kill>, 176, %X1; mem:ST8[%v](align=16)
+; CHECK: STD %x5<kill>, 176, %x1; mem:ST8[%v](align=16)
Modified: llvm/trunk/test/CodeGen/PowerPC/fp64-to-int16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fp64-to-int16.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fp64-to-int16.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fp64-to-int16.ll Tue Nov 28 09:15:09 2017
@@ -10,7 +10,7 @@ define i1 @Test(double %a) {
; CHECK-NEXT: xori 3, 3, 65534
; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: srwi 3, 3, 5
-; CHECK-NEXT: # implicit-def: %X4
+; CHECK-NEXT: # implicit-def: %x4
; CHECK-NEXT: mr 4, 3
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
Modified: llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll Tue Nov 28 09:15:09 2017
@@ -7,12 +7,12 @@ define signext i32 @fn1(i32 %baz) {
%2 = zext i32 %1 to i64
%3 = shl i64 %2, 48
%4 = ashr exact i64 %3, 48
-; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>;
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %cr0<imp-def,dead>;
; CHECK: CMPLDI
; CHECK: BCC
-; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>;
-; CHECK: COPY %CR0
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %cr0<imp-def>;
+; CHECK: COPY %cr0
; CHECK: BCC
%5 = icmp eq i64 %4, 0
br i1 %5, label %foo, label %bar
@@ -26,8 +26,8 @@ bar:
; CHECK-LABEL: fn2
define signext i32 @fn2(i64 %a, i64 %b) {
-; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0<imp-def>;
-; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0
+; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %cr0<imp-def>;
+; CHECK: [[CREG:[^, ]+]]<def> = COPY %cr0
; CHECK: BCC 12, [[CREG]]<kill>
%1 = or i64 %b, %a
%2 = icmp sgt i64 %1, -1
@@ -42,8 +42,8 @@ bar:
; CHECK-LABEL: fn3
define signext i32 @fn3(i32 %a) {
-; CHECK: ANDIo {{[^, ]+}}, 10, %CR0<imp-def>;
-; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0
+; CHECK: ANDIo {{[^, ]+}}, 10, %cr0<imp-def>;
+; CHECK: [[CREG:[^, ]+]]<def> = COPY %cr0
; CHECK: BCC 76, [[CREG]]<kill>
%1 = and i32 %a, 10
%2 = icmp ne i32 %1, 0
Modified: llvm/trunk/test/CodeGen/PowerPC/quadint-return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/quadint-return.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/quadint-return.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/quadint-return.ll Tue Nov 28 09:15:09 2017
@@ -14,6 +14,6 @@ entry:
; CHECK: ********** Function: foo
; CHECK: ********** FAST REGISTER ALLOCATION **********
-; CHECK: %X3<def> = COPY %vreg
-; CHECK-NEXT: %X4<def> = COPY %vreg
+; CHECK: %x3<def> = COPY %vreg
+; CHECK-NEXT: %x4<def> = COPY %vreg
; CHECK-NEXT: BLR
Modified: llvm/trunk/test/CodeGen/SystemZ/int-div-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-div-01.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-div-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-div-01.ll Tue Nov 28 09:15:09 2017
@@ -1,6 +1,6 @@
; Test 32-bit signed division and remainder.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
declare i32 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/int-div-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-div-02.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-div-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-div-02.ll Tue Nov 28 09:15:09 2017
@@ -1,6 +1,6 @@
; Test 32-bit unsigned division and remainder.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
declare i32 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/int-div-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-div-03.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-div-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-div-03.ll Tue Nov 28 09:15:09 2017
@@ -1,7 +1,7 @@
; Test 64-bit signed division and remainder when the divisor is
; a signed-extended i32.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
declare i64 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/int-div-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-div-04.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-div-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-div-04.ll Tue Nov 28 09:15:09 2017
@@ -1,6 +1,6 @@
; Testg 64-bit signed division and remainder.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
declare i64 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/int-div-05.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-div-05.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-div-05.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-div-05.ll Tue Nov 28 09:15:09 2017
@@ -1,6 +1,6 @@
; Testg 64-bit unsigned division and remainder.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
declare i64 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/int-div-06.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-div-06.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-div-06.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-div-06.ll Tue Nov 28 09:15:09 2017
@@ -1,6 +1,6 @@
; Test that divisions by constants are implemented as multiplications.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
; Check signed 32-bit division.
define i32 @f1(i32 %a) {
Modified: llvm/trunk/test/CodeGen/SystemZ/int-mul-08.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-mul-08.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-mul-08.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-mul-08.ll Tue Nov 28 09:15:09 2017
@@ -1,6 +1,6 @@
; Test high-part i64->i128 multiplications.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
declare i64 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/int-mul-10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-mul-10.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-mul-10.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-mul-10.ll Tue Nov 28 09:15:09 2017
@@ -1,6 +1,6 @@
; Test signed high-part i64->i128 multiplications on z14.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -asm-verbose=0 | FileCheck %s
declare i64 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/pr32505.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/pr32505.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/pr32505.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/pr32505.ll Tue Nov 28 09:15:09 2017
@@ -10,8 +10,8 @@ define <2 x float> @pr32505(<2 x i8> * %
; CHECK-NEXT: lbh %r1, 0(%r2)
; CHECK-NEXT: ldgr %f0, %r1
; CHECK-NEXT: ldgr %f2, %r0
-; CHECK-NEXT: # kill: %F0S<def> %F0S<kill> %F0D<kill>
-; CHECK-NEXT: # kill: %F2S<def> %F2S<kill> %F2D<kill>
+; CHECK-NEXT: # kill: %f0s<def> %f0s<kill> %f0d<kill>
+; CHECK-NEXT: # kill: %f2s<def> %f2s<kill> %f2d<kill>
; CHECK-NEXT: br %r14
%L17 = load <2 x i8>, <2 x i8>* %a
%Se21 = sext <2 x i8> %L17 to <2 x i32>
Modified: llvm/trunk/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll Tue Nov 28 09:15:09 2017
@@ -1,7 +1,7 @@
; RUN: llc < %s -verify-machineinstrs
;
; This test case is transformed into a single basic block by the machine
-; branch folding pass. That makes a complete mess of the %EFLAGS liveness, but
+; branch folding pass. That makes a complete mess of the %eflags liveness, but
; we don't care about liveness this late anyway.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
Modified: llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll Tue Nov 28 09:15:09 2017
@@ -2,8 +2,8 @@
; rdar://7842028
; Do not delete partially dead copy instructions.
-; %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>
-; REP_MOVSD %ECX<imp-def,dead>, %EDI<imp-def,dead>, %ESI<imp-def,dead>, %ECX<imp-use,kill>, %EDI<imp-use,kill>, %ESI<imp-use,kill>
+; %rdi<def,dead> = MOV64rr %rax<kill>, %edi<imp-def>
+; REP_MOVSD %ecx<imp-def,dead>, %edi<imp-def,dead>, %esi<imp-def,dead>, %ecx<imp-use,kill>, %edi<imp-use,kill>, %esi<imp-use,kill>
%struct.F = type { %struct.FC*, i32, i32, i8, i32, i32, i32 }
Modified: llvm/trunk/test/CodeGen/X86/2010-05-12-FastAllocKills.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-12-FastAllocKills.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-05-12-FastAllocKills.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-05-12-FastAllocKills.ll Tue Nov 28 09:15:09 2017
@@ -6,23 +6,23 @@ target triple = "x86_64-apple-darwin"
;BB#5: derived from LLVM BB %bb10
; Predecessors according to CFG: BB#4 BB#5
; %reg1024<def> = MOV_Fp8080 %reg1034
-; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
+; %reg1025<def> = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
; %reg1034<def> = MOV_Fp8080 %reg1025
-; FP_REG_KILL %FP0<imp-def>, %FP1<imp-def>, %FP2<imp-def>, %FP3<imp-def>, %FP4<imp-def>, %FP5<imp-def>, %FP6<imp-def>
+; FP_REG_KILL %fp0<imp-def>, %fp1<imp-def>, %fp2<imp-def>, %fp3<imp-def>, %fp4<imp-def>, %fp5<imp-def>, %fp6<imp-def>
; JMP_4 <BB#5>
; Successors according to CFG: BB#5
;
-; The X86FP pass needs good kill flags, like on %FP0 representing %reg1034:
+; The X86FP pass needs good kill flags, like on %fp0 representing %reg1034:
;BB#5: derived from LLVM BB %bb10
; Predecessors according to CFG: BB#4 BB#5
-; %FP0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
-; %FP1<def> = MOV_Fp8080 %FP0<kill>
-; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
-; %FP0<def> = MOV_Fp8080 %FP2
-; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %FP0<kill>; mem:ST10[FixedStack3](align=4)
-; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %FP1<kill>; mem:ST10[FixedStack4](align=4)
-; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, %FP2<kill>; mem:ST10[FixedStack5](align=4)
-; FP_REG_KILL %FP0<imp-def>, %FP1<imp-def>, %FP2<imp-def>, %FP3<imp-def>, %FP4<imp-def>, %FP5<imp-def>, %FP6<imp-def>
+; %fp0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
+; %fp1<def> = MOV_Fp8080 %fp0<kill>
+; %fp2<def> = MUL_Fp80m32 %fp1, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
+; %fp0<def> = MOV_Fp8080 %fp2
+; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %fp0<kill>; mem:ST10[FixedStack3](align=4)
+; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %fp1<kill>; mem:ST10[FixedStack4](align=4)
+; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, %fp2<kill>; mem:ST10[FixedStack5](align=4)
+; FP_REG_KILL %fp0<imp-def>, %fp1<imp-def>, %fp2<imp-def>, %fp3<imp-def>, %fp4<imp-def>, %fp5<imp-def>, %fp6<imp-def>
; JMP_4 <BB#5>
; Successors according to CFG: BB#5
Modified: llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll Tue Nov 28 09:15:09 2017
@@ -45,7 +45,7 @@ entry:
!18 = !DIFile(filename: "f.c", directory: "/tmp")
!19 = !{}
-;CHECK: DEBUG_VALUE: bar:x <- %E
+;CHECK: DEBUG_VALUE: bar:x <- %e
;CHECK: Ltmp
;CHECK: DEBUG_VALUE: foo:y <- 1{{$}}
!20 = !{i32 1, !"Debug Info Version", i32 3}
Modified: llvm/trunk/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll Tue Nov 28 09:15:09 2017
@@ -11,7 +11,7 @@ target triple = "x86_64-apple-darwin10.2
; Function Attrs: noinline nounwind optsize readnone ssp
define i32 @_ZN3foo3bazEi(%struct.foo* nocapture %this, i32 %x) #0 align 2 !dbg !4 {
entry:
- ; CHECK: DEBUG_VALUE: baz:this <- %RDI{{$}}
+ ; CHECK: DEBUG_VALUE: baz:this <- %rdi{{$}}
tail call void @llvm.dbg.value(metadata %struct.foo* %this, i64 0, metadata !13, metadata !16), !dbg !17
tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !18, metadata !16), !dbg !17
%0 = mul nsw i32 %x, 7, !dbg !19
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll Tue Nov 28 09:15:09 2017
@@ -28,8 +28,8 @@ define i64 @test_add_i64(i64 %arg1, i64
define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
; X64-LABEL: test_add_i32:
; X64: # BB#0:
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
-; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
+; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; X64-NEXT: leal (%rsi,%rdi), %eax
; X64-NEXT: retq
;
@@ -45,10 +45,10 @@ define i32 @test_add_i32(i32 %arg1, i32
define i16 @test_add_i16(i16 %arg1, i16 %arg2) {
; X64-LABEL: test_add_i16:
; X64: # BB#0:
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
-; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
+; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; X64-NEXT: leal (%rsi,%rdi), %eax
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
;
; X32-LABEL: test_add_i16:
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/ext-x86-64.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/ext-x86-64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/ext-x86-64.ll Tue Nov 28 09:15:09 2017
@@ -6,7 +6,7 @@
define i64 @test_zext_i1(i8 %a) {
; X64-LABEL: test_zext_i1:
; X64: # BB#0:
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: andq $1, %rdi
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/ext.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/ext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/ext.ll Tue Nov 28 09:15:09 2017
@@ -13,7 +13,7 @@ define i8 @test_zext_i1toi8(i32 %a) {
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: andb $1, %al
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
%val = trunc i32 %a to i1
%r = zext i1 %val to i8
@@ -31,7 +31,7 @@ define i16 @test_zext_i1toi16(i32 %a) {
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: andw $1, %ax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
%val = trunc i32 %a to i1
%r = zext i1 %val to i16
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/gep.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/gep.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/gep.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/gep.ll Tue Nov 28 09:15:09 2017
@@ -13,7 +13,7 @@ define i32* @test_gep_i8(i32 *%arr, i8 %
;
; X64-LABEL: test_gep_i8:
; X64: # BB#0:
-; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; X64-NEXT: movsbq %sil, %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax
; X64-NEXT: retq
@@ -47,7 +47,7 @@ define i32* @test_gep_i16(i32 *%arr, i16
;
; X64-LABEL: test_gep_i16:
; X64: # BB#0:
-; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; X64-NEXT: movswq %si, %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax
; X64-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/add-sub-nsw-nuw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/add-sub-nsw-nuw.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/add-sub-nsw-nuw.ll (original)
+++ llvm/trunk/test/CodeGen/X86/add-sub-nsw-nuw.ll Tue Nov 28 09:15:09 2017
@@ -10,7 +10,7 @@ define i8 @PR30841(i64 %argc) {
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: negl %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retl
entry:
%or = or i64 %argc, -4294967296
Modified: llvm/trunk/test/CodeGen/X86/add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/add.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/add.ll (original)
+++ llvm/trunk/test/CodeGen/X86/add.ll Tue Nov 28 09:15:09 2017
@@ -176,14 +176,14 @@ define i64 @test6(i64 %A, i32 %B) nounwi
;
; X64-LINUX-LABEL: test6:
; X64-LINUX: # BB#0: # %entry
-; X64-LINUX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; X64-LINUX-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; X64-LINUX-NEXT: shlq $32, %rsi
; X64-LINUX-NEXT: leaq (%rsi,%rdi), %rax
; X64-LINUX-NEXT: retq
;
; X64-WIN32-LABEL: test6:
; X64-WIN32: # BB#0: # %entry
-; X64-WIN32-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
+; X64-WIN32-NEXT: # kill: %edx<def> %edx<kill> %rdx<def>
; X64-WIN32-NEXT: shlq $32, %rdx
; X64-WIN32-NEXT: leaq (%rdx,%rcx), %rax
; X64-WIN32-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/addcarry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/addcarry.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/addcarry.ll (original)
+++ llvm/trunk/test/CodeGen/X86/addcarry.ll Tue Nov 28 09:15:09 2017
@@ -84,7 +84,7 @@ entry:
define i8 @e(i32* nocapture %a, i32 %b) nounwind {
; CHECK-LABEL: e:
; CHECK: # BB#0:
-; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; CHECK-NEXT: movl (%rdi), %ecx
; CHECK-NEXT: leal (%rsi,%rcx), %edx
; CHECK-NEXT: addl %esi, %edx
Modified: llvm/trunk/test/CodeGen/X86/anyext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/anyext.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/anyext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/anyext.ll Tue Nov 28 09:15:09 2017
@@ -8,7 +8,7 @@ define i32 @foo(i32 %p, i8 zeroext %x) n
; X32-LABEL: foo:
; X32: # BB#0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X32-NEXT: divb {{[0-9]+}}(%esp)
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: andl $1, %eax
@@ -17,7 +17,7 @@ define i32 @foo(i32 %p, i8 zeroext %x) n
; X64-LABEL: foo:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %al, %eax
; X64-NEXT: andl $1, %eax
@@ -35,7 +35,7 @@ define i32 @bar(i32 %p, i16 zeroext %x)
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: divw {{[0-9]+}}(%esp)
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<def>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<def>
; X32-NEXT: andl $1, %eax
; X32-NEXT: retl
;
@@ -44,7 +44,7 @@ define i32 @bar(i32 %p, i16 zeroext %x)
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: movl %edi, %eax
; X64-NEXT: divw %si
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<def>
; X64-NEXT: andl $1, %eax
; X64-NEXT: retq
%q = trunc i32 %p to i16
Modified: llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll Tue Nov 28 09:15:09 2017
@@ -93,7 +93,7 @@ define i8 @test_add_1_setcc_slt(i64* %p)
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: lock xaddq %rax, (%rdi)
; CHECK-NEXT: shrq $63, %rax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %RAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %rax<kill>
; CHECK-NEXT: retq
entry:
%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
Modified: llvm/trunk/test/CodeGen/X86/avx-cast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cast.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-cast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-cast.ll Tue Nov 28 09:15:09 2017
@@ -9,7 +9,7 @@
define <8 x float> @castA(<4 x float> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castA:
; AVX: ## BB#0:
-; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; AVX-NEXT: retq
@@ -20,7 +20,7 @@ define <8 x float> @castA(<4 x float> %m
define <4 x double> @castB(<2 x double> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castB:
; AVX: ## BB#0:
-; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; AVX-NEXT: retq
@@ -33,14 +33,14 @@ define <4 x double> @castB(<2 x double>
define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp {
; AVX1-LABEL: castC:
; AVX1: ## BB#0:
-; AVX1-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; AVX1-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; AVX1-NEXT: retq
;
; AVX2-LABEL: castC:
; AVX2: ## BB#0:
-; AVX2-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; AVX2-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; AVX2-NEXT: retq
@@ -54,7 +54,7 @@ define <4 x i64> @castC(<2 x i64> %m) no
define <4 x float> @castD(<8 x float> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castD:
; AVX: ## BB#0:
-; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%shuffle.i = shufflevector <8 x float> %m, <8 x float> %m, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -64,7 +64,7 @@ define <4 x float> @castD(<8 x float> %m
define <2 x i64> @castE(<4 x i64> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castE:
; AVX: ## BB#0:
-; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%shuffle.i = shufflevector <4 x i64> %m, <4 x i64> %m, <2 x i32> <i32 0, i32 1>
@@ -74,7 +74,7 @@ define <2 x i64> @castE(<4 x i64> %m) no
define <2 x double> @castF(<4 x double> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castF:
; AVX: ## BB#0:
-; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%shuffle.i = shufflevector <4 x double> %m, <4 x double> %m, <2 x i32> <i32 0, i32 1>
Modified: llvm/trunk/test/CodeGen/X86/avx-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cmp.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-cmp.ll Tue Nov 28 09:15:09 2017
@@ -197,7 +197,7 @@ define i32 @scalarcmpA() uwtable ssp {
; CHECK-NEXT: vcmpeqsd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovq %xmm0, %rax
; CHECK-NEXT: andl $1, %eax
-; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
+; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<kill>
; CHECK-NEXT: retq
%cmp29 = fcmp oeq double undef, 0.000000e+00
%res = zext i1 %cmp29 to i32
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll Tue Nov 28 09:15:09 2017
@@ -316,12 +316,12 @@ define <4 x i64> @test_mm256_castpd_si25
define <4 x double> @test_mm256_castpd128_pd256(<2 x double> %a0) nounwind {
; X32-LABEL: test_mm256_castpd128_pd256:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castpd128_pd256:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: retq
%res = shufflevector <2 x double> %a0, <2 x double> %a0, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x double> %res
@@ -330,13 +330,13 @@ define <4 x double> @test_mm256_castpd12
define <2 x double> @test_mm256_castpd256_pd128(<4 x double> %a0) nounwind {
; X32-LABEL: test_mm256_castpd256_pd128:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castpd256_pd128:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%res = shufflevector <4 x double> %a0, <4 x double> %a0, <2 x i32> <i32 0, i32 1>
@@ -370,12 +370,12 @@ define <4 x i64> @test_mm256_castps_si25
define <8 x float> @test_mm256_castps128_ps256(<4 x float> %a0) nounwind {
; X32-LABEL: test_mm256_castps128_ps256:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castps128_ps256:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: retq
%res = shufflevector <4 x float> %a0, <4 x float> %a0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x float> %res
@@ -384,13 +384,13 @@ define <8 x float> @test_mm256_castps128
define <4 x float> @test_mm256_castps256_ps128(<8 x float> %a0) nounwind {
; X32-LABEL: test_mm256_castps256_ps128:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castps256_ps128:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%res = shufflevector <8 x float> %a0, <8 x float> %a0, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -400,12 +400,12 @@ define <4 x float> @test_mm256_castps256
define <4 x i64> @test_mm256_castsi128_si256(<2 x i64> %a0) nounwind {
; X32-LABEL: test_mm256_castsi128_si256:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castsi128_si256:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: retq
%res = shufflevector <2 x i64> %a0, <2 x i64> %a0, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i64> %res
@@ -438,13 +438,13 @@ define <8 x float> @test_mm256_castsi256
define <2 x i64> @test_mm256_castsi256_si128(<4 x i64> %a0) nounwind {
; X32-LABEL: test_mm256_castsi256_si128:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castsi256_si128:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%res = shufflevector <4 x i64> %a0, <4 x i64> %a0, <2 x i32> <i32 0, i32 1>
@@ -1043,13 +1043,13 @@ define <4 x i64> @test_mm256_insert_epi6
define <4 x double> @test_mm256_insertf128_pd(<4 x double> %a0, <2 x double> %a1) nounwind {
; X32-LABEL: test_mm256_insertf128_pd:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_insertf128_pd:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; X64-NEXT: retq
%ext = shufflevector <2 x double> %a1, <2 x double> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
@@ -1075,13 +1075,13 @@ define <8 x float> @test_mm256_insertf12
define <4 x i64> @test_mm256_insertf128_si256(<4 x i64> %a0, <2 x i64> %a1) nounwind {
; X32-LABEL: test_mm256_insertf128_si256:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_insertf128_si256:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; X64-NEXT: retq
%ext = shufflevector <2 x i64> %a1, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
@@ -2188,13 +2188,13 @@ define <4 x i64> @test_mm256_set_epi64x(
define <8 x float> @test_mm256_set_m128(<4 x float> %a0, <4 x float> %a1) nounwind {
; X32-LABEL: test_mm256_set_m128:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_set_m128:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-NEXT: retq
%res = shufflevector <4 x float> %a1, <4 x float> %a0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -2204,13 +2204,13 @@ define <8 x float> @test_mm256_set_m128(
define <4 x double> @test_mm256_set_m128d(<2 x double> %a0, <2 x double> %a1) nounwind {
; X32-LABEL: test_mm256_set_m128d:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_set_m128d:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-NEXT: retq
%arg0 = bitcast <2 x double> %a0 to <4 x float>
@@ -2223,13 +2223,13 @@ define <4 x double> @test_mm256_set_m128
define <4 x i64> @test_mm256_set_m128i(<2 x i64> %a0, <2 x i64> %a1) nounwind {
; X32-LABEL: test_mm256_set_m128i:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_set_m128i:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-NEXT: retq
%arg0 = bitcast <2 x i64> %a0 to <4 x float>
@@ -2825,13 +2825,13 @@ define <4 x i64> @test_mm256_setr_epi64x
define <8 x float> @test_mm256_setr_m128(<4 x float> %a0, <4 x float> %a1) nounwind {
; X32-LABEL: test_mm256_setr_m128:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_setr_m128:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X64-NEXT: retq
%res = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -2841,13 +2841,13 @@ define <8 x float> @test_mm256_setr_m128
define <4 x double> @test_mm256_setr_m128d(<2 x double> %a0, <2 x double> %a1) nounwind {
; X32-LABEL: test_mm256_setr_m128d:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_setr_m128d:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X64-NEXT: retq
%arg0 = bitcast <2 x double> %a0 to <4 x float>
@@ -2860,13 +2860,13 @@ define <4 x double> @test_mm256_setr_m12
define <4 x i64> @test_mm256_setr_m128i(<2 x i64> %a0, <2 x i64> %a1) nounwind {
; X32-LABEL: test_mm256_setr_m128i:
; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_setr_m128i:
; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X64-NEXT: retq
%arg0 = bitcast <2 x i64> %a0 to <4 x float>
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll Tue Nov 28 09:15:09 2017
@@ -39,7 +39,7 @@ define <8 x i32> @test_x86_avx_vinsertf1
define <8 x i32> @test_x86_avx_vinsertf128_si_256_2(<8 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_2:
; CHECK: # BB#0:
-; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 2)
@@ -88,7 +88,7 @@ declare <4 x i32> @llvm.x86.avx.vextract
define <2 x double> @test_x86_avx_extractf128_pd_256_2(<4 x double> %a0) {
; CHECK-LABEL: test_x86_avx_extractf128_pd_256_2:
; CHECK: # BB#0:
-; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret{{[l|q]}}
%res = call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a0, i8 2)
Modified: llvm/trunk/test/CodeGen/X86/avx-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-load-store.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-load-store.ll Tue Nov 28 09:15:09 2017
@@ -85,7 +85,7 @@ define <8 x float> @mov00(<8 x float> %v
; CHECK_O0-LABEL: mov00:
; CHECK_O0: # BB#0:
; CHECK_O0-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK_O0-NEXT: # implicit-def: %YMM1
+; CHECK_O0-NEXT: # implicit-def: %ymm1
; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1
; CHECK_O0-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK_O0-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm2[1,2,3,4,5,6,7]
@@ -104,7 +104,7 @@ define <4 x double> @mov01(<4 x double>
; CHECK_O0-LABEL: mov01:
; CHECK_O0: # BB#0:
; CHECK_O0-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK_O0-NEXT: # implicit-def: %YMM1
+; CHECK_O0-NEXT: # implicit-def: %ymm1
; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1
; CHECK_O0-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK_O0-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm2[1,2,3]
@@ -121,7 +121,7 @@ define void @storev16i16(<16 x i16> %a)
;
; CHECK_O0-LABEL: storev16i16:
; CHECK_O0: # BB#0:
-; CHECK_O0-NEXT: # implicit-def: %RAX
+; CHECK_O0-NEXT: # implicit-def: %rax
; CHECK_O0-NEXT: vmovdqa %ymm0, (%rax)
store <16 x i16> %a, <16 x i16>* undef, align 32
unreachable
@@ -135,7 +135,7 @@ define void @storev16i16_01(<16 x i16> %
;
; CHECK_O0-LABEL: storev16i16_01:
; CHECK_O0: # BB#0:
-; CHECK_O0-NEXT: # implicit-def: %RAX
+; CHECK_O0-NEXT: # implicit-def: %rax
; CHECK_O0-NEXT: vmovdqu %ymm0, (%rax)
store <16 x i16> %a, <16 x i16>* undef, align 4
unreachable
@@ -148,7 +148,7 @@ define void @storev32i8(<32 x i8> %a) no
;
; CHECK_O0-LABEL: storev32i8:
; CHECK_O0: # BB#0:
-; CHECK_O0-NEXT: # implicit-def: %RAX
+; CHECK_O0-NEXT: # implicit-def: %rax
; CHECK_O0-NEXT: vmovdqa %ymm0, (%rax)
store <32 x i8> %a, <32 x i8>* undef, align 32
unreachable
@@ -162,13 +162,13 @@ define void @storev32i8_01(<32 x i8> %a)
;
; CHECK_O0-LABEL: storev32i8_01:
; CHECK_O0: # BB#0:
-; CHECK_O0-NEXT: # implicit-def: %RAX
+; CHECK_O0-NEXT: # implicit-def: %rax
; CHECK_O0-NEXT: vmovdqu %ymm0, (%rax)
store <32 x i8> %a, <32 x i8>* undef, align 4
unreachable
}
-; It is faster to make two saves, if the data is already in XMM registers. For
+; It is faster to make two saves, if the data is already in xmm registers. For
; example, after making an integer operation.
define void @double_save(<4 x i32> %A, <4 x i32> %B, <8 x i32>* %P) nounwind ssp {
; CHECK-LABEL: double_save:
@@ -179,7 +179,7 @@ define void @double_save(<4 x i32> %A, <
;
; CHECK_O0-LABEL: double_save:
; CHECK_O0: # BB#0:
-; CHECK_O0-NEXT: # implicit-def: %YMM2
+; CHECK_O0-NEXT: # implicit-def: %ymm2
; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2
; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2
; CHECK_O0-NEXT: vmovdqu %ymm2, (%rdi)
@@ -211,13 +211,13 @@ define void @f_f() nounwind {
;
; CHECK_O0-LABEL: f_f:
; CHECK_O0: # BB#0: # %allocas
-; CHECK_O0-NEXT: # implicit-def: %AL
+; CHECK_O0-NEXT: # implicit-def: %al
; CHECK_O0-NEXT: testb $1, %al
; CHECK_O0-NEXT: jne .LBB8_1
; CHECK_O0-NEXT: jmp .LBB8_2
; CHECK_O0-NEXT: .LBB8_1: # %cif_mask_all
; CHECK_O0-NEXT: .LBB8_2: # %cif_mask_mixed
-; CHECK_O0-NEXT: # implicit-def: %AL
+; CHECK_O0-NEXT: # implicit-def: %al
; CHECK_O0-NEXT: testb $1, %al
; CHECK_O0-NEXT: jne .LBB8_3
; CHECK_O0-NEXT: jmp .LBB8_4
@@ -225,8 +225,8 @@ define void @f_f() nounwind {
; CHECK_O0-NEXT: movl $-1, %eax
; CHECK_O0-NEXT: vmovd %eax, %xmm0
; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1
-; CHECK_O0-NEXT: # implicit-def: %RCX
-; CHECK_O0-NEXT: # implicit-def: %YMM2
+; CHECK_O0-NEXT: # implicit-def: %rcx
+; CHECK_O0-NEXT: # implicit-def: %ymm2
; CHECK_O0-NEXT: vmaskmovps %ymm2, %ymm1, (%rcx)
; CHECK_O0-NEXT: .LBB8_4: # %cif_mixed_test_any_check
allocas:
@@ -259,7 +259,7 @@ define void @add8i32(<8 x i32>* %ret, <8
; CHECK_O0: # BB#0:
; CHECK_O0-NEXT: vmovdqu (%rsi), %xmm0
; CHECK_O0-NEXT: vmovdqu 16(%rsi), %xmm1
-; CHECK_O0-NEXT: # implicit-def: %YMM2
+; CHECK_O0-NEXT: # implicit-def: %ymm2
; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2
; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2
; CHECK_O0-NEXT: vmovdqu %ymm2, (%rdi)
@@ -304,7 +304,7 @@ define void @add4i64a16(<4 x i64>* %ret,
; CHECK_O0: # BB#0:
; CHECK_O0-NEXT: vmovdqa (%rsi), %xmm0
; CHECK_O0-NEXT: vmovdqa 16(%rsi), %xmm1
-; CHECK_O0-NEXT: # implicit-def: %YMM2
+; CHECK_O0-NEXT: # implicit-def: %ymm2
; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2
; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2
; CHECK_O0-NEXT: vmovdqu %ymm2, (%rdi)
Modified: llvm/trunk/test/CodeGen/X86/avx-splat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-splat.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-splat.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-splat.ll Tue Nov 28 09:15:09 2017
@@ -61,7 +61,7 @@ define <8 x float> @funcE() nounwind {
; CHECK: # BB#0: # %for_exit499
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: # implicit-def: %YMM0
+; CHECK-NEXT: # implicit-def: %ymm0
; CHECK-NEXT: jne .LBB4_2
; CHECK-NEXT: # BB#1: # %load.i1247
; CHECK-NEXT: pushq %rbp
Modified: llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll Tue Nov 28 09:15:09 2017
@@ -75,7 +75,7 @@ define <8 x i32> @DAGCombineB(<8 x i32>
define <4 x double> @insert_undef_pd(<4 x double> %a0, <2 x double> %a1) {
; CHECK-LABEL: insert_undef_pd:
; CHECK: # BB#0:
-; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; CHECK-NEXT: vmovaps %ymm1, %ymm0
; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> undef, <2 x double> %a1, i8 0)
@@ -86,7 +86,7 @@ declare <4 x double> @llvm.x86.avx.vinse
define <8 x float> @insert_undef_ps(<8 x float> %a0, <4 x float> %a1) {
; CHECK-LABEL: insert_undef_ps:
; CHECK: # BB#0:
-; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; CHECK-NEXT: vmovaps %ymm1, %ymm0
; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %a1, i8 0)
@@ -97,7 +97,7 @@ declare <8 x float> @llvm.x86.avx.vinser
define <8 x i32> @insert_undef_si(<8 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: insert_undef_si:
; CHECK: # BB#0:
-; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; CHECK-NEXT: vmovaps %ymm1, %ymm0
; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> undef, <4 x i32> %a1, i8 0)
Modified: llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll Tue Nov 28 09:15:09 2017
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=VZ --check-prefix=AVX
; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=VZ --check-prefix=AVX512
-; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx,+fast-partial-ymm-or-zmm-write | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=FAST-YMM-ZMM
+; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx,+fast-partial-ymm-or-zmm-write | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=FAST-ymm-zmm
; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=BTVER2
declare i32 @foo()
@@ -82,14 +82,14 @@ define <4 x float> @test02(<8 x float> %
; VZ-LABEL: test02:
; VZ: # BB#0:
; VZ-NEXT: vaddps %ymm1, %ymm0, %ymm0
-; VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; VZ-NEXT: vzeroupper
; VZ-NEXT: jmp do_sse # TAILCALL
;
; NO-VZ-LABEL: test02:
; NO-VZ: # BB#0:
; NO-VZ-NEXT: vaddps %ymm1, %ymm0, %ymm0
-; NO-VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; NO-VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; NO-VZ-NEXT: jmp do_sse # TAILCALL
%add.i = fadd <8 x float> %a, %b
%add.low = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %add.i, i8 0)
@@ -222,10 +222,10 @@ define <4 x float> @test04(<4 x float> %
; VZ-LABEL: test04:
; VZ: # BB#0:
; VZ-NEXT: pushq %rax
-; VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; VZ-NEXT: callq do_avx
-; VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; VZ-NEXT: popq %rax
; VZ-NEXT: vzeroupper
; VZ-NEXT: retq
@@ -233,10 +233,10 @@ define <4 x float> @test04(<4 x float> %
; NO-VZ-LABEL: test04:
; NO-VZ: # BB#0:
; NO-VZ-NEXT: pushq %rax
-; NO-VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; NO-VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; NO-VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; NO-VZ-NEXT: callq do_avx
-; NO-VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; NO-VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; NO-VZ-NEXT: popq %rax
; NO-VZ-NEXT: retq
%shuf = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
Modified: llvm/trunk/test/CodeGen/X86/avx2-conversions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-conversions.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-conversions.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-conversions.ll Tue Nov 28 09:15:09 2017
@@ -7,7 +7,7 @@ define <4 x i32> @trunc4(<4 x i64> %A) n
; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
; X32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
@@ -15,7 +15,7 @@ define <4 x i32> @trunc4(<4 x i64> %A) n
; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
; X64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%B = trunc <4 x i64> %A to <4 x i32>
@@ -27,7 +27,7 @@ define <8 x i16> @trunc8(<8 x i32> %A) n
; X32: # BB#0:
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
@@ -35,7 +35,7 @@ define <8 x i16> @trunc8(<8 x i32> %A) n
; X64: # BB#0:
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%B = trunc <8 x i32> %A to <8 x i16>
Modified: llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll Tue Nov 28 09:15:09 2017
@@ -355,7 +355,7 @@ define <4 x double> @test_mm256_broadcas
define <4 x i64> @test_mm256_broadcastsi128_si256(<2 x i64> %a0) {
; CHECK-LABEL: test_mm256_broadcastsi128_si256:
; CHECK: # BB#0:
-; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
@@ -1447,7 +1447,7 @@ define <4 x float> @test_mm256_mask_i64g
define <4 x i64> @test0_mm256_inserti128_si256(<4 x i64> %a0, <2 x i64> %a1) nounwind {
; CHECK-LABEL: test0_mm256_inserti128_si256:
; CHECK: # BB#0:
-; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
; CHECK-NEXT: ret{{[l|q]}}
%ext = shufflevector <2 x i64> %a1, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
Modified: llvm/trunk/test/CodeGen/X86/avx2-masked-gather.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-masked-gather.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-masked-gather.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-masked-gather.ll Tue Nov 28 09:15:09 2017
@@ -30,7 +30,7 @@ define <2 x i32> @masked_gather_v2i32(<2
; NOGATHER: # BB#0: # %entry
; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3
; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax
-; NOGATHER-NEXT: # implicit-def: %XMM2
+; NOGATHER-NEXT: # implicit-def: %xmm2
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB0_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -80,7 +80,7 @@ define <4 x i32> @masked_gather_v2i32_co
; NOGATHER: # BB#0: # %entry
; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3
; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax
-; NOGATHER-NEXT: # implicit-def: %XMM2
+; NOGATHER-NEXT: # implicit-def: %xmm2
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB1_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -131,7 +131,7 @@ define <2 x float> @masked_gather_v2floa
; NOGATHER: # BB#0: # %entry
; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3
; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax
-; NOGATHER-NEXT: # implicit-def: %XMM2
+; NOGATHER-NEXT: # implicit-def: %xmm2
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB2_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -178,7 +178,7 @@ define <4 x float> @masked_gather_v2floa
; NOGATHER: # BB#0: # %entry
; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3
; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax
-; NOGATHER-NEXT: # implicit-def: %XMM2
+; NOGATHER-NEXT: # implicit-def: %xmm2
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB3_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -223,7 +223,7 @@ define <4 x i32> @masked_gather_v4i32(<4
; NOGATHER-LABEL: masked_gather_v4i32:
; NOGATHER: # BB#0: # %entry
; NOGATHER-NEXT: vpextrb $0, %xmm1, %eax
-; NOGATHER-NEXT: # implicit-def: %XMM3
+; NOGATHER-NEXT: # implicit-def: %xmm3
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB4_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -281,7 +281,7 @@ define <4 x float> @masked_gather_v4floa
; NOGATHER-LABEL: masked_gather_v4float:
; NOGATHER: # BB#0: # %entry
; NOGATHER-NEXT: vpextrb $0, %xmm1, %eax
-; NOGATHER-NEXT: # implicit-def: %XMM3
+; NOGATHER-NEXT: # implicit-def: %xmm3
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB5_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -351,7 +351,7 @@ define <8 x i32> @masked_gather_v8i32(<8
; NOGATHER-NEXT: vmovdqa (%rdi), %ymm4
; NOGATHER-NEXT: vmovdqa 32(%rdi), %ymm3
; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax
-; NOGATHER-NEXT: # implicit-def: %YMM2
+; NOGATHER-NEXT: # implicit-def: %ymm2
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB6_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -466,7 +466,7 @@ define <8 x float> @masked_gather_v8floa
; NOGATHER-NEXT: vmovdqa (%rdi), %ymm4
; NOGATHER-NEXT: vmovdqa 32(%rdi), %ymm3
; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax
-; NOGATHER-NEXT: # implicit-def: %YMM2
+; NOGATHER-NEXT: # implicit-def: %ymm2
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB7_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -579,7 +579,7 @@ define <4 x i64> @masked_gather_v4i64(<4
; NOGATHER: # BB#0: # %entry
; NOGATHER-NEXT: vmovdqa (%rdi), %ymm3
; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax
-; NOGATHER-NEXT: # implicit-def: %YMM2
+; NOGATHER-NEXT: # implicit-def: %ymm2
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB8_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -656,7 +656,7 @@ define <4 x double> @masked_gather_v4dou
; NOGATHER: # BB#0: # %entry
; NOGATHER-NEXT: vmovdqa (%rdi), %ymm3
; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax
-; NOGATHER-NEXT: # implicit-def: %YMM2
+; NOGATHER-NEXT: # implicit-def: %ymm2
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB9_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -727,7 +727,7 @@ define <2 x i64> @masked_gather_v2i64(<2
; NOGATHER: # BB#0: # %entry
; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3
; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax
-; NOGATHER-NEXT: # implicit-def: %XMM2
+; NOGATHER-NEXT: # implicit-def: %xmm2
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB10_2
; NOGATHER-NEXT: # BB#1: # %cond.load
@@ -772,7 +772,7 @@ define <2 x double> @masked_gather_v2dou
; NOGATHER: # BB#0: # %entry
; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3
; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax
-; NOGATHER-NEXT: # implicit-def: %XMM2
+; NOGATHER-NEXT: # implicit-def: %xmm2
; NOGATHER-NEXT: testb $1, %al
; NOGATHER-NEXT: je .LBB11_2
; NOGATHER-NEXT: # BB#1: # %cond.load
Modified: llvm/trunk/test/CodeGen/X86/avx2-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-shift.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-shift.ll Tue Nov 28 09:15:09 2017
@@ -532,7 +532,7 @@ define <8 x i16> @variable_shl16(<8 x i1
; X32-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
@@ -543,7 +543,7 @@ define <8 x i16> @variable_shl16(<8 x i1
; X64-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%res = shl <8 x i16> %lhs, %rhs
@@ -582,7 +582,7 @@ define <8 x i16> @variable_lshr16(<8 x i
; X32-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
@@ -593,7 +593,7 @@ define <8 x i16> @variable_lshr16(<8 x i
; X64-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%res = lshr <8 x i16> %lhs, %rhs
Modified: llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll Tue Nov 28 09:15:09 2017
@@ -409,7 +409,7 @@ define <8 x i16> @shl_8i16(<8 x i16> %r,
; X32-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
@@ -420,7 +420,7 @@ define <8 x i16> @shl_8i16(<8 x i16> %r,
; X64-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%shl = shl <8 x i16> %r, %a
@@ -617,7 +617,7 @@ define <8 x i16> @lshr_8i16(<8 x i16> %r
; X32-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
@@ -628,7 +628,7 @@ define <8 x i16> @lshr_8i16(<8 x i16> %r
; X64-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%lshr = lshr <8 x i16> %r, %a
Modified: llvm/trunk/test/CodeGen/X86/avx512-arith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-arith.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-arith.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-arith.ll Tue Nov 28 09:15:09 2017
@@ -176,10 +176,10 @@ define <4 x i64> @imulq256(<4 x i64> %y,
;
; AVX512DQ-LABEL: imulq256:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX512DQ-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: vpmullq %zmm0, %zmm1, %zmm0
-; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: retq
;
; SKX-LABEL: imulq256:
@@ -229,10 +229,10 @@ define <2 x i64> @imulq128(<2 x i64> %y,
;
; AVX512DQ-LABEL: imulq128:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def>
-; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; AVX512DQ-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def>
+; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; AVX512DQ-NEXT: vpmullq %zmm0, %zmm1, %zmm0
-; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
;
@@ -717,7 +717,7 @@ define <16 x float> @test_mask_vminps(<1
define <8 x double> @test_mask_vminpd(<8 x double> %dst, <8 x double> %i,
; AVX512F-LABEL: test_mask_vminpd:
; AVX512F: # BB#0:
-; AVX512F-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
+; AVX512F-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512F-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512F-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512F-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}
@@ -732,7 +732,7 @@ define <8 x double> @test_mask_vminpd(<8
;
; AVX512BW-LABEL: test_mask_vminpd:
; AVX512BW: # BB#0:
-; AVX512BW-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
+; AVX512BW-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512BW-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512BW-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512BW-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}
@@ -740,7 +740,7 @@ define <8 x double> @test_mask_vminpd(<8
;
; AVX512DQ-LABEL: test_mask_vminpd:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
+; AVX512DQ-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512DQ-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512DQ-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}
@@ -780,7 +780,7 @@ define <16 x float> @test_mask_vmaxps(<1
define <8 x double> @test_mask_vmaxpd(<8 x double> %dst, <8 x double> %i,
; AVX512F-LABEL: test_mask_vmaxpd:
; AVX512F: # BB#0:
-; AVX512F-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
+; AVX512F-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512F-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512F-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512F-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}
@@ -795,7 +795,7 @@ define <8 x double> @test_mask_vmaxpd(<8
;
; AVX512BW-LABEL: test_mask_vmaxpd:
; AVX512BW: # BB#0:
-; AVX512BW-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
+; AVX512BW-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512BW-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512BW-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512BW-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}
@@ -803,7 +803,7 @@ define <8 x double> @test_mask_vmaxpd(<8
;
; AVX512DQ-LABEL: test_mask_vmaxpd:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
+; AVX512DQ-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512DQ-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512DQ-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}
Modified: llvm/trunk/test/CodeGen/X86/avx512-build-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-build-vector.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-build-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-build-vector.ll Tue Nov 28 09:15:09 2017
@@ -14,7 +14,7 @@ define <16 x i32> @test2(<16 x i32> %x)
define <16 x float> @test3(<4 x float> %a) {
; CHECK-LABEL: test3:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [0,1,2,3,4,18,16,7,8,9,10,11,12,13,14,15]
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1
Modified: llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll Tue Nov 28 09:15:09 2017
@@ -124,7 +124,7 @@ define <8 x i32> @test5(<8 x i32>%a, <8
; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: callq _func8xi1
; KNL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; KNL-NEXT: vpslld $31, %ymm0, %ymm0
@@ -152,7 +152,7 @@ define <8 x i32> @test5(<8 x i32>%a, <8
; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
-; KNL_X32-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL_X32-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL_X32-NEXT: calll _func8xi1
; KNL_X32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; KNL_X32-NEXT: vpslld $31, %ymm0, %ymm0
@@ -264,7 +264,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8
; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: callq _func8xi1
; KNL-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
@@ -299,7 +299,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8
; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
-; KNL_X32-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL_X32-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL_X32-NEXT: calll _func8xi1
; KNL_X32-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL_X32-NEXT: vpsllq $63, %zmm0, %zmm0
Modified: llvm/trunk/test/CodeGen/X86/avx512-cmp-kor-sequence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-cmp-kor-sequence.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-cmp-kor-sequence.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-cmp-kor-sequence.ll Tue Nov 28 09:15:09 2017
@@ -19,7 +19,7 @@ define zeroext i16 @cmp_kor_seq_16(<16 x
; CHECK-NEXT: korw %k2, %k1, %k1
; CHECK-NEXT: korw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
%0 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %x, i32 13, i16 -1, i32 4)
Modified: llvm/trunk/test/CodeGen/X86/avx512-cvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-cvt.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-cvt.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-cvt.ll Tue Nov 28 09:15:09 2017
@@ -80,9 +80,9 @@ define <4 x double> @slto4f64(<4 x i64>
;
; AVX512DQ-LABEL: slto4f64:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0
-; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: retq
%b = sitofp <4 x i64> %a to <4 x double>
ret <4 x double> %b
@@ -105,9 +105,9 @@ define <2 x double> @slto2f64(<2 x i64>
;
; AVX512DQ-LABEL: slto2f64:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0
-; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%b = sitofp <2 x i64> %a to <2 x double>
@@ -133,9 +133,9 @@ define <2 x float> @sltof2f32(<2 x i64>
;
; AVX512DQ-LABEL: sltof2f32:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
-; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%b = sitofp <2 x i64> %a to <2 x float>
@@ -170,7 +170,7 @@ define <4 x float> @slto4f32_mem(<4 x i6
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovups (%rdi), %ymm0
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
-; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%a1 = load <4 x i64>, <4 x i64>* %a, align 8
@@ -204,9 +204,9 @@ define <4 x i64> @f64to4sl(<4 x double>
;
; AVX512DQ-LABEL: f64to4sl:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: vcvttpd2qq %zmm0, %zmm0
-; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: retq
%b = fptosi <4 x double> %a to <4 x i64>
ret <4 x i64> %b
@@ -238,9 +238,9 @@ define <4 x i64> @f32to4sl(<4 x float> %
;
; AVX512DQ-LABEL: f32to4sl:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX512DQ-NEXT: vcvttps2qq %ymm0, %zmm0
-; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: retq
%b = fptosi <4 x float> %a to <4 x i64>
ret <4 x i64> %b
@@ -272,9 +272,9 @@ define <4 x float> @slto4f32(<4 x i64> %
;
; AVX512DQ-LABEL: slto4f32:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
-; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%b = sitofp <4 x i64> %a to <4 x float>
@@ -307,9 +307,9 @@ define <4 x float> @ulto4f32(<4 x i64> %
;
; AVX512DQ-LABEL: ulto4f32:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0
-; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%b = uitofp <4 x i64> %a to <4 x float>
@@ -463,9 +463,9 @@ define <16 x i16> @f32to16us(<16 x float
define <8 x i32> @f32to8ui(<8 x float> %a) nounwind {
; NOVL-LABEL: f32to8ui:
; NOVL: # BB#0:
-; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVL-NEXT: vcvttps2udq %zmm0, %zmm0
-; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NOVL-NEXT: retq
;
; VL-LABEL: f32to8ui:
@@ -479,9 +479,9 @@ define <8 x i32> @f32to8ui(<8 x float> %
define <4 x i32> @f32to4ui(<4 x float> %a) nounwind {
; NOVL-LABEL: f32to4ui:
; NOVL: # BB#0:
-; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; NOVL-NEXT: vcvttps2udq %zmm0, %zmm0
-; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; NOVL-NEXT: vzeroupper
; NOVL-NEXT: retq
;
@@ -507,7 +507,7 @@ define <8 x i16> @f64to8us(<8 x double>
; NOVL: # BB#0:
; NOVL-NEXT: vcvttpd2dq %zmm0, %ymm0
; NOVL-NEXT: vpmovdw %zmm0, %ymm0
-; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; NOVL-NEXT: vzeroupper
; NOVL-NEXT: retq
;
@@ -526,7 +526,7 @@ define <8 x i8> @f64to8uc(<8 x double> %
; NOVL: # BB#0:
; NOVL-NEXT: vcvttpd2dq %zmm0, %ymm0
; NOVL-NEXT: vpmovdw %zmm0, %ymm0
-; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; NOVL-NEXT: vzeroupper
; NOVL-NEXT: retq
;
@@ -543,9 +543,9 @@ define <8 x i8> @f64to8uc(<8 x double> %
define <4 x i32> @f64to4ui(<4 x double> %a) nounwind {
; NOVL-LABEL: f64to4ui:
; NOVL: # BB#0:
-; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVL-NEXT: vcvttpd2udq %zmm0, %ymm0
-; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; NOVL-NEXT: vzeroupper
; NOVL-NEXT: retq
;
@@ -1266,9 +1266,9 @@ define <8 x double> @uito8f64_maskz(<8 x
define <4 x double> @uito4f64(<4 x i32> %a) nounwind {
; NOVL-LABEL: uito4f64:
; NOVL: # BB#0:
-; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; NOVL-NEXT: vcvtudq2pd %ymm0, %zmm0
-; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NOVL-NEXT: retq
;
; VL-LABEL: uito4f64:
@@ -1300,9 +1300,9 @@ define <8 x double> @uito8f64(<8 x i32>
define <8 x float> @uito8f32(<8 x i32> %a) nounwind {
; NOVL-LABEL: uito8f32:
; NOVL: # BB#0:
-; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0
-; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NOVL-NEXT: retq
;
; VL-LABEL: uito8f32:
@@ -1316,9 +1316,9 @@ define <8 x float> @uito8f32(<8 x i32> %
define <4 x float> @uito4f32(<4 x i32> %a) nounwind {
; NOVL-LABEL: uito4f32:
; NOVL: # BB#0:
-; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0
-; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; NOVL-NEXT: vzeroupper
; NOVL-NEXT: retq
;
@@ -1535,7 +1535,7 @@ define <8 x double> @sbto8f64(<8 x doubl
define <8 x float> @sbto8f32(<8 x float> %a) {
; NOVLDQ-LABEL: sbto8f32:
; NOVLDQ: # BB#0:
-; NOVLDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NOVLDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVLDQ-NEXT: vxorps %xmm1, %xmm1, %xmm1
; NOVLDQ-NEXT: vcmpltps %zmm0, %zmm1, %k1
; NOVLDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
@@ -1562,7 +1562,7 @@ define <8 x float> @sbto8f32(<8 x float>
;
; AVX512DQ-LABEL: sbto8f32:
; AVX512DQ: # BB#0:
-; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512DQ-NEXT: vcmpltps %zmm0, %zmm1, %k0
; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0
@@ -1870,13 +1870,13 @@ define <16 x double> @ubto16f64(<16 x i3
define <8 x float> @ubto8f32(<8 x i32> %a) {
; NOVL-LABEL: ubto8f32:
; NOVL: # BB#0:
-; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1
; NOVL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; NOVL-NEXT: vpmovqd %zmm0, %ymm0
; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0
-; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NOVL-NEXT: retq
;
; VL-LABEL: ubto8f32:
@@ -1894,7 +1894,7 @@ define <8 x float> @ubto8f32(<8 x i32> %
define <8 x double> @ubto8f64(<8 x i32> %a) {
; NOVL-LABEL: ubto8f64:
; NOVL: # BB#0:
-; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1
; NOVL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
Modified: llvm/trunk/test/CodeGen/X86/avx512-ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-ext.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-ext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-ext.ll Tue Nov 28 09:15:09 2017
@@ -348,7 +348,7 @@ define <8 x i32> @zext_8x8mem_to_8x32(<8
; KNL-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: zext_8x8mem_to_8x32:
@@ -372,7 +372,7 @@ define <8 x i32> @sext_8x8mem_to_8x32(<8
; KNL-NEXT: vpmovsxbd (%rdi), %ymm1
; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: sext_8x8mem_to_8x32:
@@ -705,7 +705,7 @@ define <8 x i32> @zext_8x16mem_to_8x32(<
; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: zext_8x16mem_to_8x32:
@@ -729,7 +729,7 @@ define <8 x i32> @sext_8x16mem_to_8x32ma
; KNL-NEXT: vpmovsxwd (%rdi), %ymm1
; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: sext_8x16mem_to_8x32mask:
@@ -763,7 +763,7 @@ define <8 x i32> @zext_8x16_to_8x32mask(
; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: zext_8x16_to_8x32mask:
@@ -1328,7 +1328,7 @@ define i16 @trunc_16i8_to_16i1(<16 x i8>
; KNL-NEXT: vpslld $31, %zmm0, %zmm0
; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: trunc_16i8_to_16i1:
@@ -1336,7 +1336,7 @@ define i16 @trunc_16i8_to_16i1(<16 x i8>
; SKX-NEXT: vpsllw $7, %xmm0, %xmm0
; SKX-NEXT: vpmovb2m %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq
%mask_b = trunc <16 x i8>%a to <16 x i1>
%mask = bitcast <16 x i1> %mask_b to i16
@@ -1349,7 +1349,7 @@ define i16 @trunc_16i32_to_16i1(<16 x i3
; KNL-NEXT: vpslld $31, %zmm0, %zmm0
; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: trunc_16i32_to_16i1:
@@ -1357,7 +1357,7 @@ define i16 @trunc_16i32_to_16i1(<16 x i3
; SKX-NEXT: vpslld $31, %zmm0, %zmm0
; SKX-NEXT: vptestmd %zmm0, %zmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%mask_b = trunc <16 x i32>%a to <16 x i1>
@@ -1396,7 +1396,7 @@ define i8 @trunc_8i16_to_8i1(<8 x i16> %
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; KNL-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: trunc_8i16_to_8i1:
@@ -1404,7 +1404,7 @@ define i8 @trunc_8i16_to_8i1(<8 x i16> %
; SKX-NEXT: vpsllw $15, %xmm0, %xmm0
; SKX-NEXT: vpmovw2m %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq
%mask_b = trunc <8 x i16>%a to <8 x i1>
%mask = bitcast <8 x i1> %mask_b to i8
@@ -1442,7 +1442,7 @@ define i16 @trunc_i32_to_i1(i32 %a) {
; KNL-NEXT: kmovw %edi, %k1
; KNL-NEXT: korw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: trunc_i32_to_i1:
@@ -1455,7 +1455,7 @@ define i16 @trunc_i32_to_i1(i32 %a) {
; SKX-NEXT: kmovw %edi, %k1
; SKX-NEXT: korw %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq
%a_i = trunc i32 %a to i1
%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %a_i, i32 0
@@ -1468,7 +1468,7 @@ define <8 x i16> @sext_8i1_8i16(<8 x i32
; KNL: # BB#0:
; KNL-NEXT: vpcmpgtd %ymm0, %ymm1, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: sext_8i1_8i16:
Modified: llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll Tue Nov 28 09:15:09 2017
@@ -15,7 +15,7 @@ define <8 x i16> @extract_subvector128_v
define <8 x i16> @extract_subvector128_v32i16_first_element(<32 x i16> %x) nounwind {
; SKX-LABEL: extract_subvector128_v32i16_first_element:
; SKX: ## BB#0:
-; SKX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; SKX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%r1 = shufflevector <32 x i16> %x, <32 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -35,7 +35,7 @@ define <16 x i8> @extract_subvector128_v
define <16 x i8> @extract_subvector128_v64i8_first_element(<64 x i8> %x) nounwind {
; SKX-LABEL: extract_subvector128_v64i8_first_element:
; SKX: ## BB#0:
-; SKX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; SKX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%r1 = shufflevector <64 x i8> %x, <64 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
Modified: llvm/trunk/test/CodeGen/X86/avx512-hadd-hsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-hadd-hsub.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-hadd-hsub.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-hadd-hsub.ll Tue Nov 28 09:15:09 2017
@@ -63,7 +63,7 @@ define float @fhadd_16(<16 x float> %x22
; KNL-NEXT: vaddps %zmm1, %zmm0, %zmm0
; KNL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; KNL-NEXT: vaddps %zmm1, %zmm0, %zmm0
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: fhadd_16:
@@ -72,7 +72,7 @@ define float @fhadd_16(<16 x float> %x22
; SKX-NEXT: vaddps %zmm1, %zmm0, %zmm0
; SKX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SKX-NEXT: vaddps %zmm1, %zmm0, %zmm0
-; SKX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; SKX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -90,7 +90,7 @@ define float @fhsub_16(<16 x float> %x22
; KNL-NEXT: vaddps %zmm1, %zmm0, %zmm0
; KNL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; KNL-NEXT: vsubps %zmm1, %zmm0, %zmm0
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: fhsub_16:
@@ -99,7 +99,7 @@ define float @fhsub_16(<16 x float> %x22
; SKX-NEXT: vaddps %zmm1, %zmm0, %zmm0
; SKX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SKX-NEXT: vsubps %zmm1, %zmm0, %zmm0
-; SKX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; SKX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -181,7 +181,7 @@ define <4 x double> @fadd_noundef_low(<8
; KNL-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
; KNL-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
; KNL-NEXT: vaddpd %zmm0, %zmm2, %zmm0
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: fadd_noundef_low:
@@ -189,7 +189,7 @@ define <4 x double> @fadd_noundef_low(<8
; SKX-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
; SKX-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
; SKX-NEXT: vaddpd %zmm0, %zmm2, %zmm0
-; SKX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; SKX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; SKX-NEXT: retq
%x226 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
%x228 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5 ,i32 13, i32 7, i32 15>
@@ -228,7 +228,7 @@ define <8 x i32> @hadd_16_3_sv(<16 x i32
; KNL-NEXT: vshufps {{.*#+}} zmm2 = zmm0[0,2],zmm1[0,2],zmm0[4,6],zmm1[4,6],zmm0[8,10],zmm1[8,10],zmm0[12,14],zmm1[12,14]
; KNL-NEXT: vshufps {{.*#+}} zmm0 = zmm0[1,3],zmm1[1,3],zmm0[5,7],zmm1[5,7],zmm0[9,11],zmm1[9,11],zmm0[13,15],zmm1[13,15]
; KNL-NEXT: vpaddd %zmm0, %zmm2, %zmm0
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: hadd_16_3_sv:
@@ -236,7 +236,7 @@ define <8 x i32> @hadd_16_3_sv(<16 x i32
; SKX-NEXT: vshufps {{.*#+}} zmm2 = zmm0[0,2],zmm1[0,2],zmm0[4,6],zmm1[4,6],zmm0[8,10],zmm1[8,10],zmm0[12,14],zmm1[12,14]
; SKX-NEXT: vshufps {{.*#+}} zmm0 = zmm0[1,3],zmm1[1,3],zmm0[5,7],zmm1[5,7],zmm0[9,11],zmm1[9,11],zmm0[13,15],zmm1[13,15]
; SKX-NEXT: vpaddd %zmm0, %zmm2, %zmm0
-; SKX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; SKX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; SKX-NEXT: retq
%x226 = shufflevector <16 x i32> %x225, <16 x i32> %x227, <16 x i32> <i32 0, i32 2, i32 16, i32 18
, i32 4, i32 6, i32 20, i32 22, i32 8, i32 10, i32 24, i32 26, i32 12, i32 14, i32 28, i32 30>
@@ -255,7 +255,7 @@ define double @fadd_noundef_eel(<8 x dou
; KNL-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
; KNL-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
; KNL-NEXT: vaddpd %zmm0, %zmm2, %zmm0
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: fadd_noundef_eel:
@@ -263,7 +263,7 @@ define double @fadd_noundef_eel(<8 x dou
; SKX-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
; SKX-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
; SKX-NEXT: vaddpd %zmm0, %zmm2, %zmm0
-; SKX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; SKX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%x226 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
Modified: llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll Tue Nov 28 09:15:09 2017
@@ -85,7 +85,7 @@ define float @test7(<16 x float> %x, i32
; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: andq $-64, %rsp
; CHECK-NEXT: subq $128, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %zmm0, (%rsp)
; CHECK-NEXT: andl $15, %edi
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -104,7 +104,7 @@ define double @test8(<8 x double> %x, i3
; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: andq $-64, %rsp
; CHECK-NEXT: subq $128, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %zmm0, (%rsp)
; CHECK-NEXT: andl $7, %edi
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
@@ -123,7 +123,7 @@ define float @test9(<8 x float> %x, i32
; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: andq $-32, %rsp
; CHECK-NEXT: subq $64, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %ymm0, (%rsp)
; CHECK-NEXT: andl $7, %edi
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -142,7 +142,7 @@ define i32 @test10(<16 x i32> %x, i32 %i
; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: andq $-64, %rsp
; CHECK-NEXT: subq $128, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %zmm0, (%rsp)
; CHECK-NEXT: andl $15, %edi
; CHECK-NEXT: movl (%rsp,%rdi,4), %eax
@@ -237,7 +237,7 @@ define i16 @test13(i32 %a, i32 %b) {
; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: korw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test13:
@@ -252,7 +252,7 @@ define i16 @test13(i32 %a, i32 %b) {
; SKX-NEXT: kmovw %eax, %k1
; SKX-NEXT: korw %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq
%cmp_res = icmp ult i32 %a, %b
%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %cmp_res, i32 0
@@ -318,7 +318,7 @@ define i16 @test16(i1 *%addr, i16 %a) {
; KNL-NEXT: vpslld $31, %zmm2, %zmm0
; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -332,7 +332,7 @@ define i16 @test16(i1 *%addr, i16 %a) {
; SKX-NEXT: vpermi2d %zmm0, %zmm1, %zmm2
; SKX-NEXT: vpmovd2m %zmm2, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%x = load i1 , i1 * %addr, align 128
@@ -355,7 +355,7 @@ define i8 @test17(i1 *%addr, i8 %a) {
; KNL-NEXT: vpsllq $63, %zmm2, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -369,7 +369,7 @@ define i8 @test17(i1 *%addr, i8 %a) {
; SKX-NEXT: vpermi2q %zmm0, %zmm1, %zmm2
; SKX-NEXT: vpmovq2m %zmm2, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%x = load i1 , i1 * %addr, align 128
@@ -465,7 +465,7 @@ define i16 @extract_v32i16(<32 x i16> %x
; CHECK-NEXT: vpextrw $1, %xmm0, %eax
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
; CHECK-NEXT: vpextrw $1, %xmm0, (%rdi)
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%r1 = extractelement <32 x i16> %x, i32 1
@@ -480,7 +480,7 @@ define i16 @extract_v16i16(<16 x i16> %x
; CHECK-NEXT: vpextrw $1, %xmm0, %eax
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
; CHECK-NEXT: vpextrw $1, %xmm0, (%rdi)
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%r1 = extractelement <16 x i16> %x, i32 1
@@ -494,7 +494,7 @@ define i16 @extract_v8i16(<8 x i16> %x,
; CHECK: ## BB#0:
; CHECK-NEXT: vpextrw $1, %xmm0, %eax
; CHECK-NEXT: vpextrw $3, %xmm0, (%rdi)
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%r1 = extractelement <8 x i16> %x, i32 1
%r2 = extractelement <8 x i16> %x, i32 3
@@ -508,7 +508,7 @@ define i8 @extract_v64i8(<64 x i8> %x, i
; CHECK-NEXT: vpextrb $1, %xmm0, %eax
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
; CHECK-NEXT: vpextrb $1, %xmm0, (%rdi)
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%r1 = extractelement <64 x i8> %x, i32 1
@@ -523,7 +523,7 @@ define i8 @extract_v32i8(<32 x i8> %x, i
; CHECK-NEXT: vpextrb $1, %xmm0, %eax
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
; CHECK-NEXT: vpextrb $1, %xmm0, (%rdi)
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%r1 = extractelement <32 x i8> %x, i32 1
@@ -537,7 +537,7 @@ define i8 @extract_v16i8(<16 x i8> %x, i
; CHECK: ## BB#0:
; CHECK-NEXT: vpextrb $1, %xmm0, %eax
; CHECK-NEXT: vpextrb $3, %xmm0, (%rdi)
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%r1 = extractelement <16 x i8> %x, i32 1
%r2 = extractelement <16 x i8> %x, i32 3
@@ -1013,7 +1013,7 @@ define i8 @test_iinsertelement_v4i1(i32
; KNL-NEXT: vpsllq $63, %zmm2, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -1029,7 +1029,7 @@ define i8 @test_iinsertelement_v4i1(i32
; SKX-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
; SKX-NEXT: vpmovd2m %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq
%cmp_res_i1 = icmp ult i32 %a, %b
%cmp_cmp_vec = icmp ult <4 x i32> %x, %y
@@ -1058,7 +1058,7 @@ define i8 @test_iinsertelement_v2i1(i32
; KNL-NEXT: vpsllq $63, %zmm2, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -1073,7 +1073,7 @@ define i8 @test_iinsertelement_v2i1(i32
; SKX-NEXT: kshiftrw $1, %k0, %k0
; SKX-NEXT: korw %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq
%cmp_res_i1 = icmp ult i32 %a, %b
%cmp_cmp_vec = icmp ult <2 x i64> %x, %y
@@ -1268,7 +1268,7 @@ define zeroext i8 @extractelement_v64i1_
define i64 @test_extractelement_variable_v2i64(<2 x i64> %t1, i32 %index) {
; CHECK-LABEL: test_extractelement_variable_v2i64:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: movq -24(%rsp,%rdi,8), %rax
@@ -1287,7 +1287,7 @@ define i64 @test_extractelement_variable
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-32, %rsp
; CHECK-NEXT: subq $64, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %ymm0, (%rsp)
; CHECK-NEXT: andl $3, %edi
; CHECK-NEXT: movq (%rsp,%rdi,8), %rax
@@ -1309,7 +1309,7 @@ define i64 @test_extractelement_variable
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-64, %rsp
; CHECK-NEXT: subq $128, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %zmm0, (%rsp)
; CHECK-NEXT: andl $7, %edi
; CHECK-NEXT: movq (%rsp,%rdi,8), %rax
@@ -1324,7 +1324,7 @@ define i64 @test_extractelement_variable
define double @test_extractelement_variable_v2f64(<2 x double> %t1, i32 %index) {
; CHECK-LABEL: test_extractelement_variable_v2f64:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
@@ -1343,7 +1343,7 @@ define double @test_extractelement_varia
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-32, %rsp
; CHECK-NEXT: subq $64, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %ymm0, (%rsp)
; CHECK-NEXT: andl $3, %edi
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
@@ -1365,7 +1365,7 @@ define double @test_extractelement_varia
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-64, %rsp
; CHECK-NEXT: subq $128, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %zmm0, (%rsp)
; CHECK-NEXT: andl $7, %edi
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
@@ -1380,7 +1380,7 @@ define double @test_extractelement_varia
define i32 @test_extractelement_variable_v4i32(<4 x i32> %t1, i32 %index) {
; CHECK-LABEL: test_extractelement_variable_v4i32:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: andl $3, %edi
; CHECK-NEXT: movl -24(%rsp,%rdi,4), %eax
@@ -1399,7 +1399,7 @@ define i32 @test_extractelement_variable
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-32, %rsp
; CHECK-NEXT: subq $64, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %ymm0, (%rsp)
; CHECK-NEXT: andl $7, %edi
; CHECK-NEXT: movl (%rsp,%rdi,4), %eax
@@ -1421,7 +1421,7 @@ define i32 @test_extractelement_variable
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-64, %rsp
; CHECK-NEXT: subq $128, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %zmm0, (%rsp)
; CHECK-NEXT: andl $15, %edi
; CHECK-NEXT: movl (%rsp,%rdi,4), %eax
@@ -1436,7 +1436,7 @@ define i32 @test_extractelement_variable
define float @test_extractelement_variable_v4f32(<4 x float> %t1, i32 %index) {
; CHECK-LABEL: test_extractelement_variable_v4f32:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: andl $3, %edi
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -1455,7 +1455,7 @@ define float @test_extractelement_variab
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-32, %rsp
; CHECK-NEXT: subq $64, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %ymm0, (%rsp)
; CHECK-NEXT: andl $7, %edi
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -1477,7 +1477,7 @@ define float @test_extractelement_variab
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-64, %rsp
; CHECK-NEXT: subq $128, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %zmm0, (%rsp)
; CHECK-NEXT: andl $15, %edi
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -1492,7 +1492,7 @@ define float @test_extractelement_variab
define i16 @test_extractelement_variable_v8i16(<8 x i16> %t1, i32 %index) {
; CHECK-LABEL: test_extractelement_variable_v8i16:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: andl $7, %edi
; CHECK-NEXT: movzwl -24(%rsp,%rdi,2), %eax
@@ -1511,7 +1511,7 @@ define i16 @test_extractelement_variable
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-32, %rsp
; CHECK-NEXT: subq $64, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %ymm0, (%rsp)
; CHECK-NEXT: andl $15, %edi
; CHECK-NEXT: movzwl (%rsp,%rdi,2), %eax
@@ -1533,7 +1533,7 @@ define i16 @test_extractelement_variable
; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp
-; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; KNL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp)
; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: andl $31, %edi
@@ -1552,7 +1552,7 @@ define i16 @test_extractelement_variable
; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp
-; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; SKX-NEXT: vmovaps %zmm0, (%rsp)
; SKX-NEXT: andl $31, %edi
; SKX-NEXT: movzwl (%rsp,%rdi,2), %eax
@@ -1567,7 +1567,7 @@ define i16 @test_extractelement_variable
define i8 @test_extractelement_variable_v16i8(<16 x i8> %t1, i32 %index) {
; CHECK-LABEL: test_extractelement_variable_v16i8:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: andl $15, %edi
; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax
@@ -1587,7 +1587,7 @@ define i8 @test_extractelement_variable_
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-32, %rsp
; CHECK-NEXT: subq $64, %rsp
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: vmovaps %ymm0, (%rsp)
; CHECK-NEXT: andl $31, %edi
; CHECK-NEXT: movq %rsp, %rax
@@ -1611,7 +1611,7 @@ define i8 @test_extractelement_variable_
; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp
-; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; KNL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp)
; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: andl $63, %edi
@@ -1631,7 +1631,7 @@ define i8 @test_extractelement_variable_
; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp
-; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; SKX-NEXT: vmovaps %zmm0, (%rsp)
; SKX-NEXT: andl $63, %edi
; SKX-NEXT: movq %rsp, %rax
@@ -1695,7 +1695,7 @@ define i8 @test_extractelement_variable_
define zeroext i8 @test_extractelement_varible_v2i1(<2 x i64> %a, <2 x i64> %b, i32 %index) {
; KNL-LABEL: test_extractelement_varible_v2i1:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; KNL-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1
; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0
@@ -1708,7 +1708,7 @@ define zeroext i8 @test_extractelement_v
;
; SKX-LABEL: test_extractelement_varible_v2i1:
; SKX: ## BB#0:
-; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; SKX-NEXT: vpcmpnleuq %xmm1, %xmm0, %k0
; SKX-NEXT: vpmovm2q %k0, %xmm0
; SKX-NEXT: vmovdqa %xmm0, -{{[0-9]+}}(%rsp)
@@ -1725,7 +1725,7 @@ define zeroext i8 @test_extractelement_v
define zeroext i8 @test_extractelement_varible_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %index) {
; KNL-LABEL: test_extractelement_varible_v4i1:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; KNL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1
; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0
@@ -1738,7 +1738,7 @@ define zeroext i8 @test_extractelement_v
;
; SKX-LABEL: test_extractelement_varible_v4i1:
; SKX: ## BB#0:
-; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; SKX-NEXT: vpcmpnleud %xmm1, %xmm0, %k0
; SKX-NEXT: vpmovm2d %k0, %xmm0
; SKX-NEXT: vmovdqa %xmm0, -{{[0-9]+}}(%rsp)
@@ -1762,9 +1762,9 @@ define zeroext i8 @test_extractelement_v
; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp
-; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
-; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
+; KNL-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vmovdqa64 %zmm0, (%rsp)
@@ -1785,7 +1785,7 @@ define zeroext i8 @test_extractelement_v
; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp
-; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; SKX-NEXT: vpcmpnleud %ymm1, %ymm0, %k0
; SKX-NEXT: vpmovm2q %k0, %zmm0
; SKX-NEXT: vmovdqa64 %zmm0, (%rsp)
@@ -1812,7 +1812,7 @@ define zeroext i8 @test_extractelement_v
; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp
-; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vmovdqa32 %zmm0, (%rsp)
@@ -1833,7 +1833,7 @@ define zeroext i8 @test_extractelement_v
; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp
-; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; SKX-NEXT: vpcmpnleud %zmm1, %zmm0, %k0
; SKX-NEXT: vpmovm2d %k0, %zmm0
; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
@@ -1860,7 +1860,7 @@ define zeroext i8 @test_extractelement_v
; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp
-; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; KNL-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; KNL-NEXT: vpxor %ymm2, %ymm1, %ymm1
; KNL-NEXT: vpxor %ymm2, %ymm0, %ymm0
@@ -1884,7 +1884,7 @@ define zeroext i8 @test_extractelement_v
; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp
-; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; SKX-NEXT: vpcmpnleub %ymm1, %ymm0, %k0
; SKX-NEXT: vpmovm2w %k0, %zmm0
; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
Modified: llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll Tue Nov 28 09:15:09 2017
@@ -13,7 +13,7 @@ define zeroext i8 @test_extractelement_v
; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp
-; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0
; SKX-NEXT: vpmovm2b %k0, %zmm0
; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll Tue Nov 28 09:15:09 2017
@@ -544,7 +544,7 @@ define i16 @test_pcmpeq_d(<16 x i32> %a,
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.mask.pcmpeq.d.512(<16 x i32> %a, <16 x i32> %b, i16 -1)
ret i16 %res
@@ -556,7 +556,7 @@ define i16 @test_mask_pcmpeq_d(<16 x i32
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.mask.pcmpeq.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
ret i16 %res
@@ -569,7 +569,7 @@ define i8 @test_pcmpeq_q(<8 x i64> %a, <
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1)
ret i8 %res
@@ -581,7 +581,7 @@ define i8 @test_mask_pcmpeq_q(<8 x i64>
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
ret i8 %res
@@ -594,7 +594,7 @@ define i16 @test_pcmpgt_d(<16 x i32> %a,
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.mask.pcmpgt.d.512(<16 x i32> %a, <16 x i32> %b, i16 -1)
ret i16 %res
@@ -606,7 +606,7 @@ define i16 @test_mask_pcmpgt_d(<16 x i32
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.mask.pcmpgt.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
ret i16 %res
@@ -619,7 +619,7 @@ define i8 @test_pcmpgt_q(<8 x i64> %a, <
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1)
ret i8 %res
@@ -631,7 +631,7 @@ define i8 @test_mask_pcmpgt_q(<8 x i64>
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
ret i8 %res
@@ -3095,7 +3095,7 @@ declare <16 x float> @llvm.x86.avx512.ma
define <16 x float>@test_int_x86_avx512_mask_insertf32x4_512(<16 x float> %x0, <4 x float> %x1, <16 x float> %x3, i16 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_insertf32x4_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM1<def> %XMM1<kill> %ZMM1<def>
+; CHECK-NEXT: ## kill: %xmm1<def> %xmm1<kill> %zmm1<def>
; CHECK-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm3
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm2 {%k1}
@@ -3116,7 +3116,7 @@ declare <16 x i32> @llvm.x86.avx512.mask
define <16 x i32>@test_int_x86_avx512_mask_inserti32x4_512(<16 x i32> %x0, <4 x i32> %x1, <16 x i32> %x3, i16 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_inserti32x4_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM1<def> %XMM1<kill> %ZMM1<def>
+; CHECK-NEXT: ## kill: %xmm1<def> %xmm1<kill> %zmm1<def>
; CHECK-NEXT: vinserti32x4 $1, %xmm1, %zmm0, %zmm3
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vinserti32x4 $1, %xmm1, %zmm0, %zmm2 {%k1}
@@ -3560,7 +3560,7 @@ declare <16 x float> @llvm.x86.avx512.ma
define <16 x float>@test_int_x86_avx512_mask_broadcastf32x4_512(<4 x float> %x0, <16 x float> %x2, i16 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x4_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
; CHECK-NEXT: kmovw %edi, %k1
@@ -3594,7 +3594,7 @@ declare <8 x double> @llvm.x86.avx512.ma
define <8 x double>@test_int_x86_avx512_mask_broadcastf64x4_512(<4 x double> %x0, <8 x double> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x4_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm2
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm1 {%k1}
@@ -3628,7 +3628,7 @@ declare <16 x i32> @llvm.x86.avx512.mask
define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x4_512(<4 x i32> %x0, <16 x i32> %x2, i16 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x4_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0
; CHECK-NEXT: kmovw %edi, %k1
@@ -3663,7 +3663,7 @@ declare <8 x i64> @llvm.x86.avx512.mask.
define <8 x i64>@test_int_x86_avx512_mask_broadcasti64x4_512(<4 x i64> %x0, <8 x i64> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x4_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm2
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm1 {%k1}
@@ -3733,7 +3733,7 @@ define i8 @test_vptestmq(<8 x i64> %a0,
; CHECK-NEXT: vptestmq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: addb %cl, %al
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %a0, <8 x i64> %a1, i8 -1)
%res1 = call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %a0, <8 x i64> %a1, i8 %m)
@@ -3751,7 +3751,7 @@ define i16 @test_vptestmd(<16 x i32> %a0
; CHECK-NEXT: vptestmd %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: addl %ecx, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.ptestm.d.512(<16 x i32> %a0, <16 x i32> %a1, i16 -1)
%res1 = call i16 @llvm.x86.avx512.ptestm.d.512(<16 x i32> %a0, <16 x i32> %a1, i16 %m)
@@ -3771,7 +3771,7 @@ define i16 at test_int_x86_avx512_ptestnm_d
; CHECK-NEXT: kmovw %k1, %ecx
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: addl %ecx, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.ptestnm.d.512(<16 x i32> %x0, <16 x i32> %x1, i16 %x2)
%res1 = call i16 @llvm.x86.avx512.ptestnm.d.512(<16 x i32> %x0, <16 x i32> %x1, i16-1)
@@ -3790,7 +3790,7 @@ define i8 at test_int_x86_avx512_ptestnm_q_
; CHECK-NEXT: kmovw %k1, %ecx
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: addb %cl, %al
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.ptestnm.q.512(<8 x i64> %x0, <8 x i64> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestnm.q.512(<8 x i64> %x0, <8 x i64> %x1, i8-1)
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll Tue Nov 28 09:15:09 2017
@@ -40,7 +40,7 @@ define i16 @test_kand(i16 %a0, i16 %a1)
; CHECK-NEXT: kandw %k0, %k1, %k0
; CHECK-NEXT: kandw %k0, %k2, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%t1 = call i16 @llvm.x86.avx512.kand.w(i16 %a0, i16 8)
%t2 = call i16 @llvm.x86.avx512.kand.w(i16 %t1, i16 %a1)
@@ -58,7 +58,7 @@ define i16 @test_kandn(i16 %a0, i16 %a1)
; CHECK-NEXT: kandnw %k2, %k1, %k1
; CHECK-NEXT: kandnw %k0, %k1, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%t1 = call i16 @llvm.x86.avx512.kandn.w(i16 %a0, i16 8)
%t2 = call i16 @llvm.x86.avx512.kandn.w(i16 %t1, i16 %a1)
@@ -72,7 +72,7 @@ define i16 @test_knot(i16 %a0) {
; CHECK-NEXT: kmovw %edi, %k0
; CHECK-NEXT: knotw %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.knot.w(i16 %a0)
ret i16 %res
@@ -89,7 +89,7 @@ define i16 @test_kor(i16 %a0, i16 %a1) {
; CHECK-NEXT: korw %k0, %k1, %k0
; CHECK-NEXT: korw %k0, %k2, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%t1 = call i16 @llvm.x86.avx512.kor.w(i16 %a0, i16 8)
%t2 = call i16 @llvm.x86.avx512.kor.w(i16 %t1, i16 %a1)
@@ -105,7 +105,7 @@ define i16 @unpckbw_test(i16 %a0, i16 %a
; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kunpckbw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.kunpck.bw(i16 %a0, i16 %a1)
ret i16 %res
@@ -124,7 +124,7 @@ define i16 @test_kxnor(i16 %a0, i16 %a1)
; CHECK-NEXT: kxorw %k0, %k1, %k0
; CHECK-NEXT: kxorw %k0, %k2, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%t1 = call i16 @llvm.x86.avx512.kxnor.w(i16 %a0, i16 8)
%t2 = call i16 @llvm.x86.avx512.kxnor.w(i16 %t1, i16 %a1)
@@ -142,7 +142,7 @@ define i16 @test_kxor(i16 %a0, i16 %a1)
; CHECK-NEXT: kxorw %k0, %k1, %k0
; CHECK-NEXT: kxorw %k0, %k2, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%t1 = call i16 @llvm.x86.avx512.kxor.w(i16 %a0, i16 8)
%t2 = call i16 @llvm.x86.avx512.kxor.w(i16 %t1, i16 %a1)
@@ -808,7 +808,7 @@ declare <8 x double> @llvm.x86.avx512.vb
; CHECK: ## BB#0:
; CHECK-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, i16 -1, i32 8)
ret i16 %res
@@ -820,7 +820,7 @@ declare <8 x double> @llvm.x86.avx512.vb
; CHECK: ## BB#0:
; CHECK-NEXT: vcmpneqpd %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 4, i8 -1, i32 4)
ret i8 %res
@@ -3309,7 +3309,7 @@ define i8 at test_int_x86_avx512_mask_cmp_s
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vcmpnltsd {sae}, %xmm1, %xmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res4 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 5, i8 %x3, i32 8)
@@ -3331,7 +3331,7 @@ define i8 at test_int_x86_avx512_mask_cmp_s
; CHECK-NEXT: orb %cl, %dl
; CHECK-NEXT: orb %sil, %al
; CHECK-NEXT: orb %dl, %al
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res1 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 2, i8 -1, i32 4)
@@ -3353,7 +3353,7 @@ define i8 at test_int_x86_avx512_mask_cmp_s
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vcmpunordss %xmm1, %xmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 %x3, i32 4)
@@ -3376,7 +3376,7 @@ define i8 at test_int_x86_avx512_mask_cmp_s
; CHECK-NEXT: andb %cl, %dl
; CHECK-NEXT: andb %sil, %al
; CHECK-NEXT: andb %dl, %al
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res1 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 2, i8 -1, i32 4)
%res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 -1, i32 8)
Modified: llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll Tue Nov 28 09:15:09 2017
@@ -11,7 +11,7 @@ define i16 @mask16(i16 %x) {
; KNL-NEXT: kmovw %edi, %k0
; KNL-NEXT: knotw %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: mask16:
@@ -19,7 +19,7 @@ define i16 @mask16(i16 %x) {
; SKX-NEXT: kmovd %edi, %k0
; SKX-NEXT: knotw %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq
;
; AVX512BW-LABEL: mask16:
@@ -27,7 +27,7 @@ define i16 @mask16(i16 %x) {
; AVX512BW-NEXT: kmovd %edi, %k0
; AVX512BW-NEXT: knotw %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: mask16:
@@ -35,7 +35,7 @@ define i16 @mask16(i16 %x) {
; AVX512DQ-NEXT: kmovw %edi, %k0
; AVX512DQ-NEXT: knotw %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
-; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512DQ-NEXT: retq
%m0 = bitcast i16 %x to <16 x i1>
%m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
@@ -84,7 +84,7 @@ define i8 @mask8(i8 %x) {
; KNL-NEXT: kmovw %edi, %k0
; KNL-NEXT: knotw %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: mask8:
@@ -92,7 +92,7 @@ define i8 @mask8(i8 %x) {
; SKX-NEXT: kmovd %edi, %k0
; SKX-NEXT: knotb %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq
;
; AVX512BW-LABEL: mask8:
@@ -100,7 +100,7 @@ define i8 @mask8(i8 %x) {
; AVX512BW-NEXT: kmovd %edi, %k0
; AVX512BW-NEXT: knotw %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: mask8:
@@ -108,7 +108,7 @@ define i8 @mask8(i8 %x) {
; AVX512DQ-NEXT: kmovw %edi, %k0
; AVX512DQ-NEXT: knotb %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
-; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512DQ-NEXT: retq
%m0 = bitcast i8 %x to <8 x i1>
%m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
@@ -235,7 +235,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <1
; KNL-NEXT: kxorw %k1, %k0, %k0
; KNL-NEXT: korw %k0, %k2, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: mand16_mem:
@@ -246,7 +246,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <1
; SKX-NEXT: kxorw %k1, %k0, %k0
; SKX-NEXT: korw %k0, %k2, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq
;
; AVX512BW-LABEL: mand16_mem:
@@ -257,7 +257,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <1
; AVX512BW-NEXT: kxorw %k1, %k0, %k0
; AVX512BW-NEXT: korw %k0, %k2, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: mand16_mem:
@@ -268,7 +268,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <1
; AVX512DQ-NEXT: kxorw %k1, %k0, %k0
; AVX512DQ-NEXT: korw %k0, %k2, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
-; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512DQ-NEXT: retq
%ma = load <16 x i1>, <16 x i1>* %x
%mb = load <16 x i1>, <16 x i1>* %y
@@ -285,7 +285,7 @@ define i8 @shuf_test1(i16 %v) nounwind {
; KNL-NEXT: kmovw %edi, %k0
; KNL-NEXT: kshiftrw $8, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: shuf_test1:
@@ -293,7 +293,7 @@ define i8 @shuf_test1(i16 %v) nounwind {
; SKX-NEXT: kmovd %edi, %k0
; SKX-NEXT: kshiftrw $8, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq
;
; AVX512BW-LABEL: shuf_test1:
@@ -301,7 +301,7 @@ define i8 @shuf_test1(i16 %v) nounwind {
; AVX512BW-NEXT: kmovd %edi, %k0
; AVX512BW-NEXT: kshiftrw $8, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: shuf_test1:
@@ -309,7 +309,7 @@ define i8 @shuf_test1(i16 %v) nounwind {
; AVX512DQ-NEXT: kmovw %edi, %k0
; AVX512DQ-NEXT: kshiftrw $8, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
-; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512DQ-NEXT: retq
%v1 = bitcast i16 %v to <16 x i1>
%mask = shufflevector <16 x i1> %v1, <16 x i1> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -371,7 +371,7 @@ define i16 @zext_test2(<16 x i32> %a, <1
; KNL-NEXT: kshiftrw $15, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: andl $1, %eax
-; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -382,7 +382,7 @@ define i16 @zext_test2(<16 x i32> %a, <1
; SKX-NEXT: kshiftrw $15, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: andl $1, %eax
-; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
;
@@ -393,7 +393,7 @@ define i16 @zext_test2(<16 x i32> %a, <1
; AVX512BW-NEXT: kshiftrw $15, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
; AVX512BW-NEXT: andl $1, %eax
-; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -404,7 +404,7 @@ define i16 @zext_test2(<16 x i32> %a, <1
; AVX512DQ-NEXT: kshiftrw $15, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
; AVX512DQ-NEXT: andl $1, %eax
-; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%cmp_res = icmp ugt <16 x i32> %a, %b
@@ -421,7 +421,7 @@ define i8 @zext_test3(<16 x i32> %a, <16
; KNL-NEXT: kshiftrw $15, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: andb $1, %al
-; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -432,7 +432,7 @@ define i8 @zext_test3(<16 x i32> %a, <16
; SKX-NEXT: kshiftrw $15, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: andb $1, %al
-; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
;
@@ -443,7 +443,7 @@ define i8 @zext_test3(<16 x i32> %a, <16
; AVX512BW-NEXT: kshiftrw $15, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
; AVX512BW-NEXT: andb $1, %al
-; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -454,7 +454,7 @@ define i8 @zext_test3(<16 x i32> %a, <16
; AVX512DQ-NEXT: kshiftrw $15, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
; AVX512DQ-NEXT: andb $1, %al
-; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%cmp_res = icmp ugt <16 x i32> %a, %b
@@ -704,7 +704,7 @@ define <16 x i8> @test8(<16 x i32>%a, <1
; AVX512BW-NEXT: vpcmpgtd %zmm2, %zmm0, %k0
; AVX512BW-NEXT: LBB17_3:
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
-; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -774,7 +774,7 @@ define <16 x i1> @test9(<16 x i1>%a, <16
; AVX512BW-NEXT: LBB18_3:
; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
-; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -907,7 +907,7 @@ define <16 x i1> @test15(i32 %x, i32 %y)
; AVX512BW-NEXT: cmovgw %ax, %cx
; AVX512BW-NEXT: kmovd %ecx, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
-; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -1220,7 +1220,7 @@ define <8 x i1> @test18(i8 %a, i16 %y) {
; AVX512BW-NEXT: kshiftlw $7, %k0, %k0
; AVX512BW-NEXT: korw %k0, %k1, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
-; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -1300,7 +1300,7 @@ define <32 x i16> @test21(<32 x i16> %x
define void @test22(<4 x i1> %a, <4 x i1>* %addr) {
; KNL-LABEL: test22:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; KNL-NEXT: vpslld $31, %ymm0, %ymm0
; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
@@ -1317,7 +1317,7 @@ define void @test22(<4 x i1> %a, <4 x i1
;
; AVX512BW-LABEL: test22:
; AVX512BW: ## BB#0:
-; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX512BW-NEXT: vpslld $31, %ymm0, %ymm0
; AVX512BW-NEXT: vptestmd %zmm0, %zmm0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
@@ -1327,7 +1327,7 @@ define void @test22(<4 x i1> %a, <4 x i1
;
; AVX512DQ-LABEL: test22:
; AVX512DQ: ## BB#0:
-; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; AVX512DQ-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX512DQ-NEXT: vpslld $31, %ymm0, %ymm0
; AVX512DQ-NEXT: vptestmd %zmm0, %zmm0, %k0
; AVX512DQ-NEXT: kmovb %k0, (%rdi)
@@ -1340,7 +1340,7 @@ define void @test22(<4 x i1> %a, <4 x i1
define void @test23(<2 x i1> %a, <2 x i1>* %addr) {
; KNL-LABEL: test23:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
@@ -1357,7 +1357,7 @@ define void @test23(<2 x i1> %a, <2 x i1
;
; AVX512BW-LABEL: test23:
; AVX512BW: ## BB#0:
-; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; AVX512BW-NEXT: vpsllq $63, %zmm0, %zmm0
; AVX512BW-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
@@ -1367,7 +1367,7 @@ define void @test23(<2 x i1> %a, <2 x i1
;
; AVX512DQ-LABEL: test23:
; AVX512DQ: ## BB#0:
-; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; AVX512DQ-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; AVX512DQ-NEXT: vpsllq $63, %zmm0, %zmm0
; AVX512DQ-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512DQ-NEXT: kmovb %k0, (%rdi)
@@ -2536,7 +2536,7 @@ define <2 x i16> @load_2i1(<2 x i1>* %a)
; KNL-NEXT: movzbl (%rdi), %eax
; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -2551,7 +2551,7 @@ define <2 x i16> @load_2i1(<2 x i1>* %a)
; AVX512BW-NEXT: movzbl (%rdi), %eax
; AVX512BW-NEXT: kmovd %eax, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -2559,7 +2559,7 @@ define <2 x i16> @load_2i1(<2 x i1>* %a)
; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: kmovb (%rdi), %k0
; AVX512DQ-NEXT: vpmovm2q %k0, %zmm0
-; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512DQ-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%b = load <2 x i1>, <2 x i1>* %a
@@ -2574,7 +2574,7 @@ define <4 x i16> @load_4i1(<4 x i1>* %a)
; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vpmovqd %zmm0, %ymm0
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -2590,7 +2590,7 @@ define <4 x i16> @load_4i1(<4 x i1>* %a)
; AVX512BW-NEXT: kmovd %eax, %k1
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0
-; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -2598,7 +2598,7 @@ define <4 x i16> @load_4i1(<4 x i1>* %a)
; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: kmovb (%rdi), %k0
; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0
-; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512DQ-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%b = load <4 x i1>, <4 x i1>* %a
@@ -3624,7 +3624,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %
; KNL-NEXT: kmovw %esi, %k1
; KNL-NEXT: kxorw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test_v16i1_add:
@@ -3633,7 +3633,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %
; SKX-NEXT: kmovd %esi, %k1
; SKX-NEXT: kxorw %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq
;
; AVX512BW-LABEL: test_v16i1_add:
@@ -3642,7 +3642,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %
; AVX512BW-NEXT: kmovd %esi, %k1
; AVX512BW-NEXT: kxorw %k1, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_v16i1_add:
@@ -3651,7 +3651,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %
; AVX512DQ-NEXT: kmovw %esi, %k1
; AVX512DQ-NEXT: kxorw %k1, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
-; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512DQ-NEXT: retq
%m0 = bitcast i16 %x to <16 x i1>
%m1 = bitcast i16 %y to <16 x i1>
@@ -3667,7 +3667,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %
; KNL-NEXT: kmovw %esi, %k1
; KNL-NEXT: kxorw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test_v16i1_sub:
@@ -3676,7 +3676,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %
; SKX-NEXT: kmovd %esi, %k1
; SKX-NEXT: kxorw %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq
;
; AVX512BW-LABEL: test_v16i1_sub:
@@ -3685,7 +3685,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %
; AVX512BW-NEXT: kmovd %esi, %k1
; AVX512BW-NEXT: kxorw %k1, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_v16i1_sub:
@@ -3694,7 +3694,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %
; AVX512DQ-NEXT: kmovw %esi, %k1
; AVX512DQ-NEXT: kxorw %k1, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
-; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512DQ-NEXT: retq
%m0 = bitcast i16 %x to <16 x i1>
%m1 = bitcast i16 %y to <16 x i1>
@@ -3710,7 +3710,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %
; KNL-NEXT: kmovw %esi, %k1
; KNL-NEXT: kandw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test_v16i1_mul:
@@ -3719,7 +3719,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %
; SKX-NEXT: kmovd %esi, %k1
; SKX-NEXT: kandw %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq
;
; AVX512BW-LABEL: test_v16i1_mul:
@@ -3728,7 +3728,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %
; AVX512BW-NEXT: kmovd %esi, %k1
; AVX512BW-NEXT: kandw %k1, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_v16i1_mul:
@@ -3737,7 +3737,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %
; AVX512DQ-NEXT: kmovw %esi, %k1
; AVX512DQ-NEXT: kandw %k1, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
-; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; AVX512DQ-NEXT: retq
%m0 = bitcast i16 %x to <16 x i1>
%m1 = bitcast i16 %y to <16 x i1>
@@ -3753,7 +3753,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) {
; KNL-NEXT: kmovw %esi, %k1
; KNL-NEXT: kxorw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test_v8i1_add:
@@ -3762,7 +3762,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) {
; SKX-NEXT: kmovd %esi, %k1
; SKX-NEXT: kxorb %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq
;
; AVX512BW-LABEL: test_v8i1_add:
@@ -3771,7 +3771,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) {
; AVX512BW-NEXT: kmovd %esi, %k1
; AVX512BW-NEXT: kxorw %k1, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_v8i1_add:
@@ -3780,7 +3780,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) {
; AVX512DQ-NEXT: kmovw %esi, %k1
; AVX512DQ-NEXT: kxorb %k1, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
-; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512DQ-NEXT: retq
%m0 = bitcast i8 %x to <8 x i1>
%m1 = bitcast i8 %y to <8 x i1>
@@ -3796,7 +3796,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) {
; KNL-NEXT: kmovw %esi, %k1
; KNL-NEXT: kxorw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test_v8i1_sub:
@@ -3805,7 +3805,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) {
; SKX-NEXT: kmovd %esi, %k1
; SKX-NEXT: kxorb %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq
;
; AVX512BW-LABEL: test_v8i1_sub:
@@ -3814,7 +3814,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) {
; AVX512BW-NEXT: kmovd %esi, %k1
; AVX512BW-NEXT: kxorw %k1, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_v8i1_sub:
@@ -3823,7 +3823,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) {
; AVX512DQ-NEXT: kmovw %esi, %k1
; AVX512DQ-NEXT: kxorb %k1, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
-; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512DQ-NEXT: retq
%m0 = bitcast i8 %x to <8 x i1>
%m1 = bitcast i8 %y to <8 x i1>
@@ -3839,7 +3839,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) {
; KNL-NEXT: kmovw %esi, %k1
; KNL-NEXT: kandw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test_v8i1_mul:
@@ -3848,7 +3848,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) {
; SKX-NEXT: kmovd %esi, %k1
; SKX-NEXT: kandb %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq
;
; AVX512BW-LABEL: test_v8i1_mul:
@@ -3857,7 +3857,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) {
; AVX512BW-NEXT: kmovd %esi, %k1
; AVX512BW-NEXT: kandw %k1, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_v8i1_mul:
@@ -3866,7 +3866,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) {
; AVX512DQ-NEXT: kmovw %esi, %k1
; AVX512DQ-NEXT: kandb %k1, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax
-; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; AVX512DQ-NEXT: retq
%m0 = bitcast i8 %x to <8 x i1>
%m1 = bitcast i8 %y to <8 x i1>
Modified: llvm/trunk/test/CodeGen/X86/avx512-memfold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-memfold.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-memfold.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-memfold.ll Tue Nov 28 09:15:09 2017
@@ -7,7 +7,7 @@ define i8 @test_int_x86_avx512_mask_cmp_
; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vcmpunordss (%rdi), %xmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%b.val = load float, float* %b
%bv0 = insertelement <4 x float> undef, float %b.val, i32 0
Modified: llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll Tue Nov 28 09:15:09 2017
@@ -310,9 +310,9 @@ define x86_regcallcc i32 @test_argv32i1(
; X32-NEXT: vpmovm2b %k2, %zmm0
; X32-NEXT: vpmovm2b %k1, %zmm1
; X32-NEXT: vpmovm2b %k0, %zmm2
-; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
-; X32-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<kill>
-; X32-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<kill>
+; X32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
+; X32-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<kill>
+; X32-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<kill>
; X32-NEXT: calll _test_argv32i1helper
; X32-NEXT: vmovups (%esp), %xmm4 # 16-byte Reload
; X32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm5 # 16-byte Reload
@@ -340,9 +340,9 @@ define x86_regcallcc i32 @test_argv32i1(
; WIN64-NEXT: vpmovm2b %k2, %zmm0
; WIN64-NEXT: vpmovm2b %k1, %zmm1
; WIN64-NEXT: vpmovm2b %k0, %zmm2
-; WIN64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
-; WIN64-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<kill>
-; WIN64-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<kill>
+; WIN64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
+; WIN64-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<kill>
+; WIN64-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<kill>
; WIN64-NEXT: callq test_argv32i1helper
; WIN64-NEXT: nop
; WIN64-NEXT: addq $32, %rsp
@@ -384,9 +384,9 @@ define x86_regcallcc i32 @test_argv32i1(
; LINUXOSX64-NEXT: vpmovm2b %k2, %zmm0
; LINUXOSX64-NEXT: vpmovm2b %k1, %zmm1
; LINUXOSX64-NEXT: vpmovm2b %k0, %zmm2
-; LINUXOSX64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
-; LINUXOSX64-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<kill>
-; LINUXOSX64-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<kill>
+; LINUXOSX64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
+; LINUXOSX64-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<kill>
+; LINUXOSX64-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<kill>
; LINUXOSX64-NEXT: callq test_argv32i1helper
; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload
; LINUXOSX64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm9 # 16-byte Reload
@@ -538,9 +538,9 @@ define x86_regcallcc i16 @test_argv16i1(
; X32-NEXT: vpmovm2b %k2, %zmm0
; X32-NEXT: vpmovm2b %k1, %zmm1
; X32-NEXT: vpmovm2b %k0, %zmm2
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
-; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill>
-; X32-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
+; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill>
+; X32-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: calll _test_argv16i1helper
; X32-NEXT: vmovups (%esp), %xmm4 # 16-byte Reload
@@ -568,9 +568,9 @@ define x86_regcallcc i16 @test_argv16i1(
; WIN64-NEXT: vpmovm2b %k2, %zmm0
; WIN64-NEXT: vpmovm2b %k1, %zmm1
; WIN64-NEXT: vpmovm2b %k0, %zmm2
-; WIN64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
-; WIN64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill>
-; WIN64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill>
+; WIN64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
+; WIN64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill>
+; WIN64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill>
; WIN64-NEXT: vzeroupper
; WIN64-NEXT: callq test_argv16i1helper
; WIN64-NEXT: nop
@@ -612,9 +612,9 @@ define x86_regcallcc i16 @test_argv16i1(
; LINUXOSX64-NEXT: vpmovm2b %k2, %zmm0
; LINUXOSX64-NEXT: vpmovm2b %k1, %zmm1
; LINUXOSX64-NEXT: vpmovm2b %k0, %zmm2
-; LINUXOSX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
-; LINUXOSX64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill>
-; LINUXOSX64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill>
+; LINUXOSX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
+; LINUXOSX64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill>
+; LINUXOSX64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill>
; LINUXOSX64-NEXT: vzeroupper
; LINUXOSX64-NEXT: callq test_argv16i1helper
; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload
@@ -705,9 +705,9 @@ define i16 @caller_retv16i1() #0 {
; X32-LABEL: caller_retv16i1:
; X32: # BB#0: # %entry
; X32-NEXT: calll _test_retv16i1
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<def>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<def>
; X32-NEXT: incl %eax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
;
; WIN64-LABEL: caller_retv16i1:
@@ -724,9 +724,9 @@ define i16 @caller_retv16i1() #0 {
; WIN64-NEXT: .seh_savexmm 6, 0
; WIN64-NEXT: .seh_endprologue
; WIN64-NEXT: callq test_retv16i1
-; WIN64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def>
+; WIN64-NEXT: # kill: %ax<def> %ax<kill> %eax<def>
; WIN64-NEXT: incl %eax
-; WIN64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; WIN64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; WIN64-NEXT: vmovaps (%rsp), %xmm6 # 16-byte Reload
; WIN64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm7 # 16-byte Reload
; WIN64-NEXT: addq $40, %rsp
@@ -742,9 +742,9 @@ define i16 @caller_retv16i1() #0 {
; LINUXOSX64-NEXT: pushq %rax
; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16
; LINUXOSX64-NEXT: callq test_retv16i1
-; LINUXOSX64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def>
+; LINUXOSX64-NEXT: # kill: %ax<def> %ax<kill> %eax<def>
; LINUXOSX64-NEXT: incl %eax
-; LINUXOSX64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; LINUXOSX64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; LINUXOSX64-NEXT: popq %rcx
; LINUXOSX64-NEXT: retq
entry:
@@ -771,9 +771,9 @@ define x86_regcallcc i8 @test_argv8i1(<8
; X32-NEXT: vpmovm2w %k2, %zmm0
; X32-NEXT: vpmovm2w %k1, %zmm1
; X32-NEXT: vpmovm2w %k0, %zmm2
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
-; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill>
-; X32-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
+; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill>
+; X32-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: calll _test_argv8i1helper
; X32-NEXT: vmovups (%esp), %xmm4 # 16-byte Reload
@@ -801,9 +801,9 @@ define x86_regcallcc i8 @test_argv8i1(<8
; WIN64-NEXT: vpmovm2w %k2, %zmm0
; WIN64-NEXT: vpmovm2w %k1, %zmm1
; WIN64-NEXT: vpmovm2w %k0, %zmm2
-; WIN64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
-; WIN64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill>
-; WIN64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill>
+; WIN64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
+; WIN64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill>
+; WIN64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill>
; WIN64-NEXT: vzeroupper
; WIN64-NEXT: callq test_argv8i1helper
; WIN64-NEXT: nop
@@ -845,9 +845,9 @@ define x86_regcallcc i8 @test_argv8i1(<8
; LINUXOSX64-NEXT: vpmovm2w %k2, %zmm0
; LINUXOSX64-NEXT: vpmovm2w %k1, %zmm1
; LINUXOSX64-NEXT: vpmovm2w %k0, %zmm2
-; LINUXOSX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
-; LINUXOSX64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill>
-; LINUXOSX64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill>
+; LINUXOSX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
+; LINUXOSX64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill>
+; LINUXOSX64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill>
; LINUXOSX64-NEXT: vzeroupper
; LINUXOSX64-NEXT: callq test_argv8i1helper
; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload
@@ -938,10 +938,10 @@ define <8 x i1> @caller_retv8i1() #0 {
; X32-LABEL: caller_retv8i1:
; X32: # BB#0: # %entry
; X32-NEXT: calll _test_retv8i1
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<def>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<def>
; X32-NEXT: kmovd %eax, %k0
; X32-NEXT: vpmovm2w %k0, %zmm0
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
@@ -959,10 +959,10 @@ define <8 x i1> @caller_retv8i1() #0 {
; WIN64-NEXT: .seh_savexmm 6, 0
; WIN64-NEXT: .seh_endprologue
; WIN64-NEXT: callq test_retv8i1
-; WIN64-NEXT: # kill: %AL<def> %AL<kill> %EAX<def>
+; WIN64-NEXT: # kill: %al<def> %al<kill> %eax<def>
; WIN64-NEXT: kmovd %eax, %k0
; WIN64-NEXT: vpmovm2w %k0, %zmm0
-; WIN64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; WIN64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; WIN64-NEXT: vmovaps (%rsp), %xmm6 # 16-byte Reload
; WIN64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm7 # 16-byte Reload
; WIN64-NEXT: addq $40, %rsp
@@ -979,10 +979,10 @@ define <8 x i1> @caller_retv8i1() #0 {
; LINUXOSX64-NEXT: pushq %rax
; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16
; LINUXOSX64-NEXT: callq test_retv8i1
-; LINUXOSX64-NEXT: # kill: %AL<def> %AL<kill> %EAX<def>
+; LINUXOSX64-NEXT: # kill: %al<def> %al<kill> %eax<def>
; LINUXOSX64-NEXT: kmovd %eax, %k0
; LINUXOSX64-NEXT: vpmovm2w %k0, %zmm0
-; LINUXOSX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; LINUXOSX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; LINUXOSX64-NEXT: popq %rax
; LINUXOSX64-NEXT: vzeroupper
; LINUXOSX64-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll Tue Nov 28 09:15:09 2017
@@ -8,19 +8,19 @@ define x86_regcallcc i1 @test_argReti1(i
; X32-LABEL: test_argReti1:
; X32: # BB#0:
; X32-NEXT: incb %al
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; WIN64-LABEL: test_argReti1:
; WIN64: # BB#0:
; WIN64-NEXT: incb %al
-; WIN64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; WIN64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; WIN64-NEXT: retq
;
; LINUXOSX64-LABEL: test_argReti1:
; LINUXOSX64: # BB#0:
; LINUXOSX64-NEXT: incb %al
-; LINUXOSX64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; LINUXOSX64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; LINUXOSX64-NEXT: retq
%add = add i1 %a, 1
ret i1 %add
@@ -75,19 +75,19 @@ define x86_regcallcc i8 @test_argReti8(i
; X32-LABEL: test_argReti8:
; X32: # BB#0:
; X32-NEXT: incb %al
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; WIN64-LABEL: test_argReti8:
; WIN64: # BB#0:
; WIN64-NEXT: incb %al
-; WIN64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; WIN64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; WIN64-NEXT: retq
;
; LINUXOSX64-LABEL: test_argReti8:
; LINUXOSX64: # BB#0:
; LINUXOSX64-NEXT: incb %al
-; LINUXOSX64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; LINUXOSX64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; LINUXOSX64-NEXT: retq
%add = add i8 %a, 1
ret i8 %add
@@ -142,19 +142,19 @@ define x86_regcallcc i16 @test_argReti16
; X32-LABEL: test_argReti16:
; X32: # BB#0:
; X32-NEXT: incl %eax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
;
; WIN64-LABEL: test_argReti16:
; WIN64: # BB#0:
; WIN64-NEXT: incl %eax
-; WIN64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; WIN64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; WIN64-NEXT: retq
;
; LINUXOSX64-LABEL: test_argReti16:
; LINUXOSX64: # BB#0:
; LINUXOSX64-NEXT: incl %eax
-; LINUXOSX64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; LINUXOSX64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; LINUXOSX64-NEXT: retq
%add = add i16 %a, 1
ret i16 %add
@@ -167,9 +167,9 @@ define x86_regcallcc i16 @test_CallargRe
; X32-NEXT: pushl %esp
; X32-NEXT: incl %eax
; X32-NEXT: calll _test_argReti16
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<def>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<def>
; X32-NEXT: incl %eax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: popl %esp
; X32-NEXT: retl
;
@@ -180,9 +180,9 @@ define x86_regcallcc i16 @test_CallargRe
; WIN64-NEXT: .seh_endprologue
; WIN64-NEXT: incl %eax
; WIN64-NEXT: callq test_argReti16
-; WIN64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def>
+; WIN64-NEXT: # kill: %ax<def> %ax<kill> %eax<def>
; WIN64-NEXT: incl %eax
-; WIN64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; WIN64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; WIN64-NEXT: popq %rsp
; WIN64-NEXT: retq
; WIN64-NEXT: .seh_handlerdata
@@ -196,9 +196,9 @@ define x86_regcallcc i16 @test_CallargRe
; LINUXOSX64-NEXT: .cfi_offset %rsp, -16
; LINUXOSX64-NEXT: incl %eax
; LINUXOSX64-NEXT: callq test_argReti16
-; LINUXOSX64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def>
+; LINUXOSX64-NEXT: # kill: %ax<def> %ax<kill> %eax<def>
; LINUXOSX64-NEXT: incl %eax
-; LINUXOSX64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; LINUXOSX64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; LINUXOSX64-NEXT: popq %rsp
; LINUXOSX64-NEXT: retq
%b = add i16 %a, 1
@@ -849,7 +849,7 @@ define x86_regcallcc <16 x i32> @test_Ca
ret <16 x i32> %c
}
-; Test regcall when running multiple input parameters - callee saved XMMs
+; Test regcall when running multiple input parameters - callee saved xmms
define x86_regcallcc <32 x float> @testf32_inp(<32 x float> %a, <32 x float> %b, <32 x float> %c) nounwind {
; X32-LABEL: testf32_inp:
; X32: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-schedule.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-schedule.ll Tue Nov 28 09:15:09 2017
@@ -4335,7 +4335,7 @@ define i16 @trunc_16i8_to_16i1(<16 x i8>
; GENERIC-NEXT: vpsllw $7, %xmm0, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: vpmovb2m %xmm0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: trunc_16i8_to_16i1:
@@ -4343,7 +4343,7 @@ define i16 @trunc_16i8_to_16i1(<16 x i8>
; SKX-NEXT: vpsllw $7, %xmm0, %xmm0 # sched: [1:0.50]
; SKX-NEXT: vpmovb2m %xmm0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%mask_b = trunc <16 x i8>%a to <16 x i1>
%mask = bitcast <16 x i1> %mask_b to i16
@@ -4356,7 +4356,7 @@ define i16 @trunc_16i32_to_16i1(<16 x i3
; GENERIC-NEXT: vpslld $31, %zmm0, %zmm0
; GENERIC-NEXT: vptestmd %zmm0, %zmm0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: vzeroupper
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -4365,7 +4365,7 @@ define i16 @trunc_16i32_to_16i1(<16 x i3
; SKX-NEXT: vpslld $31, %zmm0, %zmm0 # sched: [1:0.50]
; SKX-NEXT: vptestmd %zmm0, %zmm0, %k0 # sched: [3:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: vzeroupper # sched: [4:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
%mask_b = trunc <16 x i32>%a to <16 x i1>
@@ -4405,7 +4405,7 @@ define i8 @trunc_8i16_to_8i1(<8 x i16> %
; GENERIC-NEXT: vpsllw $15, %xmm0, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: vpmovw2m %xmm0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: trunc_8i16_to_8i1:
@@ -4413,7 +4413,7 @@ define i8 @trunc_8i16_to_8i1(<8 x i16> %
; SKX-NEXT: vpsllw $15, %xmm0, %xmm0 # sched: [1:0.50]
; SKX-NEXT: vpmovw2m %xmm0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%mask_b = trunc <8 x i16>%a to <8 x i1>
%mask = bitcast <8 x i1> %mask_b to i8
@@ -4450,7 +4450,7 @@ define i16 @trunc_i32_to_i1(i32 %a) {
; GENERIC-NEXT: kmovw %edi, %k1
; GENERIC-NEXT: korw %k1, %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: trunc_i32_to_i1:
@@ -4463,7 +4463,7 @@ define i16 @trunc_i32_to_i1(i32 %a) {
; SKX-NEXT: kmovw %edi, %k1 # sched: [1:1.00]
; SKX-NEXT: korw %k1, %k0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%a_i = trunc i32 %a to i1
%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %a_i, i32 0
@@ -6740,7 +6740,7 @@ define i16 @mask16(i16 %x) {
; GENERIC-NEXT: kmovd %edi, %k0
; GENERIC-NEXT: knotw %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: mask16:
@@ -6748,7 +6748,7 @@ define i16 @mask16(i16 %x) {
; SKX-NEXT: kmovd %edi, %k0 # sched: [1:1.00]
; SKX-NEXT: knotw %k0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%m0 = bitcast i16 %x to <16 x i1>
%m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
@@ -6783,7 +6783,7 @@ define i8 @mask8(i8 %x) {
; GENERIC-NEXT: kmovd %edi, %k0
; GENERIC-NEXT: knotb %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: mask8:
@@ -6791,7 +6791,7 @@ define i8 @mask8(i8 %x) {
; SKX-NEXT: kmovd %edi, %k0 # sched: [1:1.00]
; SKX-NEXT: knotb %k0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%m0 = bitcast i8 %x to <8 x i1>
%m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
@@ -6900,7 +6900,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <1
; GENERIC-NEXT: kxorw %k1, %k0, %k0
; GENERIC-NEXT: korw %k0, %k2, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: mand16_mem:
@@ -6911,7 +6911,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <1
; SKX-NEXT: kxorw %k1, %k0, %k0 # sched: [1:1.00]
; SKX-NEXT: korw %k0, %k2, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%ma = load <16 x i1>, <16 x i1>* %x
%mb = load <16 x i1>, <16 x i1>* %y
@@ -6928,7 +6928,7 @@ define i8 @shuf_test1(i16 %v) nounwind {
; GENERIC-NEXT: kmovd %edi, %k0
; GENERIC-NEXT: kshiftrw $8, %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: shuf_test1:
@@ -6936,7 +6936,7 @@ define i8 @shuf_test1(i16 %v) nounwind {
; SKX-NEXT: kmovd %edi, %k0 # sched: [1:1.00]
; SKX-NEXT: kshiftrw $8, %k0, %k0 # sched: [3:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%v1 = bitcast i16 %v to <16 x i1>
%mask = shufflevector <16 x i1> %v1, <16 x i1> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -6978,7 +6978,7 @@ define i16 @zext_test2(<16 x i32> %a, <1
; GENERIC-NEXT: kshiftrw $15, %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
; GENERIC-NEXT: andl $1, %eax # sched: [1:0.33]
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: vzeroupper
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -6989,7 +6989,7 @@ define i16 @zext_test2(<16 x i32> %a, <1
; SKX-NEXT: kshiftrw $15, %k0, %k0 # sched: [3:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
; SKX-NEXT: andl $1, %eax # sched: [1:0.25]
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: vzeroupper # sched: [4:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
%cmp_res = icmp ugt <16 x i32> %a, %b
@@ -7006,7 +7006,7 @@ define i8 @zext_test3(<16 x i32> %a, <16
; GENERIC-NEXT: kshiftrw $15, %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
; GENERIC-NEXT: andb $1, %al # sched: [1:0.33]
-; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; GENERIC-NEXT: vzeroupper
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -7017,7 +7017,7 @@ define i8 @zext_test3(<16 x i32> %a, <16
; SKX-NEXT: kshiftrw $15, %k0, %k0 # sched: [3:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
; SKX-NEXT: andb $1, %al # sched: [1:0.25]
-; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: vzeroupper # sched: [4:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
%cmp_res = icmp ugt <16 x i32> %a, %b
@@ -8133,7 +8133,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %
; GENERIC-NEXT: kmovd %esi, %k1
; GENERIC-NEXT: kxorw %k1, %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test_v16i1_add:
@@ -8142,7 +8142,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %
; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00]
; SKX-NEXT: kxorw %k1, %k0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%m0 = bitcast i16 %x to <16 x i1>
%m1 = bitcast i16 %y to <16 x i1>
@@ -8158,7 +8158,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %
; GENERIC-NEXT: kmovd %esi, %k1
; GENERIC-NEXT: kxorw %k1, %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test_v16i1_sub:
@@ -8167,7 +8167,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %
; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00]
; SKX-NEXT: kxorw %k1, %k0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%m0 = bitcast i16 %x to <16 x i1>
%m1 = bitcast i16 %y to <16 x i1>
@@ -8183,7 +8183,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %
; GENERIC-NEXT: kmovd %esi, %k1
; GENERIC-NEXT: kandw %k1, %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test_v16i1_mul:
@@ -8192,7 +8192,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %
; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00]
; SKX-NEXT: kandw %k1, %k0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%m0 = bitcast i16 %x to <16 x i1>
%m1 = bitcast i16 %y to <16 x i1>
@@ -8208,7 +8208,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) {
; GENERIC-NEXT: kmovd %esi, %k1
; GENERIC-NEXT: kxorb %k1, %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test_v8i1_add:
@@ -8217,7 +8217,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) {
; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00]
; SKX-NEXT: kxorb %k1, %k0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%m0 = bitcast i8 %x to <8 x i1>
%m1 = bitcast i8 %y to <8 x i1>
@@ -8233,7 +8233,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) {
; GENERIC-NEXT: kmovd %esi, %k1
; GENERIC-NEXT: kxorb %k1, %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test_v8i1_sub:
@@ -8242,7 +8242,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) {
; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00]
; SKX-NEXT: kxorb %k1, %k0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%m0 = bitcast i8 %x to <8 x i1>
%m1 = bitcast i8 %y to <8 x i1>
@@ -8258,7 +8258,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) {
; GENERIC-NEXT: kmovd %esi, %k1
; GENERIC-NEXT: kandb %k1, %k0, %k0
; GENERIC-NEXT: kmovd %k0, %eax
-; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test_v8i1_mul:
@@ -8267,7 +8267,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) {
; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00]
; SKX-NEXT: kandb %k1, %k0, %k0 # sched: [1:1.00]
; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00]
-; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: retq # sched: [7:1.00]
%m0 = bitcast i8 %x to <8 x i1>
%m1 = bitcast i8 %y to <8 x i1>
Modified: llvm/trunk/test/CodeGen/X86/avx512-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-select.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-select.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-select.ll Tue Nov 28 09:15:09 2017
@@ -155,7 +155,7 @@ define i8 @select05_mem(<8 x i1>* %a.0,
; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: korw %k1, %k0, %k0
; X86-NEXT: kmovw %k0, %eax
-; X86-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86-NEXT: retl
;
; X64-LABEL: select05_mem:
@@ -166,7 +166,7 @@ define i8 @select05_mem(<8 x i1>* %a.0,
; X64-NEXT: kmovw %eax, %k1
; X64-NEXT: korw %k1, %k0, %k0
; X64-NEXT: kmovw %k0, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
%mask = load <8 x i1> , <8 x i1>* %m
%a = load <8 x i1> , <8 x i1>* %a.0
@@ -205,7 +205,7 @@ define i8 @select06_mem(<8 x i1>* %a.0,
; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: kandw %k1, %k0, %k0
; X86-NEXT: kmovw %k0, %eax
-; X86-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86-NEXT: retl
;
; X64-LABEL: select06_mem:
@@ -216,7 +216,7 @@ define i8 @select06_mem(<8 x i1>* %a.0,
; X64-NEXT: kmovw %eax, %k1
; X64-NEXT: kandw %k1, %k0, %k0
; X64-NEXT: kmovw %k0, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
%mask = load <8 x i1> , <8 x i1>* %m
%a = load <8 x i1> , <8 x i1>* %a.0
@@ -237,7 +237,7 @@ define i8 @select07(i8 %a.0, i8 %b.0, i8
; X86-NEXT: kandw %k0, %k1, %k0
; X86-NEXT: korw %k2, %k0, %k0
; X86-NEXT: kmovw %k0, %eax
-; X86-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86-NEXT: retl
;
; X64-LABEL: select07:
@@ -249,7 +249,7 @@ define i8 @select07(i8 %a.0, i8 %b.0, i8
; X64-NEXT: kandw %k0, %k1, %k0
; X64-NEXT: korw %k2, %k0, %k0
; X64-NEXT: kmovw %k0, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
%mask = bitcast i8 %m to <8 x i1>
%a = bitcast i8 %a.0 to <8 x i1>
Modified: llvm/trunk/test/CodeGen/X86/avx512-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-shift.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-shift.ll Tue Nov 28 09:15:09 2017
@@ -34,7 +34,7 @@ define <4 x i64> @shift_4_i64(<4 x i64>
; KNL-NEXT: vpsrlq $1, %ymm0, %ymm0
; KNL-NEXT: vpsllq $12, %ymm0, %ymm0
; KNL-NEXT: vpsraq $12, %zmm0, %zmm0
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: shift_4_i64:
@@ -106,10 +106,10 @@ define <8 x i64> @variable_sra2(<8 x i64
define <4 x i64> @variable_sra3(<4 x i64> %x, <4 x i64> %y) {
; KNL-LABEL: variable_sra3:
; KNL: # BB#0:
-; KNL-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpsravq %zmm1, %zmm0, %zmm0
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: variable_sra3:
@@ -127,7 +127,7 @@ define <8 x i16> @variable_sra4(<8 x i16
; KNL-NEXT: vpmovsxwd %xmm0, %ymm0
; KNL-NEXT: vpsravd %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: variable_sra4:
Modified: llvm/trunk/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-shuffles/partial_permute.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-shuffles/partial_permute.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-shuffles/partial_permute.ll Tue Nov 28 09:15:09 2017
@@ -839,7 +839,7 @@ define <8 x i16> @test_32xi16_to_8xi16_p
; CHECK-NEXT: vextracti64x4 $1, %zmm1, %ymm2
; CHECK-NEXT: vmovdqa {{.*#+}} ymm0 = <16,17,5,1,14,14,13,17,u,u,u,u,u,u,u,u>
; CHECK-NEXT: vpermi2w %ymm1, %ymm2, %ymm0
-; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%vec = load <32 x i16>, <32 x i16>* %vp
@@ -967,7 +967,7 @@ define <8 x i16> @test_32xi16_to_8xi16_p
; CHECK-NEXT: vextracti64x4 $1, %zmm1, %ymm2
; CHECK-NEXT: vmovdqa {{.*#+}} ymm0 = <19,1,5,31,9,12,17,9,u,u,u,u,u,u,u,u>
; CHECK-NEXT: vpermi2w %ymm2, %ymm1, %ymm0
-; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%vec = load <32 x i16>, <32 x i16>* %vp
@@ -1493,7 +1493,7 @@ define <4 x i32> @test_16xi32_to_4xi32_p
; CHECK-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,0,3,4,6,4,7]
; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6],ymm1[7]
; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,3,2,3]
-; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%res = shufflevector <16 x i32> %vec, <16 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 12>
@@ -1814,7 +1814,7 @@ define <4 x i32> @test_16xi32_to_4xi32_p
; CHECK-NEXT: vextracti64x4 $1, %zmm1, %ymm2
; CHECK-NEXT: vmovdqa {{.*#+}} ymm0 = <13,0,0,6,u,u,u,u>
; CHECK-NEXT: vpermi2d %ymm2, %ymm1, %ymm0
-; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%vec = load <16 x i32>, <16 x i32>* %vp
@@ -3857,7 +3857,7 @@ define <4 x float> @test_16xfloat_to_4xf
; CHECK-NEXT: vextractf64x4 $1, %zmm1, %ymm2
; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <3,3,15,9,u,u,u,u>
; CHECK-NEXT: vpermi2ps %ymm2, %ymm1, %ymm0
-; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%vec = load <16 x float>, <16 x float>* %vp
@@ -4329,7 +4329,7 @@ define <2 x double> @test_8xdouble_to_2x
; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm1
; CHECK-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,3,2,3]
-; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%res = shufflevector <8 x double> %vec, <8 x double> undef, <2 x i32> <i32 0, i32 6>
@@ -4727,7 +4727,7 @@ define <2 x double> @test_8xdouble_to_2x
; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm1
; CHECK-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[1],ymm1[0],ymm0[3],ymm1[2]
; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,3,2,3]
-; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%vec = load <8 x double>, <8 x double>* %vp
Modified: llvm/trunk/test/CodeGen/X86/avx512-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-trunc.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-trunc.ll Tue Nov 28 09:15:09 2017
@@ -57,9 +57,9 @@ define void @trunc_qb_512_mem(<8 x i64>
define <4 x i8> @trunc_qb_256(<4 x i64> %i) #0 {
; KNL-LABEL: trunc_qb_256:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovqd %zmm0, %ymm0
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -75,7 +75,7 @@ define <4 x i8> @trunc_qb_256(<4 x i64>
define void @trunc_qb_256_mem(<4 x i64> %i, <4 x i8>* %res) #0 {
; KNL-LABEL: trunc_qb_256_mem:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovqd %zmm0, %ymm0
; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; KNL-NEXT: vmovd %xmm0, (%rdi)
@@ -140,9 +140,9 @@ define void @trunc_qw_512_mem(<8 x i64>
define <4 x i16> @trunc_qw_256(<4 x i64> %i) #0 {
; KNL-LABEL: trunc_qw_256:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovqd %zmm0, %ymm0
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -158,7 +158,7 @@ define <4 x i16> @trunc_qw_256(<4 x i64>
define void @trunc_qw_256_mem(<4 x i64> %i, <4 x i16>* %res) #0 {
; KNL-LABEL: trunc_qw_256_mem:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovqd %zmm0, %ymm0
; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; KNL-NEXT: vmovq %xmm0, (%rdi)
@@ -223,9 +223,9 @@ define void @trunc_qd_512_mem(<8 x i64>
define <4 x i32> @trunc_qd_256(<4 x i64> %i) #0 {
; KNL-LABEL: trunc_qd_256:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovqd %zmm0, %ymm0
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -241,7 +241,7 @@ define <4 x i32> @trunc_qd_256(<4 x i64>
define void @trunc_qd_256_mem(<4 x i64> %i, <4 x i32>* %res) #0 {
; KNL-LABEL: trunc_qd_256_mem:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovqd %zmm0, %ymm0
; KNL-NEXT: vmovdqa %xmm0, (%rdi)
; KNL-NEXT: vzeroupper
@@ -305,9 +305,9 @@ define void @trunc_db_512_mem(<16 x i32>
define <8 x i8> @trunc_db_256(<8 x i32> %i) #0 {
; KNL-LABEL: trunc_db_256:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovdw %zmm0, %ymm0
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -323,7 +323,7 @@ define <8 x i8> @trunc_db_256(<8 x i32>
define void @trunc_db_256_mem(<8 x i32> %i, <8 x i8>* %res) #0 {
; KNL-LABEL: trunc_db_256_mem:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
; KNL-NEXT: vmovq %xmm0, (%rdi)
@@ -387,9 +387,9 @@ define void @trunc_dw_512_mem(<16 x i32>
define <8 x i16> @trunc_dw_256(<8 x i32> %i) #0 {
; KNL-LABEL: trunc_dw_256:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovdw %zmm0, %ymm0
-; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -405,7 +405,7 @@ define <8 x i16> @trunc_dw_256(<8 x i32>
define void @trunc_dw_256_mem(<8 x i32> %i, <8 x i16>* %res) #0 {
; KNL-LABEL: trunc_dw_256_mem:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: vmovdqa %xmm0, (%rdi)
; KNL-NEXT: vzeroupper
Modified: llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll Tue Nov 28 09:15:09 2017
@@ -124,7 +124,7 @@ define <8 x double> @_inreg8xdouble(do
define <8 x double> @_sd8xdouble_mask(double %a, <8 x double> %i, <8 x i32> %mask1) {
; ALL-LABEL: _sd8xdouble_mask:
; ALL: # BB#0:
-; ALL-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def>
+; ALL-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def>
; ALL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; ALL-NEXT: vpcmpneqd %zmm3, %zmm2, %k1
; ALL-NEXT: vbroadcastsd %xmm0, %zmm1 {%k1}
@@ -140,7 +140,7 @@ define <8 x double> @_sd8xdouble_mask(
define <8 x double> @_sd8xdouble_maskz(double %a, <8 x i32> %mask1) {
; ALL-LABEL: _sd8xdouble_maskz:
; ALL: # BB#0:
-; ALL-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
+; ALL-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; ALL-NEXT: vpcmpneqd %zmm2, %zmm1, %k1
; ALL-NEXT: vbroadcastsd %xmm0, %zmm0 {%k1} {z}
@@ -166,7 +166,7 @@ define <8 x double> @_sd8xdouble_load(
define <8 x double> @_sd8xdouble_mask_load(double* %a.ptr, <8 x double> %i, <8 x i32> %mask1) {
; ALL-LABEL: _sd8xdouble_mask_load:
; ALL: # BB#0:
-; ALL-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
+; ALL-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; ALL-NEXT: vpcmpneqd %zmm2, %zmm1, %k1
; ALL-NEXT: vbroadcastsd (%rdi), %zmm0 {%k1}
@@ -182,7 +182,7 @@ define <8 x double> @_sd8xdouble_mask_
define <8 x double> @_sd8xdouble_maskz_load(double* %a.ptr, <8 x i32> %mask1) {
; ALL-LABEL: _sd8xdouble_maskz_load:
; ALL: # BB#0:
-; ALL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; ALL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; ALL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; ALL-NEXT: vpcmpneqd %zmm1, %zmm0, %k1
; ALL-NEXT: vbroadcastsd (%rdi), %zmm0 {%k1} {z}
Modified: llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll Tue Nov 28 09:15:09 2017
@@ -111,11 +111,11 @@ define <2 x double> @test8(<2 x double>
define <8 x i32> @test9(<8 x i32> %x, <8 x i32> %y) nounwind {
; KNL-LABEL: test9:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpcmpeqd %zmm1, %zmm0, %k1
; KNL-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test9:
@@ -131,11 +131,11 @@ define <8 x i32> @test9(<8 x i32> %x, <8
define <8 x float> @test10(<8 x float> %x, <8 x float> %y) nounwind {
; KNL-LABEL: test10:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vcmpeqps %zmm1, %zmm0, %k1
; KNL-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1}
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test10:
@@ -166,7 +166,7 @@ define i16 @test12(<16 x i64> %a, <16 x
; KNL-NEXT: vpcmpeqq %zmm3, %zmm1, %k1
; KNL-NEXT: kunpckbw %k0, %k1, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@@ -176,7 +176,7 @@ define i16 @test12(<16 x i64> %a, <16 x
; SKX-NEXT: vpcmpeqq %zmm3, %zmm1, %k1
; SKX-NEXT: kunpckbw %k0, %k1, %k0
; SKX-NEXT: kmovd %k0, %eax
-; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%res = icmp eq <16 x i64> %a, %b
@@ -1007,12 +1007,12 @@ define <4 x float> @test34(<4 x float> %
define <8 x float> @test35(<8 x float> %x, <8 x float> %x1, <8 x float>* %yp) nounwind {
; KNL-LABEL: test35:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vmovups (%rdi), %ymm2
; KNL-NEXT: vcmpltps %zmm2, %zmm0, %k1
; KNL-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1}
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test35:
@@ -1121,12 +1121,12 @@ define <16 x float> @test40(<16 x floa
define <8 x float> @test41(<8 x float> %x, <8 x float> %x1, float* %ptr) nounwind {
; KNL-LABEL: test41:
; KNL: ## BB#0:
-; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vbroadcastss (%rdi), %ymm2
; KNL-NEXT: vcmpltps %zmm2, %zmm0, %k1
; KNL-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1}
-; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: retq
;
; SKX-LABEL: test41:
Modified: llvm/trunk/test/CodeGen/X86/avx512-vec3-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-vec3-crash.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-vec3-crash.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-vec3-crash.ll Tue Nov 28 09:15:09 2017
@@ -20,9 +20,9 @@ define <3 x i8 > @foo(<3 x i8>%x, <3 x i
; CHECK-NEXT: vpextrb $0, %xmm0, %eax
; CHECK-NEXT: vpextrb $4, %xmm0, %edx
; CHECK-NEXT: vpextrb $8, %xmm0, %ecx
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
-; CHECK-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill>
-; CHECK-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
+; CHECK-NEXT: # kill: %dl<def> %dl<kill> %edx<kill>
+; CHECK-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill>
; CHECK-NEXT: retq
%cmp.i = icmp slt <3 x i8> %x, %a
%res = sext <3 x i1> %cmp.i to <3 x i8>
Modified: llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll Tue Nov 28 09:15:09 2017
@@ -1999,7 +1999,7 @@ define i64 @test_mask_cmp_b_512(<64 x i8
; AVX512F-32-NEXT: vpblendvb %ymm0, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
-; AVX512F-32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> %EAX<def>
+; AVX512F-32-NEXT: # kill: %al<def> %al<kill> %eax<kill> %eax<def>
; AVX512F-32-NEXT: shrb $7, %al
; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
@@ -2368,7 +2368,7 @@ define i64 @test_mask_cmp_b_512(<64 x i8
; AVX512F-32-NEXT: vpblendvb %ymm7, %ymm4, %ymm0, %ymm0
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512F-32-NEXT: vpmovb2m %zmm0, %k0
-; AVX512F-32-NEXT: # kill: %BL<def> %BL<kill> %EBX<kill> %EBX<def>
+; AVX512F-32-NEXT: # kill: %bl<def> %bl<kill> %ebx<kill> %ebx<def>
; AVX512F-32-NEXT: shrb $7, %bl
; AVX512F-32-NEXT: kmovd %ebx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm0
@@ -2883,7 +2883,7 @@ define i64 @test_mask_x86_avx512_ucmp_b_
; AVX512F-32-NEXT: vpblendvb %ymm0, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
-; AVX512F-32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> %EAX<def>
+; AVX512F-32-NEXT: # kill: %al<def> %al<kill> %eax<kill> %eax<def>
; AVX512F-32-NEXT: shrb $7, %al
; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
@@ -3252,7 +3252,7 @@ define i64 @test_mask_x86_avx512_ucmp_b_
; AVX512F-32-NEXT: vpblendvb %ymm7, %ymm4, %ymm0, %ymm0
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512F-32-NEXT: vpmovb2m %zmm0, %k0
-; AVX512F-32-NEXT: # kill: %BL<def> %BL<kill> %EBX<kill> %EBX<def>
+; AVX512F-32-NEXT: # kill: %bl<def> %bl<kill> %ebx<kill> %ebx<def>
; AVX512F-32-NEXT: shrb $7, %bl
; AVX512F-32-NEXT: kmovd %ebx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm0
Modified: llvm/trunk/test/CodeGen/X86/avx512bw-mov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-mov.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bw-mov.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bw-mov.ll Tue Nov 28 09:15:09 2017
@@ -105,7 +105,7 @@ define <16 x i8> @test_mask_load_16xi8(<
; CHECK-NEXT: kshiftlq $48, %k0, %k0
; CHECK-NEXT: kshiftrq $48, %k0, %k1
; CHECK-NEXT: vmovdqu8 (%rdi), %zmm0 {%k1} {z}
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; CHECK-NEXT: retq
%res = call <16 x i8> @llvm.masked.load.v16i8(<16 x i8>* %addr, i32 4, <16 x i1>%mask, <16 x i8> undef)
ret <16 x i8> %res
@@ -120,7 +120,7 @@ define <32 x i8> @test_mask_load_32xi8(<
; CHECK-NEXT: kshiftlq $32, %k0, %k0
; CHECK-NEXT: kshiftrq $32, %k0, %k1
; CHECK-NEXT: vmovdqu8 (%rdi), %zmm0 {%k1} {z}
-; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; CHECK-NEXT: retq
%res = call <32 x i8> @llvm.masked.load.v32i8(<32 x i8>* %addr, i32 4, <32 x i1>%mask, <32 x i8> zeroinitializer)
ret <32 x i8> %res
@@ -135,7 +135,7 @@ define <8 x i16> @test_mask_load_8xi16(<
; CHECK-NEXT: kshiftld $24, %k0, %k0
; CHECK-NEXT: kshiftrd $24, %k0, %k1
; CHECK-NEXT: vmovdqu16 (%rdi), %zmm0 {%k1} {z}
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.masked.load.v8i16(<8 x i16>* %addr, i32 4, <8 x i1>%mask, <8 x i16> undef)
ret <8 x i16> %res
@@ -150,7 +150,7 @@ define <16 x i16> @test_mask_load_16xi16
; CHECK-NEXT: kshiftld $16, %k0, %k0
; CHECK-NEXT: kshiftrd $16, %k0, %k1
; CHECK-NEXT: vmovdqu16 (%rdi), %zmm0 {%k1} {z}
-; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; CHECK-NEXT: retq
%res = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %addr, i32 4, <16 x i1>%mask, <16 x i16> zeroinitializer)
ret <16 x i16> %res
@@ -160,7 +160,7 @@ declare <16 x i16> @llvm.masked.load.v16
define void @test_mask_store_16xi8(<16 x i1> %mask, <16 x i8>* %addr, <16 x i8> %val) {
; CHECK-LABEL: test_mask_store_16xi8:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM1<def> %XMM1<kill> %ZMM1<def>
+; CHECK-NEXT: ## kill: %xmm1<def> %xmm1<kill> %zmm1<def>
; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0
; CHECK-NEXT: vpmovb2m %zmm0, %k0
; CHECK-NEXT: kshiftlq $48, %k0, %k0
@@ -175,7 +175,7 @@ declare void @llvm.masked.store.v16i8(<1
define void @test_mask_store_32xi8(<32 x i1> %mask, <32 x i8>* %addr, <32 x i8> %val) {
; CHECK-LABEL: test_mask_store_32xi8:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
+; CHECK-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def>
; CHECK-NEXT: vpsllw $7, %ymm0, %ymm0
; CHECK-NEXT: vpmovb2m %zmm0, %k0
; CHECK-NEXT: kshiftlq $32, %k0, %k0
@@ -190,7 +190,7 @@ declare void @llvm.masked.store.v32i8(<3
define void @test_mask_store_8xi16(<8 x i1> %mask, <8 x i16>* %addr, <8 x i16> %val) {
; CHECK-LABEL: test_mask_store_8xi16:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM1<def> %XMM1<kill> %ZMM1<def>
+; CHECK-NEXT: ## kill: %xmm1<def> %xmm1<kill> %zmm1<def>
; CHECK-NEXT: vpsllw $15, %xmm0, %xmm0
; CHECK-NEXT: vpmovw2m %zmm0, %k0
; CHECK-NEXT: kshiftld $24, %k0, %k0
@@ -205,7 +205,7 @@ declare void @llvm.masked.store.v8i16(<8
define void @test_mask_store_16xi16(<16 x i1> %mask, <16 x i16>* %addr, <16 x i16> %val) {
; CHECK-LABEL: test_mask_store_16xi16:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
+; CHECK-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def>
; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0
; CHECK-NEXT: vpmovb2m %zmm0, %k0
; CHECK-NEXT: kshiftld $16, %k0, %k0
Modified: llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll Tue Nov 28 09:15:09 2017
@@ -503,7 +503,7 @@ define i16 @test_pcmpeq_w_256(<16 x i16>
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpeqw %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x28,0x75,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.mask.pcmpeq.w.256(<16 x i16> %a, <16 x i16> %b, i16 -1)
@@ -516,7 +516,7 @@ define i16 @test_mask_pcmpeq_w_256(<16 x
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
; CHECK-NEXT: vpcmpeqw %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x75,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.mask.pcmpeq.w.256(<16 x i16> %a, <16 x i16> %b, i16 %mask)
@@ -555,7 +555,7 @@ define i16 @test_pcmpgt_w_256(<16 x i16>
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x28,0x65,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.mask.pcmpgt.w.256(<16 x i16> %a, <16 x i16> %b, i16 -1)
@@ -568,7 +568,7 @@ define i16 @test_mask_pcmpgt_w_256(<16 x
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
; CHECK-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x65,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.mask.pcmpgt.w.256(<16 x i16> %a, <16 x i16> %b, i16 %mask)
@@ -582,7 +582,7 @@ define i16 @test_pcmpeq_b_128(<16 x i8>
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x74,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.mask.pcmpeq.b.128(<16 x i8> %a, <16 x i8> %b, i16 -1)
ret i16 %res
@@ -594,7 +594,7 @@ define i16 @test_mask_pcmpeq_b_128(<16 x
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
; CHECK-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x74,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.mask.pcmpeq.b.128(<16 x i8> %a, <16 x i8> %b, i16 %mask)
ret i16 %res
@@ -607,7 +607,7 @@ define i8 @test_pcmpeq_w_128(<8 x i16> %
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x75,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.w.128(<8 x i16> %a, <8 x i16> %b, i8 -1)
ret i8 %res
@@ -619,7 +619,7 @@ define i8 @test_mask_pcmpeq_w_128(<8 x i
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
; CHECK-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x75,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.w.128(<8 x i16> %a, <8 x i16> %b, i8 %mask)
ret i8 %res
@@ -632,7 +632,7 @@ define i16 @test_pcmpgt_b_128(<16 x i8>
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x64,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.mask.pcmpgt.b.128(<16 x i8> %a, <16 x i8> %b, i16 -1)
ret i16 %res
@@ -644,7 +644,7 @@ define i16 @test_mask_pcmpgt_b_128(<16 x
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
; CHECK-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x64,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.mask.pcmpgt.b.128(<16 x i8> %a, <16 x i8> %b, i16 %mask)
ret i16 %res
@@ -657,7 +657,7 @@ define i8 @test_pcmpgt_w_128(<8 x i16> %
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x65,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.w.128(<8 x i16> %a, <8 x i16> %b, i8 -1)
ret i8 %res
@@ -669,7 +669,7 @@ define i8 @test_mask_pcmpgt_w_128(<8 x i
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
; CHECK-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x65,0xc1]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.w.128(<8 x i16> %a, <8 x i16> %b, i8 %mask)
ret i8 %res
@@ -3683,7 +3683,7 @@ define i16 at test_int_x86_avx512_ptestm_b_
; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
; CHECK-NEXT: addl %ecx, %eax ## encoding: [0x01,0xc8]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.ptestm.b.128(<16 x i8> %x0, <16 x i8> %x1, i16 %x2)
%res1 = call i16 @llvm.x86.avx512.ptestm.b.128(<16 x i8> %x0, <16 x i8> %x1, i16-1)
@@ -3721,7 +3721,7 @@ define i8 at test_int_x86_avx512_ptestm_w_1
; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.ptestm.w.128(<8 x i16> %x0, <8 x i16> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestm.w.128(<8 x i16> %x0, <8 x i16> %x1, i8-1)
@@ -3740,7 +3740,7 @@ define i16 at test_int_x86_avx512_ptestm_w_
; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
; CHECK-NEXT: addl %ecx, %eax ## encoding: [0x01,0xc8]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.ptestm.w.256(<16 x i16> %x0, <16 x i16> %x1, i16 %x2)
@@ -3760,7 +3760,7 @@ define i16 at test_int_x86_avx512_ptestnm_b
; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
; CHECK-NEXT: addl %ecx, %eax ## encoding: [0x01,0xc8]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.ptestnm.b.128(<16 x i8> %x0, <16 x i8> %x1, i16 %x2)
%res1 = call i16 @llvm.x86.avx512.ptestnm.b.128(<16 x i8> %x0, <16 x i8> %x1, i16-1)
@@ -3798,7 +3798,7 @@ define i8 at test_int_x86_avx512_ptestnm_w_
; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.ptestnm.w.128(<8 x i16> %x0, <8 x i16> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestnm.w.128(<8 x i16> %x0, <8 x i16> %x1, i8-1)
@@ -3817,7 +3817,7 @@ define i16 at test_int_x86_avx512_ptestnm_w
; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
; CHECK-NEXT: addl %ecx, %eax ## encoding: [0x01,0xc8]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.ptestnm.w.256(<16 x i16> %x0, <16 x i16> %x1, i16 %x2)
Modified: llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll Tue Nov 28 09:15:09 2017
@@ -2311,7 +2311,7 @@ define i16 at test_int_x86_avx512_cvtb2mask
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovb2m %xmm0, %k0 ## encoding: [0x62,0xf2,0x7e,0x08,0x29,0xc0]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.cvtb2mask.128(<16 x i8> %x0)
ret i16 %res
@@ -2336,7 +2336,7 @@ define i8 at test_int_x86_avx512_cvtw2mask_
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovw2m %xmm0, %k0 ## encoding: [0x62,0xf2,0xfe,0x08,0x29,0xc0]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.cvtw2mask.128(<8 x i16> %x0)
ret i8 %res
@@ -2349,7 +2349,7 @@ define i16 at test_int_x86_avx512_cvtw2mask
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0 ## encoding: [0x62,0xf2,0xfe,0x28,0x29,0xc0]
; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i16 @llvm.x86.avx512.cvtw2mask.256(<16 x i16> %x0)
ret i16 %res
Modified: llvm/trunk/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll Tue Nov 28 09:15:09 2017
@@ -7,7 +7,7 @@ define zeroext i16 @TEST_mm_test_epi8_ma
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vptestmb %xmm0, %xmm1, %k0
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -24,7 +24,7 @@ define zeroext i16 @TEST_mm_mask_test_ep
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: vptestmb %xmm0, %xmm1, %k0 {%k1}
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -42,7 +42,7 @@ define zeroext i8 @TEST_mm_test_epi16_ma
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vptestmw %xmm0, %xmm1, %k0
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -59,7 +59,7 @@ define zeroext i8 @TEST_mm_mask_test_epi
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: vptestmw %xmm0, %xmm1, %k0 {%k1}
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -77,7 +77,7 @@ define zeroext i16 @TEST_mm_testn_epi8_m
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vptestnmb %xmm0, %xmm1, %k0
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -94,7 +94,7 @@ define zeroext i16 @TEST_mm_mask_testn_e
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: vptestnmb %xmm0, %xmm1, %k0 {%k1}
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -112,7 +112,7 @@ define zeroext i8 @TEST_mm_testn_epi16_m
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vptestnmw %xmm0, %xmm1, %k0
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -129,7 +129,7 @@ define zeroext i8 @TEST_mm_mask_testn_ep
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: vptestnmw %xmm0, %xmm1, %k0 {%k1}
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -182,7 +182,7 @@ define zeroext i16 @TEST_mm256_test_epi1
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vptestmw %ymm0, %ymm1, %k0
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
@@ -200,7 +200,7 @@ define zeroext i16 @TEST_mm256_mask_test
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: vptestmw %ymm0, %ymm1, %k0 {%k1}
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
@@ -254,7 +254,7 @@ define zeroext i16 @TEST_mm256_testn_epi
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vptestnmw %ymm0, %ymm1, %k0
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
@@ -272,7 +272,7 @@ define zeroext i16 @TEST_mm256_mask_test
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: vptestnmw %ymm0, %ymm1, %k0 {%k1}
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
Modified: llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll Tue Nov 28 09:15:09 2017
@@ -161,7 +161,7 @@ declare <16 x float> @llvm.x86.avx512.ma
define <16 x float>@test_int_x86_avx512_mask_broadcastf32x8_512(<8 x float> %x0, <16 x float> %x2, i16 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x8_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm2
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vinsertf32x8 $1, %ymm0, %zmm0, %zmm1 {%k1}
@@ -195,7 +195,7 @@ declare <8 x double> @llvm.x86.avx512.ma
define <8 x double>@test_int_x86_avx512_mask_broadcastf64x2_512(<2 x double> %x0, <8 x double> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x2_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm2
; CHECK-NEXT: kmovw %edi, %k1
@@ -230,7 +230,7 @@ declare <16 x i32> @llvm.x86.avx512.mask
define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x8_512(<8 x i32> %x0, <16 x i32> %x2, i16 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x8_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm2
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vinserti32x8 $1, %ymm0, %zmm0, %zmm1 {%k1}
@@ -264,7 +264,7 @@ declare <8 x i64> @llvm.x86.avx512.mask.
define <8 x i64>@test_int_x86_avx512_mask_broadcasti64x2_512(<2 x i64> %x0, <8 x i64> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x2_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm2
; CHECK-NEXT: kmovw %edi, %k1
@@ -299,7 +299,7 @@ declare <16 x float> @llvm.x86.avx512.ma
define <16 x float>@test_int_x86_avx512_mask_broadcastf32x2_512(<4 x float> %x0, <16 x float> %x2, i16 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x2_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm2
; CHECK-NEXT: kmovw %edi, %k1
@@ -321,7 +321,7 @@ declare <16 x i32> @llvm.x86.avx512.mask
define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x2_512(<4 x i32> %x0, <16 x i32> %x2, i16 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x2_512:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm2
; CHECK-NEXT: kmovw %edi, %k1
Modified: llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll Tue Nov 28 09:15:09 2017
@@ -351,7 +351,7 @@ define i8 @test_int_x86_avx512_mask_fpcl
; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: addb %cl, %al
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 2, i8 %x1)
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 4, i8 -1)
@@ -369,7 +369,7 @@ define i16 at test_int_x86_avx512_mask_fpcl
; CHECK-NEXT: vfpclassps $4, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: addl %ecx, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 %x1)
%res1 = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 -1)
@@ -388,7 +388,7 @@ define i8 @test_int_x86_avx512_mask_fpcl
; CHECK-NEXT: vfpclasssd $4, %xmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: addb %cl, %al
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 2, i8 %x1)
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 4, i8 -1)
@@ -401,7 +401,7 @@ define i8 @test_int_x86_avx512_mask_fpcl
; CHECK: ## BB#0:
; CHECK-NEXT: vfpclasssd $4, (%rdi), %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%x0 = load <2 x double>, <2 x double>* %x0ptr
%res = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 4, i8 -1)
@@ -419,7 +419,7 @@ define i8 @test_int_x86_avx512_mask_fpcl
; CHECK-NEXT: vfpclassss $4, %xmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: addb %cl, %al
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 %x1)
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 -1)
@@ -432,7 +432,7 @@ define i8 @test_int_x86_avx512_mask_fpcl
; CHECK: ## BB#0:
; CHECK-NEXT: vfpclassss $4, (%rdi), %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%x0 = load <4 x float>, <4 x float>* %x0ptr
%res = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 -1)
@@ -446,7 +446,7 @@ define i16 at test_int_x86_avx512_cvtd2mask
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovd2m %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i16 @llvm.x86.avx512.cvtd2mask.512(<16 x i32> %x0)
ret i16 %res
@@ -459,7 +459,7 @@ define i8 at test_int_x86_avx512_cvtq2mask_
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovq2m %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.cvtq2mask.512(<8 x i64> %x0)
ret i8 %res
Modified: llvm/trunk/test/CodeGen/X86/avx512dq-mask-op.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512dq-mask-op.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512dq-mask-op.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512dq-mask-op.ll Tue Nov 28 09:15:09 2017
@@ -7,7 +7,7 @@ define i8 @mask8(i8 %x) {
; CHECK-NEXT: kmovd %edi, %k0
; CHECK-NEXT: knotb %k0, %k0
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%m0 = bitcast i8 %x to <8 x i1>
%m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
@@ -57,7 +57,7 @@ define i8 @mand8_mem(<8 x i1>* %x, <8 x
; CHECK-NEXT: kxorb %k1, %k0, %k0
; CHECK-NEXT: korb %k0, %k2, %k0
; CHECK-NEXT: kmovd %k0, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%ma = load <8 x i1>, <8 x i1>* %x
%mb = load <8 x i1>, <8 x i1>* %y
Modified: llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll Tue Nov 28 09:15:09 2017
@@ -1673,7 +1673,7 @@ declare <4 x double> @llvm.x86.avx512.ma
define <4 x double>@test_int_x86_avx512_mask_broadcastf64x2_256(<2 x double> %x0, <4 x double> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x2_256:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x18,0xd0,0x01]
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vinsertf64x2 $1, %xmm0, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0xfd,0x29,0x18,0xc8,0x01]
@@ -1708,7 +1708,7 @@ declare <4 x i64> @llvm.x86.avx512.mask.
define <4 x i64>@test_int_x86_avx512_mask_broadcasti64x2_256(<2 x i64> %x0, <4 x i64> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x2_256:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x38,0xd0,0x01]
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vinserti64x2 $1, %xmm0, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0xfd,0x29,0x38,0xc8,0x01]
@@ -1743,7 +1743,7 @@ declare <8 x float> @llvm.x86.avx512.mas
define <8 x float>@test_int_x86_avx512_mask_broadcastf32x2_256(<4 x float> %x0, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x2_256:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x18,0xd0,0x01]
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vinsertf32x4 $1, %xmm0, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0x7d,0x29,0x18,0xc8,0x01]
@@ -1764,7 +1764,7 @@ declare <8 x i32> @llvm.x86.avx512.mask.
define <8 x i32>@test_int_x86_avx512_mask_broadcasti32x2_256(<4 x i32> %x0, <8 x i32> %x2, i8 %x3, i64 * %y_ptr) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x2_256:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vmovq (%rsi), %xmm2 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x7e,0x16]
; CHECK-NEXT: ## xmm2 = mem[0],zero
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
Modified: llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics.ll Tue Nov 28 09:15:09 2017
@@ -560,7 +560,7 @@ define i8 @test_int_x86_avx512_mask_fpcl
; CHECK-NEXT: vfpclassps $4, %xmm0, %k0 ## encoding: [0x62,0xf3,0x7d,0x08,0x66,0xc0,0x04]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 2, i8 %x1)
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 4, i8 -1)
@@ -579,7 +579,7 @@ define i8 @test_int_x86_avx512_mask_fpcl
; CHECK-NEXT: vfpclassps $4, %ymm0, %k0 ## encoding: [0x62,0xf3,0x7d,0x28,0x66,0xc0,0x04]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 2, i8 %x1)
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 4, i8 -1)
@@ -598,7 +598,7 @@ define i8 @test_int_x86_avx512_mask_fpcl
; CHECK-NEXT: vfpclasspd $2, %xmm0, %k0 ## encoding: [0x62,0xf3,0xfd,0x08,0x66,0xc0,0x02]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 4, i8 %x1)
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 2, i8 -1)
@@ -617,7 +617,7 @@ define i8 @test_int_x86_avx512_mask_fpcl
; CHECK-NEXT: vfpclasspd $4, %ymm0, %k0 ## encoding: [0x62,0xf3,0xfd,0x28,0x66,0xc0,0x04]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 2, i8 %x1)
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 4, i8 -1)
@@ -632,7 +632,7 @@ define i8 at test_int_x86_avx512_cvtd2mask_
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovd2m %xmm0, %k0 ## encoding: [0x62,0xf2,0x7e,0x08,0x39,0xc0]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.cvtd2mask.128(<4 x i32> %x0)
ret i8 %res
@@ -645,7 +645,7 @@ define i8 at test_int_x86_avx512_cvtd2mask_
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovd2m %ymm0, %k0 ## encoding: [0x62,0xf2,0x7e,0x28,0x39,0xc0]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.cvtd2mask.256(<8 x i32> %x0)
ret i8 %res
@@ -658,7 +658,7 @@ define i8 at test_int_x86_avx512_cvtq2mask_
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovq2m %xmm0, %k0 ## encoding: [0x62,0xf2,0xfe,0x08,0x39,0xc0]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.cvtq2mask.128(<2 x i64> %x0)
ret i8 %res
@@ -671,7 +671,7 @@ define i8 at test_int_x86_avx512_cvtq2mask_
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovq2m %ymm0, %k0 ## encoding: [0x62,0xf2,0xfe,0x28,0x39,0xc0]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.cvtq2mask.256(<4 x i64> %x0)
ret i8 %res
Modified: llvm/trunk/test/CodeGen/X86/avx512f-vec-test-testn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512f-vec-test-testn.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512f-vec-test-testn.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512f-vec-test-testn.ll Tue Nov 28 09:15:09 2017
@@ -7,7 +7,7 @@ define zeroext i8 @TEST_mm512_test_epi64
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vptestmq %zmm0, %zmm1, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
@@ -23,7 +23,7 @@ define zeroext i16 @TEST_mm512_test_epi3
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vptestmd %zmm0, %zmm1, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
@@ -41,7 +41,7 @@ define zeroext i8 @TEST_mm512_mask_test_
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vptestmq %zmm0, %zmm1, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
@@ -60,7 +60,7 @@ define zeroext i16 @TEST_mm512_mask_test
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vptestmd %zmm0, %zmm1, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
@@ -79,7 +79,7 @@ define zeroext i8 @TEST_mm512_testn_epi6
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vptestnmq %zmm0, %zmm1, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
@@ -95,7 +95,7 @@ define zeroext i16 @TEST_mm512_testn_epi
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vptestnmd %zmm0, %zmm1, %k0
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
@@ -113,7 +113,7 @@ define zeroext i8 @TEST_mm512_mask_testn
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vptestnmq %zmm0, %zmm1, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
@@ -132,7 +132,7 @@ define zeroext i16 @TEST_mm512_mask_test
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vptestnmd %zmm0, %zmm1, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll Tue Nov 28 09:15:09 2017
@@ -1064,7 +1064,7 @@ define i8 @test_pcmpeq_d_256(<8 x i32> %
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x28,0x76,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.d.256(<8 x i32> %a, <8 x i32> %b, i8 -1)
ret i8 %res
@@ -1076,7 +1076,7 @@ define i8 @test_mask_pcmpeq_d_256(<8 x i
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x76,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.d.256(<8 x i32> %a, <8 x i32> %b, i8 %mask)
ret i8 %res
@@ -1089,7 +1089,7 @@ define i8 @test_pcmpeq_q_256(<4 x i64> %
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf2,0xfd,0x28,0x29,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.256(<4 x i64> %a, <4 x i64> %b, i8 -1)
ret i8 %res
@@ -1101,7 +1101,7 @@ define i8 @test_mask_pcmpeq_q_256(<4 x i
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x29,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.256(<4 x i64> %a, <4 x i64> %b, i8 %mask)
ret i8 %res
@@ -1114,7 +1114,7 @@ define i8 @test_pcmpgt_d_256(<8 x i32> %
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x28,0x66,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.d.256(<8 x i32> %a, <8 x i32> %b, i8 -1)
ret i8 %res
@@ -1126,7 +1126,7 @@ define i8 @test_mask_pcmpgt_d_256(<8 x i
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x66,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.d.256(<8 x i32> %a, <8 x i32> %b, i8 %mask)
ret i8 %res
@@ -1139,7 +1139,7 @@ define i8 @test_pcmpgt_q_256(<4 x i64> %
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf2,0xfd,0x28,0x37,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.256(<4 x i64> %a, <4 x i64> %b, i8 -1)
ret i8 %res
@@ -1151,7 +1151,7 @@ define i8 @test_mask_pcmpgt_q_256(<4 x i
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x37,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.256(<4 x i64> %a, <4 x i64> %b, i8 %mask)
ret i8 %res
@@ -1164,7 +1164,7 @@ define i8 @test_pcmpeq_d_128(<4 x i32> %
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x76,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.d.128(<4 x i32> %a, <4 x i32> %b, i8 -1)
ret i8 %res
@@ -1176,7 +1176,7 @@ define i8 @test_mask_pcmpeq_d_128(<4 x i
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x76,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.d.128(<4 x i32> %a, <4 x i32> %b, i8 %mask)
ret i8 %res
@@ -1189,7 +1189,7 @@ define i8 @test_pcmpeq_q_128(<2 x i64> %
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf2,0xfd,0x08,0x29,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.128(<2 x i64> %a, <2 x i64> %b, i8 -1)
ret i8 %res
@@ -1201,7 +1201,7 @@ define i8 @test_mask_pcmpeq_q_128(<2 x i
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x29,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.128(<2 x i64> %a, <2 x i64> %b, i8 %mask)
ret i8 %res
@@ -1214,7 +1214,7 @@ define i8 @test_pcmpgt_d_128(<4 x i32> %
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x66,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.d.128(<4 x i32> %a, <4 x i32> %b, i8 -1)
ret i8 %res
@@ -1226,7 +1226,7 @@ define i8 @test_mask_pcmpgt_d_128(<4 x i
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x66,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.d.128(<4 x i32> %a, <4 x i32> %b, i8 %mask)
ret i8 %res
@@ -1239,7 +1239,7 @@ define i8 @test_pcmpgt_q_128(<2 x i64> %
; CHECK: ## BB#0:
; CHECK-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf2,0xfd,0x08,0x37,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.128(<2 x i64> %a, <2 x i64> %b, i8 -1)
ret i8 %res
@@ -1251,7 +1251,7 @@ define i8 @test_mask_pcmpgt_q_128(<2 x i
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x37,0xc1]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.128(<2 x i64> %a, <2 x i64> %b, i8 %mask)
ret i8 %res
@@ -5867,7 +5867,7 @@ declare <8 x float> @llvm.x86.avx512.mas
define <8 x float>@test_int_x86_avx512_mask_broadcastf32x4_256(<4 x float> %x0, <8 x float> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x4_256:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x18,0xd0,0x01]
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vinsertf32x4 $1, %xmm0, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0x7d,0x29,0x18,0xc8,0x01]
@@ -5900,7 +5900,7 @@ declare <8 x i32> @llvm.x86.avx512.mask.
define <8 x i32>@test_int_x86_avx512_mask_broadcasti32x4_256(<4 x i32> %x0, <8 x i32> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x4_256:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x38,0xd0,0x01]
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; CHECK-NEXT: vinserti32x4 $1, %xmm0, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0x7d,0x29,0x38,0xc8,0x01]
@@ -6003,7 +6003,7 @@ define i8 at test_int_x86_avx512_ptestm_d_1
; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.ptestm.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestm.d.128(<4 x i32> %x0, <4 x i32> %x1, i8-1)
@@ -6022,7 +6022,7 @@ define i8 at test_int_x86_avx512_ptestm_d_2
; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.ptestm.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestm.d.256(<8 x i32> %x0, <8 x i32> %x1, i8-1)
@@ -6041,7 +6041,7 @@ define i8 at test_int_x86_avx512_ptestm_q_1
; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.ptestm.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestm.q.128(<2 x i64> %x0, <2 x i64> %x1, i8-1)
@@ -6060,7 +6060,7 @@ define i8 at test_int_x86_avx512_ptestm_q_2
; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.ptestm.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestm.q.256(<4 x i64> %x0, <4 x i64> %x1, i8-1)
@@ -6079,7 +6079,7 @@ define i8 at test_int_x86_avx512_ptestnm_d_
; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.ptestnm.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestnm.d.128(<4 x i32> %x0, <4 x i32> %x1, i8-1)
@@ -6098,7 +6098,7 @@ define i8 at test_int_x86_avx512_ptestnm_d_
; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.ptestnm.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestnm.d.256(<8 x i32> %x0, <8 x i32> %x1, i8-1)
@@ -6117,7 +6117,7 @@ define i8 at test_int_x86_avx512_ptestnm_q_
; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.ptestnm.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestnm.q.128(<2 x i64> %x0, <2 x i64> %x1, i8-1)
@@ -6136,7 +6136,7 @@ define i8 at test_int_x86_avx512_ptestnm_q_
; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.ptestnm.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2)
%res1 = call i8 @llvm.x86.avx512.ptestnm.q.256(<4 x i64> %x0, <4 x i64> %x1, i8-1)
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll Tue Nov 28 09:15:09 2017
@@ -718,7 +718,7 @@ define i8 @test_cmpps_256(<8 x float> %a
; CHECK: ## BB#0:
; CHECK-NEXT: vcmpleps %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0x7c,0x28,0xc2,0xc1,0x02]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 2, i8 -1)
ret i8 %res
@@ -730,7 +730,7 @@ define i8 @test_cmpps_128(<4 x float> %a
; CHECK: ## BB#0:
; CHECK-NEXT: vcmpleps %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7c,0x08,0xc2,0xc1,0x02]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %a, <4 x float> %b, i32 2, i8 -1)
ret i8 %res
@@ -742,7 +742,7 @@ define i8 @test_cmppd_256(<4 x double> %
; CHECK: ## BB#0:
; CHECK-NEXT: vcmplepd %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0xfd,0x28,0xc2,0xc1,0x02]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %a, <4 x double> %b, i32 2, i8 -1)
ret i8 %res
@@ -754,7 +754,7 @@ define i8 @test_cmppd_128(<2 x double> %
; CHECK: ## BB#0:
; CHECK-NEXT: vcmplepd %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0xfd,0x08,0xc2,0xc1,0x02]
; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0]
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %a, <2 x double> %b, i32 2, i8 -1)
ret i8 %res
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll Tue Nov 28 09:15:09 2017
@@ -45,12 +45,12 @@ define <8 x i32> @test256_3(<8 x i32> %x
;
; NoVLX-LABEL: test256_3:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def>
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k1
; NoVLX-NEXT: vpblendmd %zmm2, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%mask = icmp sge <8 x i32> %x, %y
%max = select <8 x i1> %mask, <8 x i32> %x1, <8 x i32> %y
@@ -86,12 +86,12 @@ define <8 x i32> @test256_5(<8 x i32> %x
;
; NoVLX-LABEL: test256_5:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpeqd %zmm2, %zmm0, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %yp, align 4
%mask = icmp eq <8 x i32> %x, %y
@@ -108,12 +108,12 @@ define <8 x i32> @test256_5b(<8 x i32> %
;
; NoVLX-LABEL: test256_5b:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpeqd %zmm0, %zmm2, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %yp, align 4
%mask = icmp eq <8 x i32> %y, %x
@@ -130,12 +130,12 @@ define <8 x i32> @test256_6(<8 x i32> %x
;
; NoVLX-LABEL: test256_6:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpgtd %zmm2, %zmm0, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
%mask = icmp sgt <8 x i32> %x, %y
@@ -152,12 +152,12 @@ define <8 x i32> @test256_6b(<8 x i32> %
;
; NoVLX-LABEL: test256_6b:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpgtd %zmm2, %zmm0, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
%mask = icmp slt <8 x i32> %y, %x
@@ -174,12 +174,12 @@ define <8 x i32> @test256_7(<8 x i32> %x
;
; NoVLX-LABEL: test256_7:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpled %zmm2, %zmm0, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
%mask = icmp sle <8 x i32> %x, %y
@@ -196,12 +196,12 @@ define <8 x i32> @test256_7b(<8 x i32> %
;
; NoVLX-LABEL: test256_7b:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpled %zmm2, %zmm0, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
%mask = icmp sge <8 x i32> %y, %x
@@ -218,12 +218,12 @@ define <8 x i32> @test256_8(<8 x i32> %x
;
; NoVLX-LABEL: test256_8:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpleud %zmm2, %zmm0, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
%mask = icmp ule <8 x i32> %x, %y
@@ -240,12 +240,12 @@ define <8 x i32> @test256_8b(<8 x i32> %
;
; NoVLX-LABEL: test256_8b:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpnltud %zmm0, %zmm2, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
%mask = icmp uge <8 x i32> %y, %x
@@ -263,14 +263,14 @@ define <8 x i32> @test256_9(<8 x i32> %x
;
; NoVLX-LABEL: test256_9:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
-; NoVLX-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def>
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
+; NoVLX-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k1
; NoVLX-NEXT: vpcmpeqd %zmm3, %zmm2, %k1 {%k1}
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%mask1 = icmp eq <8 x i32> %x1, %y1
%mask0 = icmp eq <8 x i32> %x, %y
@@ -336,14 +336,14 @@ define <8 x i32> @test256_12(<8 x i32> %
;
; NoVLX-LABEL: test256_12:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def>
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm3
; NoVLX-NEXT: vpcmpleud %zmm3, %zmm0, %k1
; NoVLX-NEXT: vpcmpled %zmm1, %zmm2, %k1 {%k1}
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%mask1 = icmp sge <8 x i32> %x1, %y1
%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
@@ -383,12 +383,12 @@ define <8 x i32> @test256_14(<8 x i32> %
;
; NoVLX-LABEL: test256_14:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm2
; NoVLX-NEXT: vpcmpled %zmm2, %zmm0, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%yb = load i32, i32* %yb.ptr, align 4
%y.0 = insertelement <8 x i32> undef, i32 %yb, i32 0
@@ -408,14 +408,14 @@ define <8 x i32> @test256_15(<8 x i32> %
;
; NoVLX-LABEL: test256_15:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def>
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm3
; NoVLX-NEXT: vpcmpgtd %zmm3, %zmm0, %k1
; NoVLX-NEXT: vpcmpled %zmm1, %zmm2, %k1 {%k1}
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%mask1 = icmp sge <8 x i32> %x1, %y1
%yb = load i32, i32* %yb.ptr, align 4
@@ -462,12 +462,12 @@ define <8 x i32> @test256_17(<8 x i32> %
;
; NoVLX-LABEL: test256_17:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpneqd %zmm2, %zmm0, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %yp, align 4
%mask = icmp ne <8 x i32> %x, %y
@@ -484,12 +484,12 @@ define <8 x i32> @test256_18(<8 x i32> %
;
; NoVLX-LABEL: test256_18:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpneqd %zmm0, %zmm2, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %yp, align 4
%mask = icmp ne <8 x i32> %y, %x
@@ -506,12 +506,12 @@ define <8 x i32> @test256_19(<8 x i32> %
;
; NoVLX-LABEL: test256_19:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpnltud %zmm2, %zmm0, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %yp, align 4
%mask = icmp uge <8 x i32> %x, %y
@@ -528,12 +528,12 @@ define <8 x i32> @test256_20(<8 x i32> %
;
; NoVLX-LABEL: test256_20:
; NoVLX: # BB#0:
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqu (%rdi), %ymm2
; NoVLX-NEXT: vpcmpnltud %zmm0, %zmm2, %k1
; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NoVLX-NEXT: retq
%y = load <8 x i32>, <8 x i32>* %yp, align 4
%mask = icmp uge <8 x i32> %y, %x
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll Tue Nov 28 09:15:09 2017
@@ -1208,7 +1208,7 @@ define zeroext i16 @test_vpcmpeqw_v8i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqw_v8i1_v16i1_mask:
@@ -1218,7 +1218,7 @@ define zeroext i16 @test_vpcmpeqw_v8i1_v
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -1235,7 +1235,7 @@ define zeroext i16 @test_vpcmpeqw_v8i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqw_v8i1_v16i1_mask_mem:
@@ -1245,7 +1245,7 @@ define zeroext i16 @test_vpcmpeqw_v8i1_v
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -1264,7 +1264,7 @@ define zeroext i16 @test_masked_vpcmpeqw
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v16i1_mask:
@@ -1275,7 +1275,7 @@ define zeroext i16 @test_masked_vpcmpeqw
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -1295,7 +1295,7 @@ define zeroext i16 @test_masked_vpcmpeqw
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v16i1_mask_mem:
@@ -1306,7 +1306,7 @@ define zeroext i16 @test_masked_vpcmpeqw
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4200,7 +4200,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v8i1_mask:
@@ -4239,7 +4239,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4256,7 +4256,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v8i1_mask_mem:
@@ -4295,7 +4295,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4314,7 +4314,7 @@ define zeroext i8 @test_masked_vpcmpeqd_
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v8i1_mask:
@@ -4371,7 +4371,7 @@ define zeroext i8 @test_masked_vpcmpeqd_
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4392,7 +4392,7 @@ define zeroext i8 @test_masked_vpcmpeqd_
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v8i1_mask_mem:
@@ -4449,7 +4449,7 @@ define zeroext i8 @test_masked_vpcmpeqd_
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4471,7 +4471,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v8i1_mask_mem_b:
@@ -4511,7 +4511,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4531,7 +4531,7 @@ define zeroext i8 @test_masked_vpcmpeqd_
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v8i1_mask_mem_b:
@@ -4589,7 +4589,7 @@ define zeroext i8 @test_masked_vpcmpeqd_
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4612,7 +4612,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v16i1_mask:
@@ -4650,7 +4650,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4667,7 +4667,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v16i1_mask_mem:
@@ -4705,7 +4705,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4724,7 +4724,7 @@ define zeroext i16 @test_masked_vpcmpeqd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v16i1_mask:
@@ -4780,7 +4780,7 @@ define zeroext i16 @test_masked_vpcmpeqd
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4801,7 +4801,7 @@ define zeroext i16 @test_masked_vpcmpeqd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v16i1_mask_mem:
@@ -4857,7 +4857,7 @@ define zeroext i16 @test_masked_vpcmpeqd
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4879,7 +4879,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v16i1_mask_mem_b:
@@ -4918,7 +4918,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -4938,7 +4938,7 @@ define zeroext i16 @test_masked_vpcmpeqd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v16i1_mask_mem_b:
@@ -4995,7 +4995,7 @@ define zeroext i16 @test_masked_vpcmpeqd
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -5698,19 +5698,19 @@ define zeroext i16 @test_vpcmpeqd_v8i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqd_v8i1_v16i1_mask:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -5727,19 +5727,19 @@ define zeroext i16 @test_vpcmpeqd_v8i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqd_v8i1_v16i1_mask_mem:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -5758,20 +5758,20 @@ define zeroext i16 @test_masked_vpcmpeqd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v16i1_mask:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -5791,20 +5791,20 @@ define zeroext i16 @test_masked_vpcmpeqd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v16i1_mask_mem:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -5825,19 +5825,19 @@ define zeroext i16 @test_vpcmpeqd_v8i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqd_v8i1_v16i1_mask_mem_b:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -5857,20 +5857,20 @@ define zeroext i16 @test_masked_vpcmpeqd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v16i1_mask_mem_b:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -5904,8 +5904,8 @@ define zeroext i32 @test_vpcmpeqd_v8i1_v
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
@@ -5977,7 +5977,7 @@ define zeroext i32 @test_vpcmpeqd_v8i1_v
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -6052,8 +6052,8 @@ define zeroext i32 @test_masked_vpcmpeqd
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -6129,7 +6129,7 @@ define zeroext i32 @test_masked_vpcmpeqd
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
@@ -6207,7 +6207,7 @@ define zeroext i32 @test_vpcmpeqd_v8i1_v
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -6283,7 +6283,7 @@ define zeroext i32 @test_masked_vpcmpeqd
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
@@ -6362,8 +6362,8 @@ define zeroext i64 @test_vpcmpeqd_v8i1_v
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
@@ -6440,7 +6440,7 @@ define zeroext i64 @test_vpcmpeqd_v8i1_v
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -6520,8 +6520,8 @@ define zeroext i64 @test_masked_vpcmpeqd
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -6602,7 +6602,7 @@ define zeroext i64 @test_masked_vpcmpeqd
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
@@ -6685,7 +6685,7 @@ define zeroext i64 @test_vpcmpeqd_v8i1_v
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -6766,7 +6766,7 @@ define zeroext i64 @test_masked_vpcmpeqd
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
@@ -8520,7 +8520,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v8i1_mask:
@@ -8543,7 +8543,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -8560,7 +8560,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v8i1_mask_mem:
@@ -8583,7 +8583,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -8602,7 +8602,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v8i1_mask:
@@ -8635,7 +8635,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -8656,7 +8656,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v8i1_mask_mem:
@@ -8689,7 +8689,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -8711,7 +8711,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v8i1_mask_mem_b:
@@ -8735,7 +8735,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -8755,7 +8755,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v8i1_mask_mem_b:
@@ -8789,7 +8789,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -8812,7 +8812,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v16i1_mask:
@@ -8834,7 +8834,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -8851,7 +8851,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v16i1_mask_mem:
@@ -8873,7 +8873,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -8892,7 +8892,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v16i1_mask:
@@ -8924,7 +8924,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -8945,7 +8945,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v16i1_mask_mem:
@@ -8977,7 +8977,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -8999,7 +8999,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v16i1_mask_mem_b:
@@ -9022,7 +9022,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -9042,7 +9042,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v16i1_mask_mem_b:
@@ -9075,7 +9075,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -9730,7 +9730,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -9771,7 +9771,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -9788,7 +9788,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -9829,7 +9829,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -9848,7 +9848,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -9907,7 +9907,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -9928,7 +9928,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -9987,7 +9987,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -10009,7 +10009,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -10051,7 +10051,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -10071,7 +10071,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -10131,7 +10131,7 @@ define zeroext i8 @test_masked_vpcmpeqq_
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -10154,7 +10154,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -10194,7 +10194,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -10211,7 +10211,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -10251,7 +10251,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -10270,7 +10270,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -10328,7 +10328,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -10349,7 +10349,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -10407,7 +10407,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -10429,7 +10429,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -10470,7 +10470,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -10490,7 +10490,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -10549,7 +10549,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -11276,7 +11276,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -11284,7 +11284,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -11301,7 +11301,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -11309,7 +11309,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -11328,7 +11328,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -11337,7 +11337,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -11357,7 +11357,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -11366,7 +11366,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -11387,7 +11387,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -11395,7 +11395,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -11415,7 +11415,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -11424,7 +11424,7 @@ define zeroext i16 @test_masked_vpcmpeqq
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -13569,7 +13569,7 @@ define zeroext i16 @test_vpcmpsgtw_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v16i1_mask:
@@ -13579,7 +13579,7 @@ define zeroext i16 @test_vpcmpsgtw_v8i1_
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -13596,7 +13596,7 @@ define zeroext i16 @test_vpcmpsgtw_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v16i1_mask_mem:
@@ -13606,7 +13606,7 @@ define zeroext i16 @test_vpcmpsgtw_v8i1_
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -13625,7 +13625,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v16i1_mask:
@@ -13636,7 +13636,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -13656,7 +13656,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v16i1_mask_mem:
@@ -13667,7 +13667,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -16561,7 +16561,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v8i1_mask:
@@ -16600,7 +16600,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -16617,7 +16617,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v8i1_mask_mem:
@@ -16656,7 +16656,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -16675,7 +16675,7 @@ define zeroext i8 @test_masked_vpcmpsgtd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v8i1_mask:
@@ -16732,7 +16732,7 @@ define zeroext i8 @test_masked_vpcmpsgtd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -16753,7 +16753,7 @@ define zeroext i8 @test_masked_vpcmpsgtd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v8i1_mask_mem:
@@ -16810,7 +16810,7 @@ define zeroext i8 @test_masked_vpcmpsgtd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -16832,7 +16832,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v8i1_mask_mem_b:
@@ -16872,7 +16872,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -16892,7 +16892,7 @@ define zeroext i8 @test_masked_vpcmpsgtd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v8i1_mask_mem_b:
@@ -16950,7 +16950,7 @@ define zeroext i8 @test_masked_vpcmpsgtd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -16973,7 +16973,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v16i1_mask:
@@ -17011,7 +17011,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17028,7 +17028,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v16i1_mask_mem:
@@ -17066,7 +17066,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17085,7 +17085,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v16i1_mask:
@@ -17141,7 +17141,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17162,7 +17162,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v16i1_mask_mem:
@@ -17218,7 +17218,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17240,7 +17240,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v16i1_mask_mem_b:
@@ -17279,7 +17279,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17299,7 +17299,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v16i1_mask_mem_b:
@@ -17356,7 +17356,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -18059,19 +18059,19 @@ define zeroext i16 @test_vpcmpsgtd_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v16i1_mask:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -18088,19 +18088,19 @@ define zeroext i16 @test_vpcmpsgtd_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v16i1_mask_mem:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -18119,20 +18119,20 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v16i1_mask:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -18152,20 +18152,20 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v16i1_mask_mem:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -18186,19 +18186,19 @@ define zeroext i16 @test_vpcmpsgtd_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v16i1_mask_mem_b:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -18218,20 +18218,20 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v16i1_mask_mem_b:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -18265,8 +18265,8 @@ define zeroext i32 @test_vpcmpsgtd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
@@ -18338,7 +18338,7 @@ define zeroext i32 @test_vpcmpsgtd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -18413,8 +18413,8 @@ define zeroext i32 @test_masked_vpcmpsgt
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -18490,7 +18490,7 @@ define zeroext i32 @test_masked_vpcmpsgt
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
@@ -18568,7 +18568,7 @@ define zeroext i32 @test_vpcmpsgtd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -18644,7 +18644,7 @@ define zeroext i32 @test_masked_vpcmpsgt
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
@@ -18723,8 +18723,8 @@ define zeroext i64 @test_vpcmpsgtd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
@@ -18801,7 +18801,7 @@ define zeroext i64 @test_vpcmpsgtd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -18881,8 +18881,8 @@ define zeroext i64 @test_masked_vpcmpsgt
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -18963,7 +18963,7 @@ define zeroext i64 @test_masked_vpcmpsgt
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
@@ -19046,7 +19046,7 @@ define zeroext i64 @test_vpcmpsgtd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -19127,7 +19127,7 @@ define zeroext i64 @test_masked_vpcmpsgt
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
@@ -20881,7 +20881,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v8i1_mask:
@@ -20904,7 +20904,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -20921,7 +20921,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v8i1_mask_mem:
@@ -20944,7 +20944,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -20963,7 +20963,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v8i1_mask:
@@ -20996,7 +20996,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21017,7 +21017,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v8i1_mask_mem:
@@ -21050,7 +21050,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21072,7 +21072,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v8i1_mask_mem_b:
@@ -21096,7 +21096,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21116,7 +21116,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v8i1_mask_mem_b:
@@ -21150,7 +21150,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21173,7 +21173,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v16i1_mask:
@@ -21195,7 +21195,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21212,7 +21212,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v16i1_mask_mem:
@@ -21234,7 +21234,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21253,7 +21253,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v16i1_mask:
@@ -21285,7 +21285,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21306,7 +21306,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v16i1_mask_mem:
@@ -21338,7 +21338,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21360,7 +21360,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v16i1_mask_mem_b:
@@ -21383,7 +21383,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21403,7 +21403,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v16i1_mask_mem_b:
@@ -21436,7 +21436,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22091,7 +22091,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22132,7 +22132,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22149,7 +22149,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22190,7 +22190,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22209,7 +22209,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22268,7 +22268,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22289,7 +22289,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22348,7 +22348,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22370,7 +22370,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22412,7 +22412,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22432,7 +22432,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22492,7 +22492,7 @@ define zeroext i8 @test_masked_vpcmpsgtq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22515,7 +22515,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22555,7 +22555,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22572,7 +22572,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22612,7 +22612,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22631,7 +22631,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22689,7 +22689,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22710,7 +22710,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22768,7 +22768,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22790,7 +22790,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22831,7 +22831,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -22851,7 +22851,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -22910,7 +22910,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -23637,7 +23637,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -23645,7 +23645,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -23662,7 +23662,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -23670,7 +23670,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -23689,7 +23689,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -23698,7 +23698,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -23718,7 +23718,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -23727,7 +23727,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -23748,7 +23748,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -23756,7 +23756,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -23776,7 +23776,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -23785,7 +23785,7 @@ define zeroext i16 @test_masked_vpcmpsgt
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -25960,7 +25960,7 @@ define zeroext i16 @test_vpcmpsgew_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgew_v8i1_v16i1_mask:
@@ -25972,7 +25972,7 @@ define zeroext i16 @test_vpcmpsgew_v8i1_
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -25989,7 +25989,7 @@ define zeroext i16 @test_vpcmpsgew_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgew_v8i1_v16i1_mask_mem:
@@ -26002,7 +26002,7 @@ define zeroext i16 @test_vpcmpsgew_v8i1_
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -26021,7 +26021,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v16i1_mask:
@@ -26034,7 +26034,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -26054,7 +26054,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v16i1_mask_mem:
@@ -26068,7 +26068,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29018,7 +29018,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v8i1_mask:
@@ -29059,7 +29059,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29076,7 +29076,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v8i1_mask_mem:
@@ -29118,7 +29118,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29137,7 +29137,7 @@ define zeroext i8 @test_masked_vpcmpsged
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v8i1_mask:
@@ -29194,7 +29194,7 @@ define zeroext i8 @test_masked_vpcmpsged
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29215,7 +29215,7 @@ define zeroext i8 @test_masked_vpcmpsged
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v8i1_mask_mem:
@@ -29273,7 +29273,7 @@ define zeroext i8 @test_masked_vpcmpsged
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29295,7 +29295,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltd (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v8i1_mask_mem_b:
@@ -29337,7 +29337,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29357,7 +29357,7 @@ define zeroext i8 @test_masked_vpcmpsged
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltd (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v8i1_mask_mem_b:
@@ -29415,7 +29415,7 @@ define zeroext i8 @test_masked_vpcmpsged
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29438,7 +29438,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v16i1_mask:
@@ -29478,7 +29478,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29495,7 +29495,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v16i1_mask_mem:
@@ -29536,7 +29536,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29555,7 +29555,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v16i1_mask:
@@ -29611,7 +29611,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29632,7 +29632,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v16i1_mask_mem:
@@ -29689,7 +29689,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29711,7 +29711,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltd (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v16i1_mask_mem_b:
@@ -29752,7 +29752,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -29772,7 +29772,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltd (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v16i1_mask_mem_b:
@@ -29829,7 +29829,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -30548,19 +30548,19 @@ define zeroext i16 @test_vpcmpsged_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsged_v8i1_v16i1_mask:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -30577,19 +30577,19 @@ define zeroext i16 @test_vpcmpsged_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsged_v8i1_v16i1_mask_mem:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -30608,20 +30608,20 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v16i1_mask:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -30641,20 +30641,20 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v16i1_mask_mem:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -30675,19 +30675,19 @@ define zeroext i16 @test_vpcmpsged_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltd (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsged_v8i1_v16i1_mask_mem_b:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -30707,20 +30707,20 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltd (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v16i1_mask_mem_b:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -30754,8 +30754,8 @@ define zeroext i32 @test_vpcmpsged_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
@@ -30827,7 +30827,7 @@ define zeroext i32 @test_vpcmpsged_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -30902,8 +30902,8 @@ define zeroext i32 @test_masked_vpcmpsge
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -30979,7 +30979,7 @@ define zeroext i32 @test_masked_vpcmpsge
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
@@ -31057,7 +31057,7 @@ define zeroext i32 @test_vpcmpsged_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -31133,7 +31133,7 @@ define zeroext i32 @test_masked_vpcmpsge
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
@@ -31212,8 +31212,8 @@ define zeroext i64 @test_vpcmpsged_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
@@ -31290,7 +31290,7 @@ define zeroext i64 @test_vpcmpsged_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -31370,8 +31370,8 @@ define zeroext i64 @test_masked_vpcmpsge
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -31452,7 +31452,7 @@ define zeroext i64 @test_masked_vpcmpsge
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
@@ -31535,7 +31535,7 @@ define zeroext i64 @test_vpcmpsged_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -31616,7 +31616,7 @@ define zeroext i64 @test_masked_vpcmpsge
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
@@ -33378,7 +33378,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v8i1_mask:
@@ -33403,7 +33403,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33420,7 +33420,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v8i1_mask_mem:
@@ -33446,7 +33446,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33465,7 +33465,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v8i1_mask:
@@ -33498,7 +33498,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33519,7 +33519,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v8i1_mask_mem:
@@ -33553,7 +33553,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33575,7 +33575,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v8i1_mask_mem_b:
@@ -33601,7 +33601,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33621,7 +33621,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v8i1_mask_mem_b:
@@ -33655,7 +33655,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33678,7 +33678,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v16i1_mask:
@@ -33702,7 +33702,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33719,7 +33719,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v16i1_mask_mem:
@@ -33744,7 +33744,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33763,7 +33763,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v16i1_mask:
@@ -33795,7 +33795,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33816,7 +33816,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v16i1_mask_mem:
@@ -33849,7 +33849,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33871,7 +33871,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v16i1_mask_mem_b:
@@ -33896,7 +33896,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -33916,7 +33916,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v16i1_mask_mem_b:
@@ -33949,7 +33949,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -34620,7 +34620,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -34663,7 +34663,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -34680,7 +34680,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -34724,7 +34724,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -34743,7 +34743,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -34804,7 +34804,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -34825,7 +34825,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -34887,7 +34887,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -34909,7 +34909,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -34953,7 +34953,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -34973,7 +34973,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -35035,7 +35035,7 @@ define zeroext i8 @test_masked_vpcmpsgeq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -35058,7 +35058,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -35100,7 +35100,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -35117,7 +35117,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -35160,7 +35160,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -35179,7 +35179,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -35239,7 +35239,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -35260,7 +35260,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -35321,7 +35321,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -35343,7 +35343,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -35386,7 +35386,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -35406,7 +35406,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -35467,7 +35467,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -36222,7 +36222,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -36230,7 +36230,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -36247,7 +36247,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -36255,7 +36255,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -36274,7 +36274,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -36283,7 +36283,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -36303,7 +36303,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -36312,7 +36312,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -36333,7 +36333,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -36341,7 +36341,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpnltq (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -36361,7 +36361,7 @@ define zeroext i16 @test_masked_vpcmpsge
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -36370,7 +36370,7 @@ define zeroext i16 @test_masked_vpcmpsge
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpnltq (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -38551,7 +38551,7 @@ define zeroext i16 @test_vpcmpultw_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultw_v8i1_v16i1_mask:
@@ -38564,7 +38564,7 @@ define zeroext i16 @test_vpcmpultw_v8i1_
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -38581,7 +38581,7 @@ define zeroext i16 @test_vpcmpultw_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultw_v8i1_v16i1_mask_mem:
@@ -38594,7 +38594,7 @@ define zeroext i16 @test_vpcmpultw_v8i1_
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -38613,7 +38613,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v16i1_mask:
@@ -38627,7 +38627,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -38647,7 +38647,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v16i1_mask_mem:
@@ -38661,7 +38661,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -41623,7 +41623,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v8i1_mask:
@@ -41665,7 +41665,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -41682,7 +41682,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v8i1_mask_mem:
@@ -41724,7 +41724,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -41743,7 +41743,7 @@ define zeroext i8 @test_masked_vpcmpultd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v8i1_mask:
@@ -41803,7 +41803,7 @@ define zeroext i8 @test_masked_vpcmpultd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -41824,7 +41824,7 @@ define zeroext i8 @test_masked_vpcmpultd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v8i1_mask_mem:
@@ -41884,7 +41884,7 @@ define zeroext i8 @test_masked_vpcmpultd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -41906,7 +41906,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v8i1_mask_mem_b:
@@ -41949,7 +41949,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -41969,7 +41969,7 @@ define zeroext i8 @test_masked_vpcmpultd
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v8i1_mask_mem_b:
@@ -42030,7 +42030,7 @@ define zeroext i8 @test_masked_vpcmpultd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -42053,7 +42053,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v16i1_mask:
@@ -42094,7 +42094,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -42111,7 +42111,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v16i1_mask_mem:
@@ -42152,7 +42152,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -42171,7 +42171,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v16i1_mask:
@@ -42230,7 +42230,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -42251,7 +42251,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v16i1_mask_mem:
@@ -42310,7 +42310,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -42332,7 +42332,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v16i1_mask_mem_b:
@@ -42374,7 +42374,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -42394,7 +42394,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v16i1_mask_mem_b:
@@ -42454,7 +42454,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -43193,19 +43193,19 @@ define zeroext i16 @test_vpcmpultd_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultd_v8i1_v16i1_mask:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -43222,19 +43222,19 @@ define zeroext i16 @test_vpcmpultd_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultd_v8i1_v16i1_mask_mem:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -43253,20 +43253,20 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v16i1_mask:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -43286,20 +43286,20 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v16i1_mask_mem:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -43320,19 +43320,19 @@ define zeroext i16 @test_vpcmpultd_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultd_v8i1_v16i1_mask_mem_b:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -43352,20 +43352,20 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v16i1_mask_mem_b:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -43399,8 +43399,8 @@ define zeroext i32 @test_vpcmpultd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
@@ -43472,7 +43472,7 @@ define zeroext i32 @test_vpcmpultd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -43547,8 +43547,8 @@ define zeroext i32 @test_masked_vpcmpult
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -43624,7 +43624,7 @@ define zeroext i32 @test_masked_vpcmpult
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
@@ -43702,7 +43702,7 @@ define zeroext i32 @test_vpcmpultd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -43778,7 +43778,7 @@ define zeroext i32 @test_masked_vpcmpult
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
@@ -43857,8 +43857,8 @@ define zeroext i64 @test_vpcmpultd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
@@ -43935,7 +43935,7 @@ define zeroext i64 @test_vpcmpultd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -44015,8 +44015,8 @@ define zeroext i64 @test_masked_vpcmpult
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -44097,7 +44097,7 @@ define zeroext i64 @test_masked_vpcmpult
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
@@ -44180,7 +44180,7 @@ define zeroext i64 @test_vpcmpultd_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -44261,7 +44261,7 @@ define zeroext i64 @test_masked_vpcmpult
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
@@ -46033,7 +46033,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v8i1_mask:
@@ -46059,7 +46059,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46076,7 +46076,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v8i1_mask_mem:
@@ -46102,7 +46102,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46121,7 +46121,7 @@ define zeroext i8 @test_masked_vpcmpultq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v8i1_mask:
@@ -46157,7 +46157,7 @@ define zeroext i8 @test_masked_vpcmpultq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46178,7 +46178,7 @@ define zeroext i8 @test_masked_vpcmpultq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v8i1_mask_mem:
@@ -46214,7 +46214,7 @@ define zeroext i8 @test_masked_vpcmpultq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46236,7 +46236,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v8i1_mask_mem_b:
@@ -46263,7 +46263,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46283,7 +46283,7 @@ define zeroext i8 @test_masked_vpcmpultq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v8i1_mask_mem_b:
@@ -46320,7 +46320,7 @@ define zeroext i8 @test_masked_vpcmpultq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46343,7 +46343,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v16i1_mask:
@@ -46368,7 +46368,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46385,7 +46385,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v16i1_mask_mem:
@@ -46410,7 +46410,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46429,7 +46429,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v16i1_mask:
@@ -46464,7 +46464,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46485,7 +46485,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v16i1_mask_mem:
@@ -46520,7 +46520,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46542,7 +46542,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v16i1_mask_mem_b:
@@ -46568,7 +46568,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -46588,7 +46588,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v16i1_mask_mem_b:
@@ -46624,7 +46624,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -47315,7 +47315,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -47359,7 +47359,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -47376,7 +47376,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -47420,7 +47420,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -47439,7 +47439,7 @@ define zeroext i8 @test_masked_vpcmpultq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -47501,7 +47501,7 @@ define zeroext i8 @test_masked_vpcmpultq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -47522,7 +47522,7 @@ define zeroext i8 @test_masked_vpcmpultq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -47584,7 +47584,7 @@ define zeroext i8 @test_masked_vpcmpultq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -47606,7 +47606,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -47651,7 +47651,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -47671,7 +47671,7 @@ define zeroext i8 @test_masked_vpcmpultq
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -47734,7 +47734,7 @@ define zeroext i8 @test_masked_vpcmpultq
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -47757,7 +47757,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -47800,7 +47800,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -47817,7 +47817,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -47860,7 +47860,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -47879,7 +47879,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -47940,7 +47940,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -47961,7 +47961,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -48022,7 +48022,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -48044,7 +48044,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -48088,7 +48088,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -48108,7 +48108,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -48170,7 +48170,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -48933,7 +48933,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -48941,7 +48941,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -48958,7 +48958,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -48966,7 +48966,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -48985,7 +48985,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -48994,7 +48994,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -49014,7 +49014,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -49023,7 +49023,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -49044,7 +49044,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -49052,7 +49052,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -49072,7 +49072,7 @@ define zeroext i16 @test_masked_vpcmpult
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -49081,7 +49081,7 @@ define zeroext i16 @test_masked_vpcmpult
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50026,7 +50026,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v8i1_mask:
@@ -50065,7 +50065,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50082,7 +50082,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v8i1_mask_mem:
@@ -50121,7 +50121,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50139,7 +50139,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v8i1_mask_mem_b:
@@ -50179,7 +50179,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50200,7 +50200,7 @@ define zeroext i8 @test_masked_vcmpoeqps
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v8i1_mask:
@@ -50245,7 +50245,7 @@ define zeroext i8 @test_masked_vcmpoeqps
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50266,7 +50266,7 @@ define zeroext i8 @test_masked_vcmpoeqps
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v8i1_mask_mem:
@@ -50311,7 +50311,7 @@ define zeroext i8 @test_masked_vcmpoeqps
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50333,7 +50333,7 @@ define zeroext i8 @test_masked_vcmpoeqps
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v8i1_mask_mem_b:
@@ -50379,7 +50379,7 @@ define zeroext i8 @test_masked_vcmpoeqps
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50402,7 +50402,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v16i1_mask:
@@ -50440,7 +50440,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50457,7 +50457,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v16i1_mask_mem:
@@ -50495,7 +50495,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50513,7 +50513,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v16i1_mask_mem_b:
@@ -50552,7 +50552,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50573,7 +50573,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v16i1_mask:
@@ -50617,7 +50617,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50638,7 +50638,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v16i1_mask_mem:
@@ -50682,7 +50682,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -50704,7 +50704,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v16i1_mask_mem_b:
@@ -50749,7 +50749,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -51380,19 +51380,19 @@ define zeroext i16 @test_vcmpoeqps_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqps_v8i1_v16i1_mask:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -51409,19 +51409,19 @@ define zeroext i16 @test_vcmpoeqps_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqps_v8i1_v16i1_mask_mem:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovaps (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -51439,19 +51439,19 @@ define zeroext i16 @test_vcmpoeqps_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqps_v8i1_v16i1_mask_mem_b:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vbroadcastss (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -51471,20 +51471,20 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v16i1_mask:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -51504,20 +51504,20 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vcmpeqps (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v16i1_mask_mem:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovaps (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -51538,20 +51538,20 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vcmpeqps (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v16i1_mask_mem_b:
; NoVLX: # BB#0: # %entry
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vbroadcastss (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $8, %k0, %k0
; NoVLX-NEXT: kshiftrw $8, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -51586,8 +51586,8 @@ define zeroext i32 @test_vcmpoeqps_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
@@ -51659,7 +51659,7 @@ define zeroext i32 @test_vcmpoeqps_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovaps (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -51733,7 +51733,7 @@ define zeroext i32 @test_vcmpoeqps_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vbroadcastss (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -51809,8 +51809,8 @@ define zeroext i32 @test_masked_vcmpoeqp
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -51886,7 +51886,7 @@ define zeroext i32 @test_masked_vcmpoeqp
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovaps (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
@@ -51964,7 +51964,7 @@ define zeroext i32 @test_masked_vcmpoeqp
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vbroadcastss (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
@@ -52044,8 +52044,8 @@ define zeroext i64 @test_vcmpoeqps_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
@@ -52122,7 +52122,7 @@ define zeroext i64 @test_vcmpoeqps_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovaps (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -52201,7 +52201,7 @@ define zeroext i64 @test_vcmpoeqps_v8i1_
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vbroadcastss (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -52282,8 +52282,8 @@ define zeroext i64 @test_masked_vcmpoeqp
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1
@@ -52364,7 +52364,7 @@ define zeroext i64 @test_masked_vcmpoeqp
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vmovaps (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
@@ -52447,7 +52447,7 @@ define zeroext i64 @test_masked_vcmpoeqp
; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp
-; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NoVLX-NEXT: vbroadcastss (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
@@ -54281,7 +54281,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v8i1_mask:
@@ -54304,7 +54304,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54321,7 +54321,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v8i1_mask_mem:
@@ -54344,7 +54344,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54362,7 +54362,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v8i1_mask_mem_b:
@@ -54386,7 +54386,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54407,7 +54407,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v8i1_mask:
@@ -54435,7 +54435,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54456,7 +54456,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v8i1_mask_mem:
@@ -54484,7 +54484,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54506,7 +54506,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v8i1_mask_mem_b:
@@ -54535,7 +54535,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54558,7 +54558,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v16i1_mask:
@@ -54580,7 +54580,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54597,7 +54597,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v16i1_mask_mem:
@@ -54619,7 +54619,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54637,7 +54637,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v16i1_mask_mem_b:
@@ -54660,7 +54660,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54681,7 +54681,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v16i1_mask:
@@ -54708,7 +54708,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54729,7 +54729,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v16i1_mask_mem:
@@ -54756,7 +54756,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -54778,7 +54778,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: retq
;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v16i1_mask_mem_b:
@@ -54806,7 +54806,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -55431,7 +55431,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -55472,7 +55472,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -55489,7 +55489,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -55530,7 +55530,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -55548,7 +55548,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -55590,7 +55590,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -55611,7 +55611,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -55658,7 +55658,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -55679,7 +55679,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -55726,7 +55726,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -55748,7 +55748,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -55796,7 +55796,7 @@ define zeroext i8 @test_masked_vcmpoeqpd
; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -55819,7 +55819,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -55859,7 +55859,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -55876,7 +55876,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -55916,7 +55916,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -55934,7 +55934,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -55975,7 +55975,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -55996,7 +55996,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -56042,7 +56042,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -56063,7 +56063,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -56109,7 +56109,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -56131,7 +56131,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -56178,7 +56178,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -56833,7 +56833,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -56841,7 +56841,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -56858,7 +56858,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -56866,7 +56866,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -56884,7 +56884,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_
; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -56892,7 +56892,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_
; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -56912,7 +56912,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -56921,7 +56921,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -56941,7 +56941,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -56950,7 +56950,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -56971,7 +56971,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -56980,7 +56980,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -57004,7 +57004,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_
; VLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: movzbl %al, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -57013,7 +57013,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_
; NoVLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: movzbl %al, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -57031,7 +57031,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; VLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: movzbl %al, %eax
-; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; VLX-NEXT: vzeroupper
; VLX-NEXT: retq
;
@@ -57041,7 +57041,7 @@ define zeroext i16 @test_masked_vcmpoeqp
; NoVLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: movzbl %al, %eax
-; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-vec-test-testn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-vec-test-testn.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-vec-test-testn.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-vec-test-testn.ll Tue Nov 28 09:15:09 2017
@@ -8,14 +8,14 @@ define zeroext i8 @TEST_mm_test_epi64_ma
; X86_64: # BB#0: # %entry
; X86_64-NEXT: vptestmq %xmm0, %xmm1, %k0
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: retq
;
; I386-LABEL: TEST_mm_test_epi64_mask:
; I386: # BB#0: # %entry
; I386-NEXT: vptestmq %xmm0, %xmm1, %k0
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: retl
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -31,14 +31,14 @@ define zeroext i8 @TEST_mm_test_epi32_ma
; X86_64: # BB#0: # %entry
; X86_64-NEXT: vptestmd %xmm0, %xmm1, %k0
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: retq
;
; I386-LABEL: TEST_mm_test_epi32_mask:
; I386: # BB#0: # %entry
; I386-NEXT: vptestmd %xmm0, %xmm1, %k0
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: retl
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -55,7 +55,7 @@ define zeroext i8 @TEST_mm256_test_epi64
; X86_64: # BB#0: # %entry
; X86_64-NEXT: vptestmq %ymm0, %ymm1, %k0
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: vzeroupper
; X86_64-NEXT: retq
;
@@ -63,7 +63,7 @@ define zeroext i8 @TEST_mm256_test_epi64
; I386: # BB#0: # %entry
; I386-NEXT: vptestmq %ymm0, %ymm1, %k0
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: vzeroupper
; I386-NEXT: retl
entry:
@@ -80,7 +80,7 @@ define zeroext i8 @TEST_mm256_test_epi32
; X86_64: # BB#0: # %entry
; X86_64-NEXT: vptestmd %ymm0, %ymm1, %k0
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: vzeroupper
; X86_64-NEXT: retq
;
@@ -88,7 +88,7 @@ define zeroext i8 @TEST_mm256_test_epi32
; I386: # BB#0: # %entry
; I386-NEXT: vptestmd %ymm0, %ymm1, %k0
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: vzeroupper
; I386-NEXT: retl
entry:
@@ -106,7 +106,7 @@ define zeroext i8 @TEST_mm_mask_test_epi
; X86_64-NEXT: kmovw %edi, %k1
; X86_64-NEXT: vptestmq %xmm0, %xmm1, %k0 {%k1}
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: retq
;
; I386-LABEL: TEST_mm_mask_test_epi64_mask:
@@ -115,7 +115,7 @@ define zeroext i8 @TEST_mm_mask_test_epi
; I386-NEXT: kmovw %eax, %k1
; I386-NEXT: vptestmq %xmm0, %xmm1, %k0 {%k1}
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: retl
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -135,7 +135,7 @@ define zeroext i8 @TEST_mm_mask_test_epi
; X86_64-NEXT: kmovw %edi, %k1
; X86_64-NEXT: vptestmd %xmm0, %xmm1, %k0 {%k1}
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: retq
;
; I386-LABEL: TEST_mm_mask_test_epi32_mask:
@@ -144,7 +144,7 @@ define zeroext i8 @TEST_mm_mask_test_epi
; I386-NEXT: kmovw %eax, %k1
; I386-NEXT: vptestmd %xmm0, %xmm1, %k0 {%k1}
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: retl
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -166,7 +166,7 @@ define zeroext i8 @TEST_mm256_mask_test_
; X86_64-NEXT: kmovw %edi, %k1
; X86_64-NEXT: vptestmq %ymm0, %ymm1, %k0 {%k1}
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: vzeroupper
; X86_64-NEXT: retq
;
@@ -176,7 +176,7 @@ define zeroext i8 @TEST_mm256_mask_test_
; I386-NEXT: kmovw %eax, %k1
; I386-NEXT: vptestmq %ymm0, %ymm1, %k0 {%k1}
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: vzeroupper
; I386-NEXT: retl
entry:
@@ -197,7 +197,7 @@ define zeroext i8 @TEST_mm256_mask_test_
; X86_64-NEXT: kmovw %edi, %k1
; X86_64-NEXT: vptestmd %ymm0, %ymm1, %k0 {%k1}
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: vzeroupper
; X86_64-NEXT: retq
;
@@ -207,7 +207,7 @@ define zeroext i8 @TEST_mm256_mask_test_
; I386-NEXT: kmovw %eax, %k1
; I386-NEXT: vptestmd %ymm0, %ymm1, %k0 {%k1}
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: vzeroupper
; I386-NEXT: retl
entry:
@@ -226,14 +226,14 @@ define zeroext i8 @TEST_mm_testn_epi64_m
; X86_64: # BB#0: # %entry
; X86_64-NEXT: vptestnmq %xmm0, %xmm1, %k0
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: retq
;
; I386-LABEL: TEST_mm_testn_epi64_mask:
; I386: # BB#0: # %entry
; I386-NEXT: vptestnmq %xmm0, %xmm1, %k0
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: retl
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -249,14 +249,14 @@ define zeroext i8 @TEST_mm_testn_epi32_m
; X86_64: # BB#0: # %entry
; X86_64-NEXT: vptestnmd %xmm0, %xmm1, %k0
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: retq
;
; I386-LABEL: TEST_mm_testn_epi32_mask:
; I386: # BB#0: # %entry
; I386-NEXT: vptestnmd %xmm0, %xmm1, %k0
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: retl
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -273,7 +273,7 @@ define zeroext i8 @TEST_mm256_testn_epi6
; X86_64: # BB#0: # %entry
; X86_64-NEXT: vptestnmq %ymm0, %ymm1, %k0
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: vzeroupper
; X86_64-NEXT: retq
;
@@ -281,7 +281,7 @@ define zeroext i8 @TEST_mm256_testn_epi6
; I386: # BB#0: # %entry
; I386-NEXT: vptestnmq %ymm0, %ymm1, %k0
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: vzeroupper
; I386-NEXT: retl
entry:
@@ -298,7 +298,7 @@ define zeroext i8 @TEST_mm256_testn_epi3
; X86_64: # BB#0: # %entry
; X86_64-NEXT: vptestnmd %ymm0, %ymm1, %k0
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: vzeroupper
; X86_64-NEXT: retq
;
@@ -306,7 +306,7 @@ define zeroext i8 @TEST_mm256_testn_epi3
; I386: # BB#0: # %entry
; I386-NEXT: vptestnmd %ymm0, %ymm1, %k0
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: vzeroupper
; I386-NEXT: retl
entry:
@@ -324,7 +324,7 @@ define zeroext i8 @TEST_mm_mask_testn_ep
; X86_64-NEXT: kmovw %edi, %k1
; X86_64-NEXT: vptestnmq %xmm0, %xmm1, %k0 {%k1}
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: retq
;
; I386-LABEL: TEST_mm_mask_testn_epi64_mask:
@@ -333,7 +333,7 @@ define zeroext i8 @TEST_mm_mask_testn_ep
; I386-NEXT: kmovw %eax, %k1
; I386-NEXT: vptestnmq %xmm0, %xmm1, %k0 {%k1}
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: retl
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -353,7 +353,7 @@ define zeroext i8 @TEST_mm_mask_testn_ep
; X86_64-NEXT: kmovw %edi, %k1
; X86_64-NEXT: vptestnmd %xmm0, %xmm1, %k0 {%k1}
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: retq
;
; I386-LABEL: TEST_mm_mask_testn_epi32_mask:
@@ -362,7 +362,7 @@ define zeroext i8 @TEST_mm_mask_testn_ep
; I386-NEXT: kmovw %eax, %k1
; I386-NEXT: vptestnmd %xmm0, %xmm1, %k0 {%k1}
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: retl
entry:
%and.i.i = and <2 x i64> %__B, %__A
@@ -384,7 +384,7 @@ define zeroext i8 @TEST_mm256_mask_testn
; X86_64-NEXT: kmovw %edi, %k1
; X86_64-NEXT: vptestnmq %ymm0, %ymm1, %k0 {%k1}
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: vzeroupper
; X86_64-NEXT: retq
;
@@ -394,7 +394,7 @@ define zeroext i8 @TEST_mm256_mask_testn
; I386-NEXT: kmovw %eax, %k1
; I386-NEXT: vptestnmq %ymm0, %ymm1, %k0 {%k1}
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: vzeroupper
; I386-NEXT: retl
entry:
@@ -415,7 +415,7 @@ define zeroext i8 @TEST_mm256_mask_testn
; X86_64-NEXT: kmovw %edi, %k1
; X86_64-NEXT: vptestnmd %ymm0, %ymm1, %k0 {%k1}
; X86_64-NEXT: kmovw %k0, %eax
-; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X86_64-NEXT: vzeroupper
; X86_64-NEXT: retq
;
@@ -425,7 +425,7 @@ define zeroext i8 @TEST_mm256_mask_testn
; I386-NEXT: kmovw %eax, %k1
; I386-NEXT: vptestnmd %ymm0, %ymm1, %k0 {%k1}
; I386-NEXT: kmovw %k0, %eax
-; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; I386-NEXT: vzeroupper
; I386-NEXT: retl
entry:
Modified: llvm/trunk/test/CodeGen/X86/base-pointer-and-cmpxchg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/base-pointer-and-cmpxchg.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/base-pointer-and-cmpxchg.ll (original)
+++ llvm/trunk/test/CodeGen/X86/base-pointer-and-cmpxchg.ll Tue Nov 28 09:15:09 2017
@@ -19,23 +19,23 @@
; USE_BASE_64: movq %rsp, %rbx
; USE_BASE_32: movl %esp, %ebx
;
-; Make sure the base pointer is saved before the RBX argument for
+; Make sure the base pointer is saved before the rbx argument for
; cmpxchg16b is set.
;
-; Because of how the test is written, we spill SAVE_RBX.
+; Because of how the test is written, we spill SAVE_rbx.
; However, it would have been perfectly fine to just keep it in register.
-; USE_BASE: movq %rbx, [[SAVE_RBX_SLOT:[0-9]*\(%[er]bx\)]]
+; USE_BASE: movq %rbx, [[SAVE_rbx_SLOT:[0-9]*\(%[er]bx\)]]
;
-; SAVE_RBX must be in register before we clobber rbx.
+; SAVE_rbx must be in register before we clobber rbx.
; It is fine to use any register but rbx and the ones defined and use
; by cmpxchg. Since such regex would be complicated to write, just stick
; to the numbered registers. The bottom line is: if this test case fails
; because of that regex, this is likely just the regex being too conservative.
-; USE_BASE: movq [[SAVE_RBX_SLOT]], [[SAVE_RBX:%r[0-9]+]]
+; USE_BASE: movq [[SAVE_rbx_SLOT]], [[SAVE_rbx:%r[0-9]+]]
;
; USE_BASE: movq {{[^ ]+}}, %rbx
; USE_BASE-NEXT: cmpxchg16b
-; USE_BASE-NEXT: movq [[SAVE_RBX]], %rbx
+; USE_BASE-NEXT: movq [[SAVE_rbx]], %rbx
;
; DONT_USE_BASE-NOT: movq %rsp, %rbx
; DONT_USE_BASE-NOT: movl %esp, %ebx
Modified: llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-128.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-128.ll Tue Nov 28 09:15:09 2017
@@ -14,7 +14,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16>
; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2
; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm2
; SSE2-SSSE3-NEXT: pmovmskb %xmm2, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v8i16:
@@ -24,7 +24,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16>
; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v8i16:
@@ -38,7 +38,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16>
; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -47,7 +47,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16>
; AVX512BW-NEXT: vpcmpgtw %xmm1, %xmm0, %k1
; AVX512BW-NEXT: vpcmpgtw %xmm3, %xmm2, %k0 {%k1}
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: retq
%x0 = icmp sgt <8 x i16> %a, %b
%x1 = icmp sgt <8 x i16> %c, %d
@@ -63,7 +63,7 @@ define i4 @v4i32(<4 x i32> %a, <4 x i32>
; SSE2-SSSE3-NEXT: pcmpgtd %xmm3, %xmm2
; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2
; SSE2-SSSE3-NEXT: movmskps %xmm2, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v4i32:
@@ -72,7 +72,7 @@ define i4 @v4i32(<4 x i32> %a, <4 x i32>
; AVX12-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm1
; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vmovmskps %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v4i32:
@@ -106,7 +106,7 @@ define i4 @v4f32(<4 x float> %a, <4 x fl
; SSE2-SSSE3-NEXT: cmpltps %xmm2, %xmm3
; SSE2-SSSE3-NEXT: andps %xmm1, %xmm3
; SSE2-SSSE3-NEXT: movmskps %xmm3, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v4f32:
@@ -115,7 +115,7 @@ define i4 @v4f32(<4 x float> %a, <4 x fl
; AVX12-NEXT: vcmpltps %xmm2, %xmm3, %xmm1
; AVX12-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vmovmskps %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v4f32:
@@ -149,7 +149,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8
; SSE2-SSSE3-NEXT: pcmpgtb %xmm3, %xmm2
; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2
; SSE2-SSSE3-NEXT: pmovmskb %xmm2, %eax
-; SSE2-SSSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v16i8:
@@ -158,7 +158,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8
; AVX12-NEXT: vpcmpgtb %xmm3, %xmm2, %xmm1
; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
-; AVX12-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v16i8:
@@ -172,7 +172,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8
; AVX512F-NEXT: vpslld $31, %zmm0, %zmm0
; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -181,7 +181,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8
; AVX512BW-NEXT: vpcmpgtb %xmm1, %xmm0, %k1
; AVX512BW-NEXT: vpcmpgtb %xmm3, %xmm2, %k0 {%k1}
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: retq
%x0 = icmp sgt <16 x i8> %a, %b
%x1 = icmp sgt <16 x i8> %c, %d
@@ -244,7 +244,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b
; SSE2-SSSE3-NEXT: por %xmm2, %xmm0
; SSE2-SSSE3-NEXT: pand %xmm1, %xmm0
; SSE2-SSSE3-NEXT: movmskpd %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v2i8:
@@ -273,7 +273,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vmovmskpd %xmm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: retq
;
; AVX2-LABEL: v2i8:
@@ -302,7 +302,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vmovmskpd %xmm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: retq
;
; AVX512F-LABEL: v2i8:
@@ -399,7 +399,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16>
; SSE2-SSSE3-NEXT: por %xmm2, %xmm0
; SSE2-SSSE3-NEXT: pand %xmm1, %xmm0
; SSE2-SSSE3-NEXT: movmskpd %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v2i16:
@@ -428,7 +428,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16>
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vmovmskpd %xmm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: retq
;
; AVX2-LABEL: v2i16:
@@ -457,7 +457,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16>
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vmovmskpd %xmm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: retq
;
; AVX512F-LABEL: v2i16:
@@ -546,7 +546,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32>
; SSE2-SSSE3-NEXT: por %xmm2, %xmm0
; SSE2-SSSE3-NEXT: pand %xmm3, %xmm0
; SSE2-SSSE3-NEXT: movmskpd %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v2i32:
@@ -571,7 +571,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32>
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vmovmskpd %xmm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: retq
;
; AVX2-LABEL: v2i32:
@@ -596,7 +596,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32>
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vmovmskpd %xmm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: retq
;
; AVX512F-LABEL: v2i32:
@@ -665,7 +665,7 @@ define i2 @v2i64(<2 x i64> %a, <2 x i64>
; SSE2-SSSE3-NEXT: por %xmm2, %xmm0
; SSE2-SSSE3-NEXT: pand %xmm1, %xmm0
; SSE2-SSSE3-NEXT: movmskpd %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v2i64:
@@ -674,7 +674,7 @@ define i2 @v2i64(<2 x i64> %a, <2 x i64>
; AVX12-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm1
; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vmovmskpd %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v2i64:
@@ -708,7 +708,7 @@ define i2 @v2f64(<2 x double> %a, <2 x d
; SSE2-SSSE3-NEXT: cmpltpd %xmm2, %xmm3
; SSE2-SSSE3-NEXT: andpd %xmm1, %xmm3
; SSE2-SSSE3-NEXT: movmskpd %xmm3, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v2f64:
@@ -717,7 +717,7 @@ define i2 @v2f64(<2 x double> %a, <2 x d
; AVX12-NEXT: vcmpltpd %xmm2, %xmm3, %xmm1
; AVX12-NEXT: vandpd %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vmovmskpd %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v2f64:
@@ -759,7 +759,7 @@ define i4 @v4i8(<4 x i8> %a, <4 x i8> %b
; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-SSSE3-NEXT: pand %xmm2, %xmm0
; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v4i8:
@@ -776,7 +776,7 @@ define i4 @v4i8(<4 x i8> %a, <4 x i8> %b
; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX12-NEXT: vmovmskps %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v4i8:
@@ -834,7 +834,7 @@ define i4 @v4i16(<4 x i16> %a, <4 x i16>
; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-SSSE3-NEXT: pand %xmm2, %xmm0
; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v4i16:
@@ -851,7 +851,7 @@ define i4 @v4i16(<4 x i16> %a, <4 x i16>
; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX12-NEXT: vmovmskps %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v4i16:
@@ -910,7 +910,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b
; SSE2-SSSE3-NEXT: pand %xmm2, %xmm0
; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0
; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v8i8:
@@ -928,7 +928,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b
; AVX12-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v8i8:
@@ -950,7 +950,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b
; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -967,7 +967,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b
; AVX512BW-NEXT: vpcmpgtw %xmm1, %xmm0, %k1
; AVX512BW-NEXT: vpcmpgtw %xmm3, %xmm2, %k0 {%k1}
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: retq
%x0 = icmp sgt <8 x i8> %a, %b
%x1 = icmp sgt <8 x i8> %c, %d
Modified: llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll Tue Nov 28 09:15:09 2017
@@ -54,7 +54,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64>
; SSE2-SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,2]
; SSE2-SSSE3-NEXT: andps %xmm0, %xmm2
; SSE2-SSSE3-NEXT: movmskps %xmm2, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v4i64:
@@ -71,7 +71,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64>
; AVX1-NEXT: vpackssdw %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmovmskps %xmm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -85,7 +85,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64>
; AVX2-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vmovmskps %xmm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -126,7 +126,7 @@ define i4 @v4f64(<4 x double> %a, <4 x d
; SSE2-SSSE3-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm7[0,2]
; SSE2-SSSE3-NEXT: andps %xmm2, %xmm6
; SSE2-SSSE3-NEXT: movmskps %xmm6, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v4f64:
@@ -139,7 +139,7 @@ define i4 @v4f64(<4 x double> %a, <4 x d
; AVX12-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vmovmskps %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: vzeroupper
; AVX12-NEXT: retq
;
@@ -180,7 +180,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x
; SSE2-SSSE3-NEXT: packsswb %xmm5, %xmm4
; SSE2-SSSE3-NEXT: pand %xmm0, %xmm4
; SSE2-SSSE3-NEXT: pmovmskb %xmm4, %eax
-; SSE2-SSSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v16i16:
@@ -197,7 +197,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x
; AVX1-NEXT: vpacksswb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax
-; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -211,7 +211,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x
; AVX2-NEXT: vpacksswb %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
-; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -226,7 +226,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x
; AVX512F-NEXT: vpslld $31, %zmm0, %zmm0
; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -235,7 +235,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x
; AVX512BW-NEXT: vpcmpgtw %ymm1, %ymm0, %k1
; AVX512BW-NEXT: vpcmpgtw %ymm3, %ymm2, %k0 {%k1}
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x0 = icmp sgt <16 x i16> %a, %b
@@ -257,7 +257,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; SSE2-SSSE3-NEXT: pand %xmm0, %xmm4
; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm4
; SSE2-SSSE3-NEXT: pmovmskb %xmm4, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v8i32:
@@ -275,7 +275,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -290,7 +290,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -299,7 +299,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; AVX512F-NEXT: vpcmpgtd %ymm1, %ymm0, %k1
; AVX512F-NEXT: vpcmpgtd %ymm3, %ymm2, %k0 {%k1}
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -308,7 +308,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; AVX512BW-NEXT: vpcmpgtd %ymm1, %ymm0, %k1
; AVX512BW-NEXT: vpcmpgtd %ymm3, %ymm2, %k0 {%k1}
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x0 = icmp sgt <8 x i32> %a, %b
@@ -330,7 +330,7 @@ define i8 @v8f32(<8 x float> %a, <8 x fl
; SSE2-SSSE3-NEXT: pand %xmm2, %xmm6
; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm6
; SSE2-SSSE3-NEXT: pmovmskb %xmm6, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v8f32:
@@ -344,7 +344,7 @@ define i8 @v8f32(<8 x float> %a, <8 x fl
; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: vzeroupper
; AVX12-NEXT: retq
;
@@ -353,7 +353,7 @@ define i8 @v8f32(<8 x float> %a, <8 x fl
; AVX512F-NEXT: vcmpltps %ymm0, %ymm1, %k1
; AVX512F-NEXT: vcmpltps %ymm2, %ymm3, %k0 {%k1}
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -362,7 +362,7 @@ define i8 @v8f32(<8 x float> %a, <8 x fl
; AVX512BW-NEXT: vcmpltps %ymm0, %ymm1, %k1
; AVX512BW-NEXT: vcmpltps %ymm2, %ymm3, %k0 {%k1}
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x0 = fcmp ogt <8 x float> %a, %b
Modified: llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll Tue Nov 28 09:15:09 2017
@@ -41,7 +41,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; SSE-NEXT: psraw $15, %xmm8
; SSE-NEXT: packsswb %xmm0, %xmm8
; SSE-NEXT: pmovmskb %xmm8, %eax
-; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX1-LABEL: v8i64:
@@ -76,7 +76,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -104,7 +104,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -113,7 +113,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; AVX512F-NEXT: vpcmpgtq %zmm1, %zmm0, %k1
; AVX512F-NEXT: vpcmpgtq %zmm3, %zmm2, %k0 {%k1}
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -122,7 +122,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; AVX512BW-NEXT: vpcmpgtq %zmm1, %zmm0, %k1
; AVX512BW-NEXT: vpcmpgtq %zmm3, %zmm2, %k0 {%k1}
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x0 = icmp sgt <8 x i64> %a, %b
@@ -168,7 +168,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; SSE-NEXT: psraw $15, %xmm8
; SSE-NEXT: packsswb %xmm0, %xmm8
; SSE-NEXT: pmovmskb %xmm8, %eax
-; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX12-LABEL: v8f64:
@@ -195,7 +195,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: vzeroupper
; AVX12-NEXT: retq
;
@@ -204,7 +204,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; AVX512F-NEXT: vcmpltpd %zmm0, %zmm1, %k1
; AVX512F-NEXT: vcmpltpd %zmm2, %zmm3, %k0 {%k1}
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -213,7 +213,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; AVX512BW-NEXT: vcmpltpd %zmm0, %zmm1, %k1
; AVX512BW-NEXT: vcmpltpd %zmm2, %zmm3, %k0 {%k1}
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x0 = fcmp ogt <8 x double> %a, %b
@@ -634,7 +634,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; SSE-NEXT: packsswb %xmm10, %xmm8
; SSE-NEXT: pand %xmm0, %xmm8
; SSE-NEXT: pmovmskb %xmm8, %eax
-; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX1-LABEL: v16i32:
@@ -663,7 +663,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; AVX1-NEXT: vpacksswb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax
-; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -685,7 +685,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; AVX2-NEXT: vpacksswb %xmm1, %xmm2, %xmm1
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
-; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -694,7 +694,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; AVX512F-NEXT: vpcmpgtd %zmm1, %zmm0, %k1
; AVX512F-NEXT: vpcmpgtd %zmm3, %zmm2, %k0 {%k1}
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -703,7 +703,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; AVX512BW-NEXT: vpcmpgtd %zmm1, %zmm0, %k1
; AVX512BW-NEXT: vpcmpgtd %zmm3, %zmm2, %k0 {%k1}
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x0 = icmp sgt <16 x i32> %a, %b
@@ -736,7 +736,7 @@ define i16 @v16f32(<16 x float> %a, <16
; SSE-NEXT: packsswb %xmm10, %xmm8
; SSE-NEXT: pand %xmm4, %xmm8
; SSE-NEXT: pmovmskb %xmm8, %eax
-; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX12-LABEL: v16f32:
@@ -757,7 +757,7 @@ define i16 @v16f32(<16 x float> %a, <16
; AVX12-NEXT: vpacksswb %xmm1, %xmm2, %xmm1
; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
-; AVX12-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX12-NEXT: vzeroupper
; AVX12-NEXT: retq
;
@@ -766,7 +766,7 @@ define i16 @v16f32(<16 x float> %a, <16
; AVX512F-NEXT: vcmpltps %zmm0, %zmm1, %k1
; AVX512F-NEXT: vcmpltps %zmm2, %zmm3, %k0 {%k1}
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -775,7 +775,7 @@ define i16 @v16f32(<16 x float> %a, <16
; AVX512BW-NEXT: vcmpltps %zmm0, %zmm1, %k1
; AVX512BW-NEXT: vcmpltps %zmm2, %zmm3, %k0 {%k1}
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x0 = fcmp ogt <16 x float> %a, %b
Modified: llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll Tue Nov 28 09:15:09 2017
@@ -12,7 +12,7 @@
define <2 x i64> @ext_i2_2i64(i2 %a0) {
; SSE2-SSSE3-LABEL: ext_i2_2i64:
; SSE2-SSSE3: # BB#0:
-; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SSE2-SSSE3-NEXT: movq %rdi, %xmm0
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2]
@@ -24,7 +24,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) {
;
; AVX1-LABEL: ext_i2_2i64:
; AVX1: # BB#0:
-; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX1-NEXT: vmovq %rdi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2]
@@ -34,7 +34,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) {
;
; AVX2-LABEL: ext_i2_2i64:
; AVX2: # BB#0:
-; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX2-NEXT: vmovq %rdi, %xmm0
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2]
@@ -49,7 +49,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) {
; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512-NEXT: kmovd %eax, %k1
; AVX512-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%1 = bitcast i2 %a0 to <2 x i1>
@@ -93,7 +93,7 @@ define <4 x i32> @ext_i4_4i32(i4 %a0) {
; AVX512-NEXT: kmovd %eax, %k1
; AVX512-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
-; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%1 = bitcast i4 %a0 to <4 x i1>
@@ -197,7 +197,7 @@ define <16 x i8> @ext_i16_16i8(i16 %a0)
define <4 x i64> @ext_i4_4i64(i4 %a0) {
; SSE2-SSSE3-LABEL: ext_i4_4i64:
; SSE2-SSSE3: # BB#0:
-; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SSE2-SSSE3-NEXT: movq %rdi, %xmm0
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,0,1]
; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2]
@@ -215,7 +215,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
;
; AVX1-LABEL: ext_i4_4i64:
; AVX1: # BB#0:
-; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX1-NEXT: vmovq %rdi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
@@ -232,7 +232,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
;
; AVX2-LABEL: ext_i4_4i64:
; AVX2: # BB#0:
-; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX2-NEXT: vmovq %rdi, %xmm0
; AVX2-NEXT: vpbroadcastq %xmm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1,2,4,8]
@@ -247,7 +247,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512-NEXT: kmovd %eax, %k1
; AVX512-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512-NEXT: retq
%1 = bitcast i4 %a0 to <4 x i1>
%2 = sext <4 x i1> %1 to <4 x i64>
@@ -422,7 +422,7 @@ define <32 x i8> @ext_i32_32i8(i32 %a0)
define <8 x i64> @ext_i8_8i64(i8 %a0) {
; SSE2-SSSE3-LABEL: ext_i8_8i64:
; SSE2-SSSE3: # BB#0:
-; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SSE2-SSSE3-NEXT: movq %rdi, %xmm0
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,1,0,1]
; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2]
@@ -452,7 +452,7 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) {
;
; AVX1-LABEL: ext_i8_8i64:
; AVX1: # BB#0:
-; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX1-NEXT: vmovq %rdi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
@@ -476,7 +476,7 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) {
;
; AVX2-LABEL: ext_i8_8i64:
; AVX2: # BB#0:
-; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX2-NEXT: vmovq %rdi, %xmm0
; AVX2-NEXT: vpbroadcastq %xmm0, %ymm1
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [1,2,4,8]
Modified: llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll Tue Nov 28 09:15:09 2017
@@ -13,7 +13,7 @@
define <2 x i64> @ext_i2_2i64(i2 %a0) {
; SSE2-SSSE3-LABEL: ext_i2_2i64:
; SSE2-SSSE3: # BB#0:
-; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SSE2-SSSE3-NEXT: movq %rdi, %xmm0
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2]
@@ -26,7 +26,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) {
;
; AVX1-LABEL: ext_i2_2i64:
; AVX1: # BB#0:
-; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX1-NEXT: vmovq %rdi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2]
@@ -37,7 +37,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) {
;
; AVX2-LABEL: ext_i2_2i64:
; AVX2: # BB#0:
-; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX2-NEXT: vmovq %rdi, %xmm0
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2]
@@ -53,7 +53,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) {
; AVX512F-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
-; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -64,7 +64,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) {
; AVX512VLBW-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512VLBW-NEXT: kmovd %eax, %k1
; AVX512VLBW-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
-; AVX512VLBW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512VLBW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512VLBW-NEXT: vzeroupper
; AVX512VLBW-NEXT: retq
%1 = bitcast i2 %a0 to <2 x i1>
@@ -111,7 +111,7 @@ define <4 x i32> @ext_i4_4i32(i4 %a0) {
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; AVX512F-NEXT: vpmovqd %zmm0, %ymm0
-; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -122,7 +122,7 @@ define <4 x i32> @ext_i4_4i32(i4 %a0) {
; AVX512VLBW-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512VLBW-NEXT: kmovd %eax, %k1
; AVX512VLBW-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z}
-; AVX512VLBW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX512VLBW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512VLBW-NEXT: vzeroupper
; AVX512VLBW-NEXT: retq
%1 = bitcast i4 %a0 to <4 x i1>
@@ -253,7 +253,7 @@ define <16 x i8> @ext_i16_16i8(i16 %a0)
define <4 x i64> @ext_i4_4i64(i4 %a0) {
; SSE2-SSSE3-LABEL: ext_i4_4i64:
; SSE2-SSSE3: # BB#0:
-; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SSE2-SSSE3-NEXT: movq %rdi, %xmm0
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,0,1]
; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2]
@@ -273,7 +273,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
;
; AVX1-LABEL: ext_i4_4i64:
; AVX1: # BB#0:
-; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX1-NEXT: vmovq %rdi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
@@ -292,7 +292,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
;
; AVX2-LABEL: ext_i4_4i64:
; AVX2: # BB#0:
-; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX2-NEXT: vmovq %rdi, %xmm0
; AVX2-NEXT: vpbroadcastq %xmm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1,2,4,8]
@@ -308,7 +308,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
; AVX512F-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
-; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512F-NEXT: retq
;
; AVX512VLBW-LABEL: ext_i4_4i64:
@@ -318,7 +318,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
; AVX512VLBW-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512VLBW-NEXT: kmovd %eax, %k1
; AVX512VLBW-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
-; AVX512VLBW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; AVX512VLBW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512VLBW-NEXT: retq
%1 = bitcast i4 %a0 to <4 x i1>
%2 = zext <4 x i1> %1 to <4 x i64>
@@ -550,7 +550,7 @@ define <32 x i8> @ext_i32_32i8(i32 %a0)
define <8 x i64> @ext_i8_8i64(i8 %a0) {
; SSE2-SSSE3-LABEL: ext_i8_8i64:
; SSE2-SSSE3: # BB#0:
-; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SSE2-SSSE3-NEXT: movq %rdi, %xmm0
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,1,0,1]
; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2]
@@ -584,7 +584,7 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) {
;
; AVX1-LABEL: ext_i8_8i64:
; AVX1: # BB#0:
-; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX1-NEXT: vmovq %rdi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
@@ -612,7 +612,7 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) {
;
; AVX2-LABEL: ext_i8_8i64:
; AVX2: # BB#0:
-; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX2-NEXT: vmovq %rdi, %xmm0
; AVX2-NEXT: vpbroadcastq %xmm0, %ymm1
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [1,2,4,8]
Modified: llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool.ll Tue Nov 28 09:15:09 2017
@@ -8,7 +8,7 @@
define <2 x i1> @bitcast_i2_2i1(i2 zeroext %a0) {
; SSE2-SSSE3-LABEL: bitcast_i2_2i1:
; SSE2-SSSE3: # BB#0:
-; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SSE2-SSSE3-NEXT: movq %rdi, %xmm0
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2]
@@ -21,7 +21,7 @@ define <2 x i1> @bitcast_i2_2i1(i2 zeroe
;
; AVX1-LABEL: bitcast_i2_2i1:
; AVX1: # BB#0:
-; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX1-NEXT: vmovq %rdi, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2]
@@ -32,7 +32,7 @@ define <2 x i1> @bitcast_i2_2i1(i2 zeroe
;
; AVX2-LABEL: bitcast_i2_2i1:
; AVX2: # BB#0:
-; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; AVX2-NEXT: vmovq %rdi, %xmm0
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2]
@@ -47,7 +47,7 @@ define <2 x i1> @bitcast_i2_2i1(i2 zeroe
; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512-NEXT: kmovd %eax, %k1
; AVX512-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%1 = bitcast i2 %a0 to <2 x i1>
@@ -92,7 +92,7 @@ define <4 x i1> @bitcast_i4_4i1(i4 zeroe
; AVX512-NEXT: kmovd %eax, %k1
; AVX512-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX512-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
-; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%1 = bitcast i4 %a0 to <4 x i1>
Modified: llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector.ll Tue Nov 28 09:15:09 2017
@@ -10,7 +10,7 @@ define i1 @foo(i64 %a) {
; X86-NEXT: flds {{[0-9]+}}(%esp)
; X86-NEXT: fucompp
; X86-NEXT: fnstsw %ax
-; X86-NEXT: # kill: %AH<def> %AH<kill> %AX<kill>
+; X86-NEXT: # kill: %ah<def> %ah<kill> %ax<kill>
; X86-NEXT: sahf
; X86-NEXT: setp %al
; X86-NEXT: retl
Modified: llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll Tue Nov 28 09:15:09 2017
@@ -12,7 +12,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16>
; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0
; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0
; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v8i16:
@@ -20,7 +20,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16>
; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v8i16:
@@ -30,7 +30,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16>
; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -38,7 +38,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16>
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vpcmpgtw %xmm1, %xmm0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: retq
%x = icmp sgt <8 x i16> %a, %b
%res = bitcast <8 x i1> %x to i8
@@ -50,14 +50,14 @@ define i4 @v4i32(<4 x i32> %a, <4 x i32>
; SSE2-SSSE3: # BB#0:
; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v4i32:
; AVX12: # BB#0:
; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vmovmskps %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v4i32:
@@ -85,14 +85,14 @@ define i4 @v4f32(<4 x float> %a, <4 x fl
; SSE2-SSSE3: # BB#0:
; SSE2-SSSE3-NEXT: cmpltps %xmm0, %xmm1
; SSE2-SSSE3-NEXT: movmskps %xmm1, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v4f32:
; AVX12: # BB#0:
; AVX12-NEXT: vcmpltps %xmm0, %xmm1, %xmm0
; AVX12-NEXT: vmovmskps %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v4f32:
@@ -120,14 +120,14 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8
; SSE2-SSSE3: # BB#0:
; SSE2-SSSE3-NEXT: pcmpgtb %xmm1, %xmm0
; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v16i8:
; AVX12: # BB#0:
; AVX12-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
-; AVX12-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v16i8:
@@ -137,7 +137,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8
; AVX512F-NEXT: vpslld $31, %zmm0, %zmm0
; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -145,7 +145,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vpcmpgtb %xmm1, %xmm0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: retq
%x = icmp sgt <16 x i8> %a, %b
%res = bitcast <16 x i1> %x to i16
@@ -181,7 +181,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE2-SSSE3-NEXT: por %xmm0, %xmm1
; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v2i8:
@@ -198,7 +198,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmovmskpd %xmm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: retq
;
; AVX2-LABEL: v2i8:
@@ -215,7 +215,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vmovmskpd %xmm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: retq
;
; AVX512F-LABEL: v2i8:
@@ -275,7 +275,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16>
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE2-SSSE3-NEXT: por %xmm0, %xmm1
; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v2i16:
@@ -292,7 +292,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16>
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmovmskpd %xmm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: retq
;
; AVX2-LABEL: v2i16:
@@ -309,7 +309,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16>
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vmovmskpd %xmm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: retq
;
; AVX512F-LABEL: v2i16:
@@ -365,7 +365,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32>
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-SSSE3-NEXT: por %xmm0, %xmm1
; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v2i32:
@@ -380,7 +380,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32>
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmovmskpd %xmm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: retq
;
; AVX2-LABEL: v2i32:
@@ -395,7 +395,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32>
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vmovmskpd %xmm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: retq
;
; AVX512F-LABEL: v2i32:
@@ -441,14 +441,14 @@ define i2 @v2i64(<2 x i64> %a, <2 x i64>
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE2-SSSE3-NEXT: por %xmm0, %xmm1
; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v2i64:
; AVX12: # BB#0:
; AVX12-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vmovmskpd %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v2i64:
@@ -476,14 +476,14 @@ define i2 @v2f64(<2 x double> %a, <2 x d
; SSE2-SSSE3: # BB#0:
; SSE2-SSSE3-NEXT: cmpltpd %xmm0, %xmm1
; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v2f64:
; AVX12: # BB#0:
; AVX12-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0
; AVX12-NEXT: vmovmskpd %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v2f64:
@@ -515,7 +515,7 @@ define i4 @v4i8(<4 x i8> %a, <4 x i8> %b
; SSE2-SSSE3-NEXT: psrad $24, %xmm0
; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v4i8:
@@ -526,7 +526,7 @@ define i4 @v4i8(<4 x i8> %a, <4 x i8> %b
; AVX12-NEXT: vpsrad $24, %xmm0, %xmm0
; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vmovmskps %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v4i8:
@@ -566,7 +566,7 @@ define i4 @v4i16(<4 x i16> %a, <4 x i16>
; SSE2-SSSE3-NEXT: psrad $16, %xmm0
; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v4i16:
@@ -577,7 +577,7 @@ define i4 @v4i16(<4 x i16> %a, <4 x i16>
; AVX12-NEXT: vpsrad $16, %xmm0, %xmm0
; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vmovmskps %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v4i16:
@@ -618,7 +618,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b
; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0
; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0
; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v8i8:
@@ -630,7 +630,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b
; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: retq
;
; AVX512F-LABEL: v8i8:
@@ -644,7 +644,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b
; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -656,7 +656,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b
; AVX512BW-NEXT: vpsraw $8, %xmm0, %xmm0
; AVX512BW-NEXT: vpcmpgtw %xmm1, %xmm0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: retq
%x = icmp sgt <8 x i8> %a, %b
%res = bitcast <8 x i1> %x to i8
Modified: llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll Tue Nov 28 09:15:09 2017
@@ -13,7 +13,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x
; SSE2-SSSE3-NEXT: pcmpgtw %xmm2, %xmm0
; SSE2-SSSE3-NEXT: packsswb %xmm1, %xmm0
; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v16i16:
@@ -24,7 +24,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x
; AVX1-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax
-; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -34,7 +34,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
-; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -45,7 +45,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x
; AVX512F-NEXT: vpslld $31, %zmm0, %zmm0
; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -53,7 +53,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vpcmpgtw %ymm1, %ymm0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x = icmp sgt <16 x i16> %a, %b
@@ -69,7 +69,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; SSE2-SSSE3-NEXT: packssdw %xmm1, %xmm0
; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0
; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v8i32:
@@ -80,7 +80,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; AVX1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: vmovmskps %ymm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -88,7 +88,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; AVX2: # BB#0:
; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vmovmskps %ymm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -96,7 +96,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; AVX512F: # BB#0:
; AVX512F-NEXT: vpcmpgtd %ymm1, %ymm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -104,7 +104,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vpcmpgtd %ymm1, %ymm0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x = icmp sgt <8 x i32> %a, %b
@@ -120,14 +120,14 @@ define i8 @v8f32(<8 x float> %a, <8 x fl
; SSE2-SSSE3-NEXT: packssdw %xmm3, %xmm2
; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm2
; SSE2-SSSE3-NEXT: pmovmskb %xmm2, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v8f32:
; AVX12: # BB#0:
; AVX12-NEXT: vcmpltps %ymm0, %ymm1, %ymm0
; AVX12-NEXT: vmovmskps %ymm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: vzeroupper
; AVX12-NEXT: retq
;
@@ -135,7 +135,7 @@ define i8 @v8f32(<8 x float> %a, <8 x fl
; AVX512F: # BB#0:
; AVX512F-NEXT: vcmpltps %ymm0, %ymm1, %k0
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -143,7 +143,7 @@ define i8 @v8f32(<8 x float> %a, <8 x fl
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vcmpltps %ymm0, %ymm1, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x = fcmp ogt <8 x float> %a, %b
@@ -244,7 +244,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64>
; SSE2-SSSE3-NEXT: por %xmm0, %xmm1
; SSE2-SSSE3-NEXT: packssdw %xmm3, %xmm1
; SSE2-SSSE3-NEXT: movmskps %xmm1, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v4i64:
@@ -255,7 +255,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64>
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: vmovmskpd %ymm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -263,7 +263,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64>
; AVX2: # BB#0:
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vmovmskpd %ymm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -296,14 +296,14 @@ define i4 @v4f64(<4 x double> %a, <4 x d
; SSE2-SSSE3-NEXT: cmpltpd %xmm0, %xmm2
; SSE2-SSSE3-NEXT: packssdw %xmm3, %xmm2
; SSE2-SSSE3-NEXT: movmskps %xmm2, %eax
-; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v4f64:
; AVX12: # BB#0:
; AVX12-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
; AVX12-NEXT: vmovmskpd %ymm0, %eax
-; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX12-NEXT: vzeroupper
; AVX12-NEXT: retq
;
Modified: llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll Tue Nov 28 09:15:09 2017
@@ -228,7 +228,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: packsswb %xmm2, %xmm0
; SSE-NEXT: pmovmskb %xmm0, %eax
-; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX1-LABEL: v16i32:
@@ -245,7 +245,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; AVX1-NEXT: vpackssdw %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax
-; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -258,7 +258,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
-; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -266,7 +266,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; AVX512F: # BB#0:
; AVX512F-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -274,7 +274,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x = icmp sgt <16 x i32> %a, %b
@@ -293,7 +293,7 @@ define i16 @v16f32(<16 x float> %a, <16
; SSE-NEXT: packssdw %xmm5, %xmm4
; SSE-NEXT: packsswb %xmm6, %xmm4
; SSE-NEXT: pmovmskb %xmm4, %eax
-; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX1-LABEL: v16f32:
@@ -306,7 +306,7 @@ define i16 @v16f32(<16 x float> %a, <16
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax
-; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -319,7 +319,7 @@ define i16 @v16f32(<16 x float> %a, <16
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
-; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -327,7 +327,7 @@ define i16 @v16f32(<16 x float> %a, <16
; AVX512F: # BB#0:
; AVX512F-NEXT: vcmpltps %zmm0, %zmm1, %k0
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -335,7 +335,7 @@ define i16 @v16f32(<16 x float> %a, <16
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vcmpltps %zmm0, %zmm1, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x = fcmp ogt <16 x float> %a, %b
@@ -1047,7 +1047,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; SSE-NEXT: packssdw %xmm2, %xmm0
; SSE-NEXT: packsswb %xmm0, %xmm0
; SSE-NEXT: pmovmskb %xmm0, %eax
-; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX1-LABEL: v8i64:
@@ -1064,7 +1064,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; AVX1-NEXT: vpackssdw %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vmovmskps %ymm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -1075,7 +1075,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; AVX2-NEXT: vpackssdw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-NEXT: vmovmskps %ymm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -1083,7 +1083,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; AVX512F: # BB#0:
; AVX512F-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -1091,7 +1091,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x = icmp sgt <8 x i64> %a, %b
@@ -1111,7 +1111,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; SSE-NEXT: packssdw %xmm6, %xmm4
; SSE-NEXT: packsswb %xmm0, %xmm4
; SSE-NEXT: pmovmskb %xmm4, %eax
-; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX1-LABEL: v8f64:
@@ -1124,7 +1124,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vmovmskps %ymm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -1135,7 +1135,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; AVX2-NEXT: vpackssdw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-NEXT: vmovmskps %ymm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -1143,7 +1143,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; AVX512F: # BB#0:
; AVX512F-NEXT: vcmpltpd %zmm0, %zmm1, %k0
; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -1151,7 +1151,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vcmpltpd %zmm0, %zmm1, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%x = fcmp ogt <8 x double> %a, %b
Modified: llvm/trunk/test/CodeGen/X86/bitreverse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitreverse.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitreverse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitreverse.ll Tue Nov 28 09:15:09 2017
@@ -46,8 +46,8 @@ define <2 x i16> @test_bitreverse_v2i16(
; X86-NEXT: andl $43690, %ecx # imm = 0xAAAA
; X86-NEXT: shrl %ecx
; X86-NEXT: leal (%ecx,%edx,2), %edx
-; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
-; X86-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill>
+; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
+; X86-NEXT: # kill: %dx<def> %dx<kill> %edx<kill>
; X86-NEXT: retl
;
; X64-LABEL: test_bitreverse_v2i16:
@@ -191,7 +191,7 @@ define i32 @test_bitreverse_i32(i32 %a)
;
; X64-LABEL: test_bitreverse_i32:
; X64: # BB#0:
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: bswapl %edi
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F
@@ -242,7 +242,7 @@ define i24 @test_bitreverse_i24(i24 %a)
;
; X64-LABEL: test_bitreverse_i24:
; X64: # BB#0:
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: bswapl %edi
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F
@@ -289,12 +289,12 @@ define i16 @test_bitreverse_i16(i16 %a)
; X86-NEXT: andl $43690, %eax # imm = 0xAAAA
; X86-NEXT: shrl %eax
; X86-NEXT: leal (%eax,%ecx,2), %eax
-; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X86-NEXT: retl
;
; X64-LABEL: test_bitreverse_i16:
; X64: # BB#0:
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: rolw $8, %di
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $3855, %eax # imm = 0xF0F
@@ -312,7 +312,7 @@ define i16 @test_bitreverse_i16(i16 %a)
; X64-NEXT: andl $43690, %eax # imm = 0xAAAA
; X64-NEXT: shrl %eax
; X64-NEXT: leal (%rax,%rcx,2), %eax
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
%b = call i16 @llvm.bitreverse.i16(i16 %a)
ret i16 %b
Modified: llvm/trunk/test/CodeGen/X86/bmi-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi-schedule.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bmi-schedule.ll Tue Nov 28 09:15:09 2017
@@ -14,7 +14,7 @@ define i16 @test_andn_i16(i16 zeroext %a
; GENERIC-NEXT: notl %edi # sched: [1:0.33]
; GENERIC-NEXT: andw (%rdx), %di # sched: [6:0.50]
; GENERIC-NEXT: addl %edi, %eax # sched: [1:0.33]
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_andn_i16:
@@ -23,7 +23,7 @@ define i16 @test_andn_i16(i16 zeroext %a
; HASWELL-NEXT: notl %edi # sched: [1:0.25]
; HASWELL-NEXT: andw (%rdx), %di # sched: [1:0.50]
; HASWELL-NEXT: addl %edi, %eax # sched: [1:0.25]
-; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; HASWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_andn_i16:
@@ -32,7 +32,7 @@ define i16 @test_andn_i16(i16 zeroext %a
; BROADWELL-NEXT: notl %edi # sched: [1:0.25]
; BROADWELL-NEXT: andw (%rdx), %di # sched: [6:0.50]
; BROADWELL-NEXT: addl %edi, %eax # sched: [1:0.25]
-; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; BROADWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_andn_i16:
@@ -41,7 +41,7 @@ define i16 @test_andn_i16(i16 zeroext %a
; SKYLAKE-NEXT: notl %edi # sched: [1:0.25]
; SKYLAKE-NEXT: andw (%rdx), %di # sched: [6:0.50]
; SKYLAKE-NEXT: addl %edi, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKYLAKE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_andn_i16:
@@ -50,7 +50,7 @@ define i16 @test_andn_i16(i16 zeroext %a
; BTVER2-NEXT: notl %edi # sched: [1:0.50]
; BTVER2-NEXT: andw (%rdx), %di # sched: [4:1.00]
; BTVER2-NEXT: addl %edi, %eax # sched: [1:0.50]
-; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; BTVER2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_andn_i16:
@@ -59,7 +59,7 @@ define i16 @test_andn_i16(i16 zeroext %a
; ZNVER1-NEXT: notl %edi # sched: [1:0.25]
; ZNVER1-NEXT: andw (%rdx), %di # sched: [5:0.50]
; ZNVER1-NEXT: addl %edi, %eax # sched: [1:0.25]
-; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; ZNVER1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load i16, i16 *%a2
%2 = xor i16 %a0, -1
@@ -581,7 +581,7 @@ define i16 @test_cttz_i16(i16 zeroext %a
; GENERIC-NEXT: tzcntw (%rsi), %cx
; GENERIC-NEXT: tzcntw %di, %ax
; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33]
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_cttz_i16:
@@ -589,7 +589,7 @@ define i16 @test_cttz_i16(i16 zeroext %a
; HASWELL-NEXT: tzcntw (%rsi), %cx # sched: [3:1.00]
; HASWELL-NEXT: tzcntw %di, %ax # sched: [3:1.00]
; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; HASWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_cttz_i16:
@@ -597,7 +597,7 @@ define i16 @test_cttz_i16(i16 zeroext %a
; BROADWELL-NEXT: tzcntw (%rsi), %cx # sched: [8:1.00]
; BROADWELL-NEXT: tzcntw %di, %ax # sched: [3:1.00]
; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; BROADWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_cttz_i16:
@@ -605,7 +605,7 @@ define i16 @test_cttz_i16(i16 zeroext %a
; SKYLAKE-NEXT: tzcntw (%rsi), %cx # sched: [8:1.00]
; SKYLAKE-NEXT: tzcntw %di, %ax # sched: [3:1.00]
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKYLAKE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_cttz_i16:
@@ -613,7 +613,7 @@ define i16 @test_cttz_i16(i16 zeroext %a
; BTVER2-NEXT: tzcntw (%rsi), %cx
; BTVER2-NEXT: tzcntw %di, %ax
; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
-; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; BTVER2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_cttz_i16:
@@ -621,7 +621,7 @@ define i16 @test_cttz_i16(i16 zeroext %a
; ZNVER1-NEXT: tzcntw (%rsi), %cx # sched: [6:0.50]
; ZNVER1-NEXT: tzcntw %di, %ax # sched: [2:0.25]
; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; ZNVER1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load i16, i16 *%a1
%2 = tail call i16 @llvm.cttz.i16( i16 %1, i1 false )
Modified: llvm/trunk/test/CodeGen/X86/bmi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bmi.ll Tue Nov 28 09:15:09 2017
@@ -13,7 +13,7 @@ define i8 @t1(i8 %x) {
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: orl $256, %eax # imm = 0x100
; CHECK-NEXT: tzcntl %eax, %eax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false )
ret i8 %tmp
@@ -61,7 +61,7 @@ define i8 @t5(i8 %x) {
; CHECK: # BB#0:
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: tzcntl %eax, %eax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true )
ret i8 %tmp
@@ -516,7 +516,7 @@ define i32 @bzhi32d(i32 %a, i32 %b) {
; BMI1-NEXT: movl $32, %ecx
; BMI1-NEXT: subl %esi, %ecx
; BMI1-NEXT: movl $-1, %eax
-; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
+; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill>
; BMI1-NEXT: shrl %cl, %eax
; BMI1-NEXT: andl %edi, %eax
; BMI1-NEXT: retq
@@ -538,7 +538,7 @@ define i32 @bzhi32e(i32 %a, i32 %b) {
; BMI1-NEXT: movl $32, %ecx
; BMI1-NEXT: subl %esi, %ecx
; BMI1-NEXT: shll %cl, %edi
-; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
+; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill>
; BMI1-NEXT: shrl %cl, %edi
; BMI1-NEXT: movl %edi, %eax
; BMI1-NEXT: retq
@@ -566,7 +566,7 @@ define i64 @bzhi64b(i64 %x, i8 zeroext %
;
; BMI2-LABEL: bzhi64b:
; BMI2: # BB#0: # %entry
-; BMI2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; BMI2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; BMI2-NEXT: bzhiq %rsi, %rdi, %rax
; BMI2-NEXT: retq
entry:
@@ -583,7 +583,7 @@ define i64 @bzhi64c(i64 %a, i64 %b) {
; BMI1-NEXT: movl $64, %ecx
; BMI1-NEXT: subl %esi, %ecx
; BMI1-NEXT: movq $-1, %rax
-; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
+; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill>
; BMI1-NEXT: shrq %cl, %rax
; BMI1-NEXT: andq %rdi, %rax
; BMI1-NEXT: retq
@@ -605,14 +605,14 @@ define i64 @bzhi64d(i64 %a, i32 %b) {
; BMI1-NEXT: movl $64, %ecx
; BMI1-NEXT: subl %esi, %ecx
; BMI1-NEXT: movq $-1, %rax
-; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
+; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill>
; BMI1-NEXT: shrq %cl, %rax
; BMI1-NEXT: andq %rdi, %rax
; BMI1-NEXT: retq
;
; BMI2-LABEL: bzhi64d:
; BMI2: # BB#0: # %entry
-; BMI2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; BMI2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; BMI2-NEXT: bzhiq %rsi, %rdi, %rax
; BMI2-NEXT: retq
entry:
@@ -629,7 +629,7 @@ define i64 @bzhi64e(i64 %a, i64 %b) {
; BMI1-NEXT: movl $64, %ecx
; BMI1-NEXT: subl %esi, %ecx
; BMI1-NEXT: shlq %cl, %rdi
-; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
+; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill>
; BMI1-NEXT: shrq %cl, %rdi
; BMI1-NEXT: movq %rdi, %rax
; BMI1-NEXT: retq
@@ -651,14 +651,14 @@ define i64 @bzhi64f(i64 %a, i32 %b) {
; BMI1-NEXT: movl $64, %ecx
; BMI1-NEXT: subl %esi, %ecx
; BMI1-NEXT: shlq %cl, %rdi
-; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
+; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill>
; BMI1-NEXT: shrq %cl, %rdi
; BMI1-NEXT: movq %rdi, %rax
; BMI1-NEXT: retq
;
; BMI2-LABEL: bzhi64f:
; BMI2: # BB#0: # %entry
-; BMI2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; BMI2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; BMI2-NEXT: bzhiq %rsi, %rdi, %rax
; BMI2-NEXT: retq
entry:
Modified: llvm/trunk/test/CodeGen/X86/bool-simplify.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bool-simplify.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bool-simplify.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bool-simplify.ll Tue Nov 28 09:15:09 2017
@@ -55,7 +55,7 @@ define i16 @rnd16(i16 %arg) nounwind {
; CHECK-NEXT: rdrandw %cx
; CHECK-NEXT: cmovbw %di, %ax
; CHECK-NEXT: addl %ecx, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%1 = tail call { i16, i32 } @llvm.x86.rdrand.16() nounwind
%2 = extractvalue { i16, i32 } %1, 0
@@ -107,7 +107,7 @@ define i16 @seed16(i16 %arg) nounwind {
; CHECK-NEXT: rdseedw %cx
; CHECK-NEXT: cmovbw %di, %ax
; CHECK-NEXT: addl %ecx, %eax
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%1 = tail call { i16, i32 } @llvm.x86.rdseed.16() nounwind
%2 = extractvalue { i16, i32 } %1, 0
Modified: llvm/trunk/test/CodeGen/X86/bool-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bool-vector.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bool-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bool-vector.ll Tue Nov 28 09:15:09 2017
@@ -138,10 +138,10 @@ define i32 @PR15215_good(<4 x i32> %inpu
;
; X64-LABEL: PR15215_good:
; X64: # BB#0: # %entry
-; X64-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def>
-; X64-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
-; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def>
+; X64-NEXT: # kill: %edx<def> %edx<kill> %rdx<def>
+; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: andl $1, %edi
; X64-NEXT: andl $1, %esi
; X64-NEXT: andl $1, %edx
Modified: llvm/trunk/test/CodeGen/X86/broadcastm-lowering.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/broadcastm-lowering.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/broadcastm-lowering.ll (original)
+++ llvm/trunk/test/CodeGen/X86/broadcastm-lowering.ll Tue Nov 28 09:15:09 2017
@@ -106,8 +106,8 @@ entry:
define <8 x i64> @test_mm512_epi64(<8 x i32> %a, <8 x i32> %b) {
; AVX512CD-LABEL: test_mm512_epi64:
; AVX512CD: # BB#0: # %entry
-; AVX512CD-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX512CD-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512CD-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; AVX512CD-NEXT: vpbroadcastmb2q %k0, %zmm0
; AVX512CD-NEXT: retq
@@ -140,8 +140,8 @@ entry:
define <4 x i64> @test_mm256_epi64(<8 x i32> %a, <8 x i32> %b) {
; AVX512CD-LABEL: test_mm256_epi64:
; AVX512CD: # BB#0: # %entry
-; AVX512CD-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX512CD-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512CD-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; AVX512CD-NEXT: kmovw %k0, %eax
; AVX512CD-NEXT: vpxor %xmm0, %xmm0, %xmm0
Modified: llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll Tue Nov 28 09:15:09 2017
@@ -17,7 +17,7 @@ define i32 @Test_get_quotient(i32 %a, i3
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; CHECK-NEXT: divb %cl
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: retl
@@ -41,7 +41,7 @@ define i32 @Test_get_remainder(i32 %a, i
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; CHECK-NEXT: divb %cl
; CHECK-NEXT: movzbl %ah, %eax # NOREX
; CHECK-NEXT: retl
@@ -65,7 +65,7 @@ define i32 @Test_get_quotient_and_remain
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB2_1:
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; CHECK-NEXT: divb %cl
; CHECK-NEXT: movzbl %ah, %edx # NOREX
; CHECK-NEXT: movzbl %al, %eax
@@ -103,14 +103,14 @@ define i32 @Test_use_div_and_idiv(i32 %a
; CHECK-NEXT: jmp .LBB3_6
; CHECK-NEXT: .LBB3_1:
; CHECK-NEXT: movzbl %cl, %eax
-; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; CHECK-NEXT: divb %bl
; CHECK-NEXT: movzbl %al, %esi
; CHECK-NEXT: testl $-256, %edi
; CHECK-NEXT: jne .LBB3_5
; CHECK-NEXT: .LBB3_4:
; CHECK-NEXT: movzbl %cl, %eax
-; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; CHECK-NEXT: divb %bl
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: .LBB3_6:
@@ -208,7 +208,7 @@ define i32 @Test_use_div_imm_reg(i32 %a)
; CHECK-NEXT: .LBB8_1:
; CHECK-NEXT: movb $4, %al
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; CHECK-NEXT: divb %cl
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: retl
@@ -230,7 +230,7 @@ define i32 @Test_use_rem_imm_reg(i32 %a)
; CHECK-NEXT: .LBB9_1:
; CHECK-NEXT: movb $4, %al
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; CHECK-NEXT: divb %cl
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: retl
Modified: llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll Tue Nov 28 09:15:09 2017
@@ -20,7 +20,7 @@ define i64 @Test_get_quotient(i64 %a, i6
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: divl %esi
-; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
+; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<def>
; CHECK-NEXT: retq
%result = sdiv i64 %a, %b
ret i64 %result
@@ -43,7 +43,7 @@ define i64 @Test_get_remainder(i64 %a, i
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: divl %esi
-; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
+; CHECK-NEXT: # kill: %edx<def> %edx<kill> %rdx<def>
; CHECK-NEXT: movq %rdx, %rax
; CHECK-NEXT: retq
%result = srem i64 %a, %b
@@ -67,8 +67,8 @@ define i64 @Test_get_quotient_and_remain
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: divl %esi
-; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
-; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
+; CHECK-NEXT: # kill: %edx<def> %edx<kill> %rdx<def>
+; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<def>
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: retq
%resultdiv = sdiv i64 %a, %b
Modified: llvm/trunk/test/CodeGen/X86/clz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/clz.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/clz.ll (original)
+++ llvm/trunk/test/CodeGen/X86/clz.ll Tue Nov 28 09:15:09 2017
@@ -19,28 +19,28 @@ define i8 @cttz_i8(i8 %x) {
; X32: # BB#0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: bsfl %eax, %eax
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: cttz_i8:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: bsfl %eax, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
;
; X32-CLZ-LABEL: cttz_i8:
; X32-CLZ: # BB#0:
; X32-CLZ-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-CLZ-NEXT: tzcntl %eax, %eax
-; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-CLZ-NEXT: retl
;
; X64-CLZ-LABEL: cttz_i8:
; X64-CLZ: # BB#0:
; X64-CLZ-NEXT: movzbl %dil, %eax
; X64-CLZ-NEXT: tzcntl %eax, %eax
-; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-CLZ-NEXT: retq
%tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true )
ret i8 %tmp
@@ -144,7 +144,7 @@ define i8 @ctlz_i8(i8 %x) {
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: bsrl %eax, %eax
; X32-NEXT: xorl $7, %eax
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: ctlz_i8:
@@ -152,7 +152,7 @@ define i8 @ctlz_i8(i8 %x) {
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: bsrl %eax, %eax
; X64-NEXT: xorl $7, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
;
; X32-CLZ-LABEL: ctlz_i8:
@@ -160,7 +160,7 @@ define i8 @ctlz_i8(i8 %x) {
; X32-CLZ-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-CLZ-NEXT: lzcntl %eax, %eax
; X32-CLZ-NEXT: addl $-24, %eax
-; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-CLZ-NEXT: retl
;
; X64-CLZ-LABEL: ctlz_i8:
@@ -168,7 +168,7 @@ define i8 @ctlz_i8(i8 %x) {
; X64-CLZ-NEXT: movzbl %dil, %eax
; X64-CLZ-NEXT: lzcntl %eax, %eax
; X64-CLZ-NEXT: addl $-24, %eax
-; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-CLZ-NEXT: retq
%tmp2 = call i8 @llvm.ctlz.i8( i8 %x, i1 true )
ret i8 %tmp2
@@ -179,14 +179,14 @@ define i16 @ctlz_i16(i16 %x) {
; X32: # BB#0:
; X32-NEXT: bsrw {{[0-9]+}}(%esp), %ax
; X32-NEXT: xorl $15, %eax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: ctlz_i16:
; X64: # BB#0:
; X64-NEXT: bsrw %di, %ax
; X64-NEXT: xorl $15, %eax
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
;
; X32-CLZ-LABEL: ctlz_i16:
@@ -286,11 +286,11 @@ define i8 @ctlz_i8_zero_test(i8 %n) {
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: bsrl %eax, %eax
; X32-NEXT: xorl $7, %eax
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
; X32-NEXT: .LBB8_1:
; X32-NEXT: movb $8, %al
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: ctlz_i8_zero_test:
@@ -301,11 +301,11 @@ define i8 @ctlz_i8_zero_test(i8 %n) {
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: bsrl %eax, %eax
; X64-NEXT: xorl $7, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
; X64-NEXT: .LBB8_1:
; X64-NEXT: movb $8, %al
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
;
; X32-CLZ-LABEL: ctlz_i8_zero_test:
@@ -313,7 +313,7 @@ define i8 @ctlz_i8_zero_test(i8 %n) {
; X32-CLZ-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-CLZ-NEXT: lzcntl %eax, %eax
; X32-CLZ-NEXT: addl $-24, %eax
-; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-CLZ-NEXT: retl
;
; X64-CLZ-LABEL: ctlz_i8_zero_test:
@@ -321,7 +321,7 @@ define i8 @ctlz_i8_zero_test(i8 %n) {
; X64-CLZ-NEXT: movzbl %dil, %eax
; X64-CLZ-NEXT: lzcntl %eax, %eax
; X64-CLZ-NEXT: addl $-24, %eax
-; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-CLZ-NEXT: retq
%tmp1 = call i8 @llvm.ctlz.i8(i8 %n, i1 false)
ret i8 %tmp1
@@ -337,11 +337,11 @@ define i16 @ctlz_i16_zero_test(i16 %n) {
; X32-NEXT: # BB#2: # %cond.false
; X32-NEXT: bsrw %ax, %ax
; X32-NEXT: xorl $15, %eax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
; X32-NEXT: .LBB9_1:
; X32-NEXT: movw $16, %ax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: ctlz_i16_zero_test:
@@ -351,11 +351,11 @@ define i16 @ctlz_i16_zero_test(i16 %n) {
; X64-NEXT: # BB#2: # %cond.false
; X64-NEXT: bsrw %di, %ax
; X64-NEXT: xorl $15, %eax
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
; X64-NEXT: .LBB9_1:
; X64-NEXT: movw $16, %ax
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
;
; X32-CLZ-LABEL: ctlz_i16_zero_test:
@@ -480,11 +480,11 @@ define i8 @cttz_i8_zero_test(i8 %n) {
; X32-NEXT: # BB#2: # %cond.false
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: bsfl %eax, %eax
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
; X32-NEXT: .LBB12_1
; X32-NEXT: movb $8, %al
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: cttz_i8_zero_test:
@@ -494,11 +494,11 @@ define i8 @cttz_i8_zero_test(i8 %n) {
; X64-NEXT: # BB#2: # %cond.false
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: bsfl %eax, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
; X64-NEXT: .LBB12_1:
; X64-NEXT: movb $8, %al
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
;
; X32-CLZ-LABEL: cttz_i8_zero_test:
@@ -506,7 +506,7 @@ define i8 @cttz_i8_zero_test(i8 %n) {
; X32-CLZ-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-CLZ-NEXT: orl $256, %eax # imm = 0x100
; X32-CLZ-NEXT: tzcntl %eax, %eax
-; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-CLZ-NEXT: retl
;
; X64-CLZ-LABEL: cttz_i8_zero_test:
@@ -514,7 +514,7 @@ define i8 @cttz_i8_zero_test(i8 %n) {
; X64-CLZ-NEXT: movzbl %dil, %eax
; X64-CLZ-NEXT: orl $256, %eax # imm = 0x100
; X64-CLZ-NEXT: tzcntl %eax, %eax
-; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-CLZ-NEXT: retq
%tmp1 = call i8 @llvm.cttz.i8(i8 %n, i1 false)
ret i8 %tmp1
@@ -786,7 +786,7 @@ define i8 @cttz_i8_knownbits(i8 %x) {
; X32-NEXT: orb $2, %al
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: bsfl %eax, %eax
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: cttz_i8_knownbits:
@@ -794,7 +794,7 @@ define i8 @cttz_i8_knownbits(i8 %x) {
; X64-NEXT: orb $2, %dil
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: bsfl %eax, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
;
; X32-CLZ-LABEL: cttz_i8_knownbits:
@@ -803,7 +803,7 @@ define i8 @cttz_i8_knownbits(i8 %x) {
; X32-CLZ-NEXT: orb $2, %al
; X32-CLZ-NEXT: movzbl %al, %eax
; X32-CLZ-NEXT: tzcntl %eax, %eax
-; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-CLZ-NEXT: retl
;
; X64-CLZ-LABEL: cttz_i8_knownbits:
@@ -811,7 +811,7 @@ define i8 @cttz_i8_knownbits(i8 %x) {
; X64-CLZ-NEXT: orb $2, %dil
; X64-CLZ-NEXT: movzbl %dil, %eax
; X64-CLZ-NEXT: tzcntl %eax, %eax
-; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-CLZ-NEXT: retq
%x2 = or i8 %x, 2
%tmp = call i8 @llvm.cttz.i8(i8 %x2, i1 true )
@@ -827,7 +827,7 @@ define i8 @ctlz_i8_knownbits(i8 %x) {
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: bsrl %eax, %eax
; X32-NEXT: xorl $7, %eax
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: ctlz_i8_knownbits:
@@ -836,7 +836,7 @@ define i8 @ctlz_i8_knownbits(i8 %x) {
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: bsrl %eax, %eax
; X64-NEXT: xorl $7, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
;
; X32-CLZ-LABEL: ctlz_i8_knownbits:
@@ -846,7 +846,7 @@ define i8 @ctlz_i8_knownbits(i8 %x) {
; X32-CLZ-NEXT: movzbl %al, %eax
; X32-CLZ-NEXT: lzcntl %eax, %eax
; X32-CLZ-NEXT: addl $-24, %eax
-; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-CLZ-NEXT: retl
;
; X64-CLZ-LABEL: ctlz_i8_knownbits:
@@ -855,7 +855,7 @@ define i8 @ctlz_i8_knownbits(i8 %x) {
; X64-CLZ-NEXT: movzbl %dil, %eax
; X64-CLZ-NEXT: lzcntl %eax, %eax
; X64-CLZ-NEXT: addl $-24, %eax
-; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-CLZ-NEXT: retq
%x2 = or i8 %x, 64
Modified: llvm/trunk/test/CodeGen/X86/cmov-into-branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmov-into-branch.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmov-into-branch.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmov-into-branch.ll Tue Nov 28 09:15:09 2017
@@ -65,7 +65,7 @@ define i32 @test5(i32 %a, i32* nocapture
define void @test6(i32 %a, i32 %x, i32* %y.ptr, i64* %z.ptr) {
; CHECK-LABEL: test6:
; CHECK: # BB#0: # %entry
-; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
+; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: cmovnsl (%rdx), %esi
; CHECK-NEXT: movq %rsi, (%rcx)
Modified: llvm/trunk/test/CodeGen/X86/cmov-promotion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmov-promotion.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmov-promotion.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmov-promotion.ll Tue Nov 28 09:15:09 2017
@@ -12,7 +12,7 @@ define i16 @cmov_zpromotion_8_to_16(i1 %
; CMOV-NEXT: movb $-19, %al
; CMOV-NEXT: .LBB0_2:
; CMOV-NEXT: movzbl %al, %eax
-; CMOV-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CMOV-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CMOV-NEXT: retq
;
; NO_CMOV-LABEL: cmov_zpromotion_8_to_16:
@@ -24,7 +24,7 @@ define i16 @cmov_zpromotion_8_to_16(i1 %
; NO_CMOV-NEXT: movb $-19, %al
; NO_CMOV-NEXT: .LBB0_2:
; NO_CMOV-NEXT: movzbl %al, %eax
-; NO_CMOV-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NO_CMOV-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NO_CMOV-NEXT: retl
%t0 = select i1 %c, i8 117, i8 -19
%ret = zext i8 %t0 to i16
@@ -167,7 +167,7 @@ define i16 @cmov_spromotion_8_to_16(i1 %
; CMOV-NEXT: movb $-19, %al
; CMOV-NEXT: .LBB6_2:
; CMOV-NEXT: movsbl %al, %eax
-; CMOV-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CMOV-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CMOV-NEXT: retq
;
; NO_CMOV-LABEL: cmov_spromotion_8_to_16:
@@ -179,7 +179,7 @@ define i16 @cmov_spromotion_8_to_16(i1 %
; NO_CMOV-NEXT: movb $-19, %al
; NO_CMOV-NEXT: .LBB6_2:
; NO_CMOV-NEXT: movsbl %al, %eax
-; NO_CMOV-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; NO_CMOV-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; NO_CMOV-NEXT: retl
%t0 = select i1 %c, i8 117, i8 -19
%ret = sext i8 %t0 to i16
Modified: llvm/trunk/test/CodeGen/X86/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmov.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmov.ll Tue Nov 28 09:15:09 2017
@@ -83,7 +83,7 @@ define i1 @test4() nounwind {
; CHECK-NEXT: shrb $7, %al
; CHECK-NEXT: movzbl %al, %ecx
; CHECK-NEXT: xorl $1, %ecx
-; CHECK-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
+; CHECK-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill>
; CHECK-NEXT: sarl %cl, %edx
; CHECK-NEXT: movb {{.*}}(%rip), %al
; CHECK-NEXT: testb %al, %al
Modified: llvm/trunk/test/CodeGen/X86/coalescer-dce.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalescer-dce.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/coalescer-dce.ll (original)
+++ llvm/trunk/test/CodeGen/X86/coalescer-dce.ll Tue Nov 28 09:15:09 2017
@@ -16,7 +16,7 @@ target triple = "x86_64-apple-macosx10.7
; Considering merging %vreg7 with %vreg10
; RHS = %vreg7 = [208d,272d:0)[304L,480L:0) 0 at 208d
; LHS = %vreg10 = [16d,64L:2)[64L,160L:1)[192L,240L:1)[272d,304L:3)[304L,352d:1)[352d,400d:0)[400d,400S:4) 0 at 352d 1 at 64L-phidef 2 at 16d-phikill 3 at 272d-phikill 4 at 400d
-; Remat: %vreg10<def> = MOV64r0 %vreg10<imp-def>, %EFLAGS<imp-def,dead>, %vreg10<imp-def>; GR64:%vreg10
+; Remat: %vreg10<def> = MOV64r0 %vreg10<imp-def>, %eflags<imp-def,dead>, %vreg10<imp-def>; GR64:%vreg10
; Shrink: %vreg7 = [208d,272d:0)[304L,480L:0) 0 at 208d
; live-in at 240L
; live-in at 416L
Modified: llvm/trunk/test/CodeGen/X86/combine-abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-abs.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-abs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-abs.ll Tue Nov 28 09:15:09 2017
@@ -77,9 +77,9 @@ define <4 x i64> @combine_v4i64_abs_abs(
;
; AVX512F-LABEL: combine_v4i64_abs_abs:
; AVX512F: # BB#0:
-; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512F-NEXT: vpabsq %zmm0, %zmm0
-; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: combine_v4i64_abs_abs:
Modified: llvm/trunk/test/CodeGen/X86/compress_expand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/compress_expand.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/compress_expand.ll (original)
+++ llvm/trunk/test/CodeGen/X86/compress_expand.ll Tue Nov 28 09:15:09 2017
@@ -72,11 +72,11 @@ define <4 x float> @test4(float* %base,
;
; KNL-LABEL: test4:
; KNL: # BB#0:
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; KNL-NEXT: movw $7, %ax
; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vexpandps (%rdi), %zmm0 {%k1}
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; KNL-NEXT: retq
%res = call <4 x float> @llvm.masked.expandload.v4f32(float* %base, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x float> %src0)
ret <4 x float>%res
@@ -92,11 +92,11 @@ define <2 x i64> @test5(i64* %base, <2 x
;
; KNL-LABEL: test5:
; KNL: # BB#0:
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; KNL-NEXT: movb $2, %al
; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vpexpandq (%rdi), %zmm0 {%k1}
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; KNL-NEXT: retq
%res = call <2 x i64> @llvm.masked.expandload.v2i64(i64* %base, <2 x i1> <i1 false, i1 true>, <2 x i64> %src0)
ret <2 x i64>%res
@@ -137,7 +137,7 @@ define void @test7(float* %base, <8 x fl
;
; KNL-LABEL: test7:
; KNL: # BB#0:
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpmovsxwq %xmm1, %zmm1
; KNL-NEXT: vpsllq $63, %zmm1, %zmm1
; KNL-NEXT: vptestmq %zmm1, %zmm1, %k1
@@ -198,7 +198,7 @@ define void @test10(i64* %base, <4 x i64
;
; KNL-LABEL: test10:
; KNL: # BB#0:
-; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; KNL-NEXT: vpslld $31, %xmm1, %xmm1
; KNL-NEXT: vpsrad $31, %xmm1, %xmm1
; KNL-NEXT: vpmovsxdq %xmm1, %ymm1
@@ -221,7 +221,7 @@ define void @test11(i64* %base, <2 x i64
;
; KNL-LABEL: test11:
; KNL: # BB#0:
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; KNL-NEXT: vpsllq $63, %xmm1, %xmm1
; KNL-NEXT: vpsraq $63, %zmm1, %zmm1
; KNL-NEXT: vmovdqa %xmm1, %xmm1
@@ -243,7 +243,7 @@ define void @test12(float* %base, <4 x f
;
; KNL-LABEL: test12:
; KNL: # BB#0:
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; KNL-NEXT: vpslld $31, %xmm1, %xmm1
; KNL-NEXT: vpsrad $31, %xmm1, %xmm1
; KNL-NEXT: vmovdqa %xmm1, %xmm1
@@ -266,7 +266,7 @@ define <2 x float> @test13(float* %base,
;
; KNL-LABEL: test13:
; KNL: # BB#0:
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; KNL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; KNL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
; KNL-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1
@@ -275,7 +275,7 @@ define <2 x float> @test13(float* %base,
; KNL-NEXT: vpslld $31, %zmm1, %zmm1
; KNL-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL-NEXT: vexpandps (%rdi), %zmm0 {%k1}
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; KNL-NEXT: retq
%mask = icmp eq <2 x i32> %trigger, zeroinitializer
%res = call <2 x float> @llvm.masked.expandload.v2f32(float* %base, <2 x i1> %mask, <2 x float> %src0)
@@ -293,7 +293,7 @@ define void @test14(float* %base, <2 x f
;
; KNL-LABEL: test14:
; KNL: # BB#0:
-; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
+; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; KNL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; KNL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
; KNL-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1
Modified: llvm/trunk/test/CodeGen/X86/critical-edge-split-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/critical-edge-split-2.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/critical-edge-split-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/critical-edge-split-2.ll Tue Nov 28 09:15:09 2017
@@ -25,7 +25,7 @@ define i16 @test1(i1 zeroext %C, i8** no
; CHECK-NEXT: divl %esi
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: .LBB0_2: # %cond.end.i
-; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
br i1 %C, label %cond.end.i, label %cond.false.i
Modified: llvm/trunk/test/CodeGen/X86/ctpop-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ctpop-combine.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/ctpop-combine.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ctpop-combine.ll Tue Nov 28 09:15:09 2017
@@ -55,7 +55,7 @@ define i8 @test4(i8 %x) nounwind readnon
; CHECK: # BB#0:
; CHECK-NEXT: andl $127, %edi
; CHECK-NEXT: popcntw %di, %ax
-; CHECK-NEXT: # kill: %AL<def> %AL<kill> %AX<kill>
+; CHECK-NEXT: # kill: %al<def> %al<kill> %ax<kill>
; CHECK-NEXT: retq
%x2 = and i8 %x, 127
%count = tail call i8 @llvm.ctpop.i8(i8 %x2)
Modified: llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll Tue Nov 28 09:15:09 2017
@@ -19,8 +19,8 @@ define i32 @t(i8* %ref_frame_ptr, i32 %r
;
; X64-LABEL: t:
; X64: ## BB#0: ## %entry
-; X64-NEXT: ## kill: %EDX<def> %EDX<kill> %RDX<def>
-; X64-NEXT: ## kill: %ESI<def> %ESI<kill> %RSI<def>
+; X64-NEXT: ## kill: %edx<def> %edx<kill> %rdx<def>
+; X64-NEXT: ## kill: %esi<def> %esi<kill> %rsi<def>
; X64-NEXT: imull %ecx, %esi
; X64-NEXT: leal (%rsi,%rdx), %eax
; X64-NEXT: cltq
Modified: llvm/trunk/test/CodeGen/X86/divide-by-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divide-by-constant.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/divide-by-constant.ll (original)
+++ llvm/trunk/test/CodeGen/X86/divide-by-constant.ll Tue Nov 28 09:15:09 2017
@@ -8,14 +8,14 @@ define zeroext i16 @test1(i16 zeroext %x
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: imull $63551, %eax, %eax # imm = 0xF83F
; X32-NEXT: shrl $21, %eax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test1:
; X64: # BB#0: # %entry
; X64-NEXT: imull $63551, %edi, %eax # imm = 0xF83F
; X64-NEXT: shrl $21, %eax
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
entry:
%div = udiv i16 %x, 33
@@ -28,14 +28,14 @@ define zeroext i16 @test2(i8 signext %x,
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: imull $43691, %eax, %eax # imm = 0xAAAB
; X32-NEXT: shrl $17, %eax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test2:
; X64: # BB#0: # %entry
; X64-NEXT: imull $43691, %esi, %eax # imm = 0xAAAB
; X64-NEXT: shrl $17, %eax
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
entry:
%div = udiv i16 %c, 3
@@ -50,7 +50,7 @@ define zeroext i8 @test3(i8 zeroext %x,
; X32-NEXT: imull $171, %eax, %eax
; X32-NEXT: shrl $9, %eax
; X32-NEXT: movzwl %ax, %eax
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test3:
@@ -58,7 +58,7 @@ define zeroext i8 @test3(i8 zeroext %x,
; X64-NEXT: imull $171, %esi, %eax
; X64-NEXT: shrl $9, %eax
; X64-NEXT: movzwl %ax, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
entry:
%div = udiv i8 %c, 3
@@ -74,7 +74,7 @@ define signext i16 @test4(i16 signext %x
; X32-NEXT: shrl $31, %ecx
; X32-NEXT: shrl $16, %eax
; X32-NEXT: addl %ecx, %eax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test4:
@@ -84,7 +84,7 @@ define signext i16 @test4(i16 signext %x
; X64-NEXT: shrl $31, %ecx
; X64-NEXT: shrl $16, %eax
; X64-NEXT: addl %ecx, %eax
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
entry:
%div = sdiv i16 %x, 33 ; <i32> [#uses=1]
@@ -105,7 +105,7 @@ define i32 @test5(i32 %A) nounwind {
; X64-NEXT: movl %edi, %eax
; X64-NEXT: imulq $365384439, %rax, %rax # imm = 0x15C752F7
; X64-NEXT: shrq $59, %rax
-; X64-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
+; X64-NEXT: # kill: %eax<def> %eax<kill> %rax<kill>
; X64-NEXT: retq
%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
ret i32 %tmp1
@@ -120,7 +120,7 @@ define signext i16 @test6(i16 signext %x
; X32-NEXT: shrl $31, %ecx
; X32-NEXT: sarl $18, %eax
; X32-NEXT: addl %ecx, %eax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test6:
@@ -130,7 +130,7 @@ define signext i16 @test6(i16 signext %x
; X64-NEXT: shrl $31, %ecx
; X64-NEXT: sarl $18, %eax
; X64-NEXT: addl %ecx, %eax
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
entry:
%div = sdiv i16 %x, 10
@@ -149,11 +149,11 @@ define i32 @test7(i32 %x) nounwind {
;
; X64-LABEL: test7:
; X64: # BB#0:
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: shrl $2, %edi
; X64-NEXT: imulq $613566757, %rdi, %rax # imm = 0x24924925
; X64-NEXT: shrq $32, %rax
-; X64-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
+; X64-NEXT: # kill: %eax<def> %eax<kill> %rax<kill>
; X64-NEXT: retq
%div = udiv i32 %x, 28
ret i32 %div
@@ -169,7 +169,7 @@ define i8 @test8(i8 %x) nounwind {
; X32-NEXT: imull $211, %eax, %eax
; X32-NEXT: shrl $13, %eax
; X32-NEXT: movzwl %ax, %eax
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test8:
@@ -179,7 +179,7 @@ define i8 @test8(i8 %x) nounwind {
; X64-NEXT: imull $211, %eax, %eax
; X64-NEXT: shrl $13, %eax
; X64-NEXT: movzwl %ax, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
%div = udiv i8 %x, 78
ret i8 %div
@@ -194,7 +194,7 @@ define i8 @test9(i8 %x) nounwind {
; X32-NEXT: imull $71, %eax, %eax
; X32-NEXT: shrl $11, %eax
; X32-NEXT: movzwl %ax, %eax
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test9:
@@ -204,7 +204,7 @@ define i8 @test9(i8 %x) nounwind {
; X64-NEXT: imull $71, %eax, %eax
; X64-NEXT: shrl $11, %eax
; X64-NEXT: movzwl %ax, %eax
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
%div = udiv i8 %x, 116
ret i8 %div
Modified: llvm/trunk/test/CodeGen/X86/divrem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divrem.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/divrem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/divrem.ll Tue Nov 28 09:15:09 2017
@@ -262,7 +262,7 @@ define void @ui8(i8 %x, i8 %y, i8* %p, i
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X32-NEXT: divb {{[0-9]+}}(%esp)
; X32-NEXT: movzbl %ah, %ebx # NOREX
; X32-NEXT: movb %al, (%edx)
@@ -273,7 +273,7 @@ define void @ui8(i8 %x, i8 %y, i8* %p, i
; X64-LABEL: ui8:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %ah, %esi # NOREX
; X64-NEXT: movb %al, (%rdx)
Modified: llvm/trunk/test/CodeGen/X86/divrem8_ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divrem8_ext.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/divrem8_ext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/divrem8_ext.ll Tue Nov 28 09:15:09 2017
@@ -6,7 +6,7 @@ define zeroext i8 @test_udivrem_zext_ah(
; X32-LABEL: test_udivrem_zext_ah:
; X32: # BB#0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X32-NEXT: divb {{[0-9]+}}(%esp)
; X32-NEXT: movzbl %ah, %ecx # NOREX
; X32-NEXT: movb %al, z
@@ -16,7 +16,7 @@ define zeroext i8 @test_udivrem_zext_ah(
; X64-LABEL: test_udivrem_zext_ah:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %ah, %ecx # NOREX
; X64-NEXT: movb %al, {{.*}}(%rip)
@@ -32,19 +32,19 @@ define zeroext i8 @test_urem_zext_ah(i8
; X32-LABEL: test_urem_zext_ah:
; X32: # BB#0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X32-NEXT: divb {{[0-9]+}}(%esp)
; X32-NEXT: movzbl %ah, %eax # NOREX
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test_urem_zext_ah:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %ah, %eax # NOREX
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
%1 = urem i8 %x, %y
ret i8 %1
@@ -55,21 +55,21 @@ define i8 @test_urem_noext_ah(i8 %x, i8
; X32: # BB#0:
; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X32-NEXT: divb %cl
; X32-NEXT: movzbl %ah, %eax # NOREX
; X32-NEXT: addb %cl, %al
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test_urem_noext_ah:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %ah, %eax # NOREX
; X64-NEXT: addb %sil, %al
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
%1 = urem i8 %x, %y
%2 = add i8 %1, %y
@@ -80,7 +80,7 @@ define i64 @test_urem_zext64_ah(i8 %x, i
; X32-LABEL: test_urem_zext64_ah:
; X32: # BB#0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X32-NEXT: divb {{[0-9]+}}(%esp)
; X32-NEXT: movzbl %ah, %eax # NOREX
; X32-NEXT: xorl %edx, %edx
@@ -89,7 +89,7 @@ define i64 @test_urem_zext64_ah(i8 %x, i
; X64-LABEL: test_urem_zext64_ah:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %ah, %eax # NOREX
; X64-NEXT: retq
@@ -131,7 +131,7 @@ define signext i8 @test_srem_sext_ah(i8
; X32-NEXT: cbtw
; X32-NEXT: idivb {{[0-9]+}}(%esp)
; X32-NEXT: movsbl %ah, %eax # NOREX
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test_srem_sext_ah:
@@ -140,7 +140,7 @@ define signext i8 @test_srem_sext_ah(i8
; X64-NEXT: cbtw
; X64-NEXT: idivb %sil
; X64-NEXT: movsbl %ah, %eax # NOREX
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
%1 = srem i8 %x, %y
ret i8 %1
@@ -155,7 +155,7 @@ define i8 @test_srem_noext_ah(i8 %x, i8
; X32-NEXT: idivb %cl
; X32-NEXT: movsbl %ah, %eax # NOREX
; X32-NEXT: addb %cl, %al
-; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test_srem_noext_ah:
@@ -165,7 +165,7 @@ define i8 @test_srem_noext_ah(i8 %x, i8
; X64-NEXT: idivb %sil
; X64-NEXT: movsbl %ah, %eax # NOREX
; X64-NEXT: addb %sil, %al
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
%1 = srem i8 %x, %y
%2 = add i8 %1, %y
@@ -200,7 +200,7 @@ define i64 @pr25754(i8 %a, i8 %c) {
; X32-LABEL: pr25754:
; X32: # BB#0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X32-NEXT: divb {{[0-9]+}}(%esp)
; X32-NEXT: movzbl %ah, %ecx # NOREX
; X32-NEXT: movzbl %al, %eax
@@ -211,7 +211,7 @@ define i64 @pr25754(i8 %a, i8 %c) {
; X64-LABEL: pr25754:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %ah, %ecx # NOREX
; X64-NEXT: movzbl %al, %eax
Modified: llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir (original)
+++ llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir Tue Nov 28 09:15:09 2017
@@ -48,7 +48,7 @@ body: |
; Save AL.
; CHECK: PUSH32r killed %eax
- ; Copy EDI into EFLAGS
+ ; Copy edi into EFLAGS
; CHECK-NEXT: %eax = MOV32rr %edi
; CHECK-NEXT: %al = ADD8ri %al, 127, implicit-def %eflags
; CHECK-NEXT: SAHF implicit-def %eflags, implicit %ah
Modified: llvm/trunk/test/CodeGen/X86/extractelement-index.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extractelement-index.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/extractelement-index.ll (original)
+++ llvm/trunk/test/CodeGen/X86/extractelement-index.ll Tue Nov 28 09:15:09 2017
@@ -13,19 +13,19 @@ define i8 @extractelement_v16i8_1(<16 x
; SSE2: # BB#0:
; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: shrl $8, %eax
-; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-NEXT: retq
;
; SSE41-LABEL: extractelement_v16i8_1:
; SSE41: # BB#0:
; SSE41-NEXT: pextrb $1, %xmm0, %eax
-; SSE41-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE41-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE41-NEXT: retq
;
; AVX-LABEL: extractelement_v16i8_1:
; AVX: # BB#0:
; AVX-NEXT: vpextrb $1, %xmm0, %eax
-; AVX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX-NEXT: retq
%b = extractelement <16 x i8> %a, i256 1
ret i8 %b
@@ -36,19 +36,19 @@ define i8 @extractelement_v16i8_11(<16 x
; SSE2: # BB#0:
; SSE2-NEXT: pextrw $5, %xmm0, %eax
; SSE2-NEXT: shrl $8, %eax
-; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-NEXT: retq
;
; SSE41-LABEL: extractelement_v16i8_11:
; SSE41: # BB#0:
; SSE41-NEXT: pextrb $11, %xmm0, %eax
-; SSE41-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE41-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE41-NEXT: retq
;
; AVX-LABEL: extractelement_v16i8_11:
; AVX: # BB#0:
; AVX-NEXT: vpextrb $11, %xmm0, %eax
-; AVX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX-NEXT: retq
%b = extractelement <16 x i8> %a, i256 11
ret i8 %b
@@ -58,19 +58,19 @@ define i8 @extractelement_v16i8_14(<16 x
; SSE2-LABEL: extractelement_v16i8_14:
; SSE2: # BB#0:
; SSE2-NEXT: pextrw $7, %xmm0, %eax
-; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-NEXT: retq
;
; SSE41-LABEL: extractelement_v16i8_14:
; SSE41: # BB#0:
; SSE41-NEXT: pextrb $14, %xmm0, %eax
-; SSE41-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE41-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE41-NEXT: retq
;
; AVX-LABEL: extractelement_v16i8_14:
; AVX: # BB#0:
; AVX-NEXT: vpextrb $14, %xmm0, %eax
-; AVX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX-NEXT: retq
%b = extractelement <16 x i8> %a, i256 14
ret i8 %b
@@ -81,19 +81,19 @@ define i8 @extractelement_v32i8_1(<32 x
; SSE2: # BB#0:
; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: shrl $8, %eax
-; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-NEXT: retq
;
; SSE41-LABEL: extractelement_v32i8_1:
; SSE41: # BB#0:
; SSE41-NEXT: pextrb $1, %xmm0, %eax
-; SSE41-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE41-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE41-NEXT: retq
;
; AVX-LABEL: extractelement_v32i8_1:
; AVX: # BB#0:
; AVX-NEXT: vpextrb $1, %xmm0, %eax
-; AVX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%b = extractelement <32 x i8> %a, i256 1
@@ -105,20 +105,20 @@ define i8 @extractelement_v32i8_17(<32 x
; SSE2: # BB#0:
; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: shrl $8, %eax
-; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE2-NEXT: retq
;
; SSE41-LABEL: extractelement_v32i8_17:
; SSE41: # BB#0:
; SSE41-NEXT: pextrb $1, %xmm1, %eax
-; SSE41-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE41-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SSE41-NEXT: retq
;
; AVX1-LABEL: extractelement_v32i8_17:
; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpextrb $1, %xmm0, %eax
-; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -126,7 +126,7 @@ define i8 @extractelement_v32i8_17(<32 x
; AVX2: # BB#0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vpextrb $1, %xmm0, %eax
-; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
%b = extractelement <32 x i8> %a, i256 17
@@ -137,13 +137,13 @@ define i16 @extractelement_v8i16_0(<8 x
; SSE-LABEL: extractelement_v8i16_0:
; SSE: # BB#0:
; SSE-NEXT: movd %xmm0, %eax
-; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX-LABEL: extractelement_v8i16_0:
; AVX: # BB#0:
; AVX-NEXT: vmovd %xmm0, %eax
-; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX-NEXT: retq
%b = extractelement <8 x i16> %a, i256 0
ret i16 %b
@@ -153,13 +153,13 @@ define i16 @extractelement_v8i16_3(<8 x
; SSE-LABEL: extractelement_v8i16_3:
; SSE: # BB#0:
; SSE-NEXT: pextrw $3, %xmm0, %eax
-; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX-LABEL: extractelement_v8i16_3:
; AVX: # BB#0:
; AVX-NEXT: vpextrw $3, %xmm0, %eax
-; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX-NEXT: retq
%b = extractelement <8 x i16> %a, i256 3
ret i16 %b
@@ -169,13 +169,13 @@ define i16 @extractelement_v16i16_0(<16
; SSE-LABEL: extractelement_v16i16_0:
; SSE: # BB#0:
; SSE-NEXT: movd %xmm0, %eax
-; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX-LABEL: extractelement_v16i16_0:
; AVX: # BB#0:
; AVX-NEXT: vmovd %xmm0, %eax
-; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%b = extractelement <16 x i16> %a, i256 0
@@ -186,14 +186,14 @@ define i16 @extractelement_v16i16_13(<16
; SSE-LABEL: extractelement_v16i16_13:
; SSE: # BB#0:
; SSE-NEXT: pextrw $5, %xmm1, %eax
-; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SSE-NEXT: retq
;
; AVX1-LABEL: extractelement_v16i16_13:
; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpextrw $5, %xmm0, %eax
-; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -201,7 +201,7 @@ define i16 @extractelement_v16i16_13(<16
; AVX2: # BB#0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vpextrw $5, %xmm0, %eax
-; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
%b = extractelement <16 x i16> %a, i256 13
Modified: llvm/trunk/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll Tue Nov 28 09:15:09 2017
@@ -43,7 +43,7 @@ define i16 @test_cvtss_sh(float %a0) nou
; X32-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
; X32-NEXT: vcvtps2ph $0, %xmm0, %xmm0
; X32-NEXT: vmovd %xmm0, %eax
-; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
;
; X64-LABEL: test_cvtss_sh:
@@ -52,7 +52,7 @@ define i16 @test_cvtss_sh(float %a0) nou
; X64-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
; X64-NEXT: vcvtps2ph $0, %xmm0, %xmm0
; X64-NEXT: vmovd %xmm0, %eax
-; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
%ins0 = insertelement <4 x float> undef, float %a0, i32 0
%ins1 = insertelement <4 x float> %ins0, float 0.000000e+00, i32 1
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-cmp.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-cmp.ll Tue Nov 28 09:15:09 2017
@@ -10,7 +10,7 @@ define zeroext i1 @fcmp_oeq(float %x, fl
; SDAG-NEXT: cmpeqss %xmm1, %xmm0
; SDAG-NEXT: movd %xmm0, %eax
; SDAG-NEXT: andl $1, %eax
-; SDAG-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SDAG-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SDAG-NEXT: retq
;
; FAST_NOAVX-LABEL: fcmp_oeq:
@@ -354,7 +354,7 @@ define zeroext i1 @fcmp_une(float %x, fl
; SDAG-NEXT: cmpneqss %xmm1, %xmm0
; SDAG-NEXT: movd %xmm0, %eax
; SDAG-NEXT: andl $1, %eax
-; SDAG-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SDAG-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SDAG-NEXT: retq
;
; FAST_NOAVX-LABEL: fcmp_une:
@@ -594,7 +594,7 @@ define zeroext i1 @fcmp_oeq3(float %x) {
; SDAG-NEXT: cmpeqss %xmm0, %xmm1
; SDAG-NEXT: movd %xmm1, %eax
; SDAG-NEXT: andl $1, %eax
-; SDAG-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SDAG-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SDAG-NEXT: retq
;
; FAST_NOAVX-LABEL: fcmp_oeq3:
@@ -1249,7 +1249,7 @@ define zeroext i1 @fcmp_une3(float %x) {
; SDAG-NEXT: cmpneqss %xmm0, %xmm1
; SDAG-NEXT: movd %xmm1, %eax
; SDAG-NEXT: andl $1, %eax
-; SDAG-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; SDAG-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; SDAG-NEXT: retq
;
; FAST_NOAVX-LABEL: fcmp_une3:
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll Tue Nov 28 09:15:09 2017
@@ -547,7 +547,7 @@ define <8 x float> @test_load_nt8xfloat(
; AVX1-LABEL: test_load_nt8xfloat:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
@@ -589,7 +589,7 @@ define <4 x double> @test_load_nt4xdoubl
; AVX1-LABEL: test_load_nt4xdouble:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
@@ -631,7 +631,7 @@ define <32 x i8> @test_load_nt32xi8(<32
; AVX1-LABEL: test_load_nt32xi8:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
@@ -673,7 +673,7 @@ define <16 x i16> @test_load_nt16xi16(<1
; AVX1-LABEL: test_load_nt16xi16:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
@@ -715,7 +715,7 @@ define <8 x i32> @test_load_nt8xi32(<8 x
; AVX1-LABEL: test_load_nt8xi32:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
@@ -757,7 +757,7 @@ define <4 x i64> @test_load_nt4xi64(<4 x
; AVX1-LABEL: test_load_nt4xi64:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
@@ -997,12 +997,12 @@ define <16 x float> @test_load_nt16xfloa
; AVX1-LABEL: test_load_nt16xfloat:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm2, %xmm1
; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
@@ -1051,12 +1051,12 @@ define <8 x double> @test_load_nt8xdoubl
; AVX1-LABEL: test_load_nt8xdouble:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm2, %xmm1
; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
@@ -1105,12 +1105,12 @@ define <64 x i8> @test_load_nt64xi8(<64
; AVX1-LABEL: test_load_nt64xi8:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm2, %xmm1
; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
@@ -1171,12 +1171,12 @@ define <32 x i16> @test_load_nt32xi16(<3
; AVX1-LABEL: test_load_nt32xi16:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm2, %xmm1
; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
@@ -1237,12 +1237,12 @@ define <16 x i32> @test_load_nt16xi32(<1
; AVX1-LABEL: test_load_nt16xi32:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm2, %xmm1
; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
@@ -1291,12 +1291,12 @@ define <8 x i64> @test_load_nt8xi64(<8 x
; AVX1-LABEL: test_load_nt8xi64:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovntdqa (%rdi), %xmm0
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm0, %xmm1
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2
-; AVX1-NEXT: # implicit-def: %YMM1
+; AVX1-NEXT: # implicit-def: %ymm1
; AVX1-NEXT: vmovaps %xmm2, %xmm1
; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-sext-zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-sext-zext.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-sext-zext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-sext-zext.ll Tue Nov 28 09:15:09 2017
@@ -30,7 +30,7 @@ define i16 @test2(i16 %x) nounwind {
; X32-NEXT: andb $1, %al
; X32-NEXT: negb %al
; X32-NEXT: movsbl %al, %eax
-; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
; X32-NEXT: ## -- End function
;
@@ -39,7 +39,7 @@ define i16 @test2(i16 %x) nounwind {
; X64-NEXT: andb $1, %dil
; X64-NEXT: negb %dil
; X64-NEXT: movsbl %dil, %eax
-; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
; X64-NEXT: ## -- End function
%z = trunc i16 %x to i1
@@ -116,7 +116,7 @@ define i16 @test6(i16 %x) nounwind {
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: andb $1, %al
; X32-NEXT: movzbl %al, %eax
-; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
; X32-NEXT: ## -- End function
;
@@ -124,7 +124,7 @@ define i16 @test6(i16 %x) nounwind {
; X64: ## BB#0:
; X64-NEXT: andb $1, %dil
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
; X64-NEXT: ## -- End function
%z = trunc i16 %x to i1
@@ -176,14 +176,14 @@ define i16 @test9(i8 %x) nounwind {
; X32-LABEL: test9:
; X32: ## BB#0:
; X32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
; X32-NEXT: ## -- End function
;
; X64-LABEL: test9:
; X64: ## BB#0:
; X64-NEXT: movsbl %dil, %eax
-; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
; X64-NEXT: ## -- End function
%u = sext i8 %x to i16
@@ -228,14 +228,14 @@ define i16 @test12(i8 %x) nounwind {
; X32-LABEL: test12:
; X32: ## BB#0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X32-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: retl
; X32-NEXT: ## -- End function
;
; X64-LABEL: test12:
; X64: ## BB#0:
; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: retq
; X64-NEXT: ## -- End function
%u = zext i8 %x to i16
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-shift.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-shift.ll Tue Nov 28 09:15:09 2017
@@ -16,7 +16,7 @@ define i16 @shl_i16(i16 %a, i16 %b) {
; CHECK-LABEL: shl_i16:
; CHECK: ## BB#0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: %CL<def> %CX<kill>
+; CHECK-NEXT: ## kill: %cl<def> %cx<kill>
; CHECK-NEXT: shlw %cl, %di
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
@@ -28,7 +28,7 @@ define i32 @shl_i32(i32 %a, i32 %b) {
; CHECK-LABEL: shl_i32:
; CHECK: ## BB#0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: %CL<def> %ECX<kill>
+; CHECK-NEXT: ## kill: %cl<def> %ecx<kill>
; CHECK-NEXT: shll %cl, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
@@ -40,7 +40,7 @@ define i64 @shl_i64(i64 %a, i64 %b) {
; CHECK-LABEL: shl_i64:
; CHECK: ## BB#0:
; CHECK-NEXT: movq %rsi, %rcx
-; CHECK-NEXT: ## kill: %CL<def> %RCX<kill>
+; CHECK-NEXT: ## kill: %cl<def> %rcx<kill>
; CHECK-NEXT: shlq %cl, %rdi
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: retq
@@ -63,7 +63,7 @@ define i16 @lshr_i16(i16 %a, i16 %b) {
; CHECK-LABEL: lshr_i16:
; CHECK: ## BB#0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: %CL<def> %CX<kill>
+; CHECK-NEXT: ## kill: %cl<def> %cx<kill>
; CHECK-NEXT: shrw %cl, %di
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
@@ -75,7 +75,7 @@ define i32 @lshr_i32(i32 %a, i32 %b) {
; CHECK-LABEL: lshr_i32:
; CHECK: ## BB#0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: %CL<def> %ECX<kill>
+; CHECK-NEXT: ## kill: %cl<def> %ecx<kill>
; CHECK-NEXT: shrl %cl, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
@@ -87,7 +87,7 @@ define i64 @lshr_i64(i64 %a, i64 %b) {
; CHECK-LABEL: lshr_i64:
; CHECK: ## BB#0:
; CHECK-NEXT: movq %rsi, %rcx
-; CHECK-NEXT: ## kill: %CL<def> %RCX<kill>
+; CHECK-NEXT: ## kill: %cl<def> %rcx<kill>
; CHECK-NEXT: shrq %cl, %rdi
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: retq
@@ -110,7 +110,7 @@ define i16 @ashr_i16(i16 %a, i16 %b) {
; CHECK-LABEL: ashr_i16:
; CHECK: ## BB#0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: %CL<def> %CX<kill>
+; CHECK-NEXT: ## kill: %cl<def> %cx<kill>
; CHECK-NEXT: sarw %cl, %di
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
@@ -122,7 +122,7 @@ define i32 @ashr_i32(i32 %a, i32 %b) {
; CHECK-LABEL: ashr_i32:
; CHECK: ## BB#0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: %CL<def> %ECX<kill>
+; CHECK-NEXT: ## kill: %cl<def> %ecx<kill>
; CHECK-NEXT: sarl %cl, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
@@ -134,7 +134,7 @@ define i64 @ashr_i64(i64 %a, i64 %b) {
; CHECK-LABEL: ashr_i64:
; CHECK: ## BB#0:
; CHECK-NEXT: movq %rsi, %rcx
-; CHECK-NEXT: ## kill: %CL<def> %RCX<kill>
+; CHECK-NEXT: ## kill: %cl<def> %rcx<kill>
; CHECK-NEXT: sarq %cl, %rdi
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: retq
@@ -155,9 +155,9 @@ define i8 @shl_imm1_i8(i8 %a) {
define i16 @shl_imm1_i16(i16 %a) {
; CHECK-LABEL: shl_imm1_i16:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: leal (,%rdi,2), %eax
-; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: retq
%c = shl i16 %a, 1
ret i16 %c
@@ -166,7 +166,7 @@ define i16 @shl_imm1_i16(i16 %a) {
define i32 @shl_imm1_i32(i32 %a) {
; CHECK-LABEL: shl_imm1_i32:
; CHECK: ## BB#0:
-; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: leal (,%rdi,2), %eax
; CHECK-NEXT: retq
%c = shl i32 %a, 1
Modified: llvm/trunk/test/CodeGen/X86/fixup-bw-copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fixup-bw-copy.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fixup-bw-copy.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fixup-bw-copy.ll Tue Nov 28 09:15:09 2017
@@ -54,7 +54,7 @@ define i8 @test_movb_hreg(i16 %a0) {
; X64-NEXT: movl %edi, %eax
; X64-NEXT: shrl $8, %eax
; X64-NEXT: addb %dil, %al
-; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X64-NEXT: retq
;
; X32-LABEL: test_movb_hreg:
Modified: llvm/trunk/test/CodeGen/X86/fp_load_cast_fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp_load_cast_fold.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fp_load_cast_fold.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fp_load_cast_fold.ll Tue Nov 28 09:15:09 2017
@@ -20,7 +20,7 @@ define double @long(i64* %P) {
; CHECK: long
; CHECK: fild
-; CHECK-NOT: ESP
+; CHECK-NOT: esp
; CHECK-NOT: esp
; CHECK: {{$}}
; CHECK: ret
Modified: llvm/trunk/test/CodeGen/X86/ghc-cc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ghc-cc.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/ghc-cc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ghc-cc.ll Tue Nov 28 09:15:09 2017
@@ -2,10 +2,10 @@
; Test the GHC call convention works (x86-32)
- at base = external global i32 ; assigned to register: EBX
- at sp = external global i32 ; assigned to register: EBP
- at hp = external global i32 ; assigned to register: EDI
- at r1 = external global i32 ; assigned to register: ESI
+ at base = external global i32 ; assigned to register: ebx
+ at sp = external global i32 ; assigned to register: ebp
+ at hp = external global i32 ; assigned to register: edi
+ at r1 = external global i32 ; assigned to register: esi
define void @zap(i32 %a, i32 %b) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/X86/ghc-cc64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ghc-cc64.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/ghc-cc64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ghc-cc64.ll Tue Nov 28 09:15:09 2017
@@ -3,22 +3,22 @@
; Check the GHC call convention works (x86-64)
@base = external global i64 ; assigned to register: R13
- at sp = external global i64 ; assigned to register: RBP
+ at sp = external global i64 ; assigned to register: rbp
@hp = external global i64 ; assigned to register: R12
- at r1 = external global i64 ; assigned to register: RBX
+ at r1 = external global i64 ; assigned to register: rbx
@r2 = external global i64 ; assigned to register: R14
- at r3 = external global i64 ; assigned to register: RSI
- at r4 = external global i64 ; assigned to register: RDI
+ at r3 = external global i64 ; assigned to register: rsi
+ at r4 = external global i64 ; assigned to register: rdi
@r5 = external global i64 ; assigned to register: R8
@r6 = external global i64 ; assigned to register: R9
@splim = external global i64 ; assigned to register: R15
- at f1 = external global float ; assigned to register: XMM1
- at f2 = external global float ; assigned to register: XMM2
- at f3 = external global float ; assigned to register: XMM3
- at f4 = external global float ; assigned to register: XMM4
- at d1 = external global double ; assigned to register: XMM5
- at d2 = external global double ; assigned to register: XMM6
+ at f1 = external global float ; assigned to register: xmm1
+ at f2 = external global float ; assigned to register: xmm2
+ at f3 = external global float ; assigned to register: xmm3
+ at f4 = external global float ; assigned to register: xmm4
+ at d1 = external global double ; assigned to register: xmm5
+ at d2 = external global double ; assigned to register: xmm6
define void @zap(i64 %a, i64 %b) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/X86/gpr-to-mask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/gpr-to-mask.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/gpr-to-mask.ll (original)
+++ llvm/trunk/test/CodeGen/X86/gpr-to-mask.ll Tue Nov 28 09:15:09 2017
@@ -167,8 +167,8 @@ exit:
define void @test_shl1(i1 %cond, i8* %ptr1, i8* %ptr2, <8 x float> %fvec1, <8 x float> %fvec2, <8 x float>* %fptrvec) {
; CHECK-LABEL: test_shl1:
; CHECK: # BB#0: # %entry
-; CHECK-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; CHECK-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; CHECK-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; CHECK-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: je .LBB5_2
; CHECK-NEXT: # BB#1: # %if
@@ -205,8 +205,8 @@ exit:
define void @test_shr1(i1 %cond, i8* %ptr1, i8* %ptr2, <8 x float> %fvec1, <8 x float> %fvec2, <8 x float>* %fptrvec) {
; CHECK-LABEL: test_shr1:
; CHECK: # BB#0: # %entry
-; CHECK-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; CHECK-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; CHECK-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; CHECK-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: je .LBB6_2
; CHECK-NEXT: # BB#1: # %if
@@ -244,8 +244,8 @@ exit:
define void @test_shr2(i1 %cond, i8* %ptr1, i8* %ptr2, <8 x float> %fvec1, <8 x float> %fvec2, <8 x float>* %fptrvec) {
; CHECK-LABEL: test_shr2:
; CHECK: # BB#0: # %entry
-; CHECK-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; CHECK-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; CHECK-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; CHECK-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: je .LBB7_2
; CHECK-NEXT: # BB#1: # %if
@@ -282,8 +282,8 @@ exit:
define void @test_shl(i1 %cond, i8* %ptr1, i8* %ptr2, <8 x float> %fvec1, <8 x float> %fvec2, <8 x float>* %fptrvec) {
; CHECK-LABEL: test_shl:
; CHECK: # BB#0: # %entry
-; CHECK-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; CHECK-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; CHECK-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; CHECK-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: je .LBB8_2
; CHECK-NEXT: # BB#1: # %if
@@ -320,8 +320,8 @@ exit:
define void @test_add(i1 %cond, i8* %ptr1, i8* %ptr2, <8 x float> %fvec1, <8 x float> %fvec2, <8 x float>* %fptrvec) {
; CHECK-LABEL: test_add:
; CHECK: # BB#0: # %entry
-; CHECK-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
-; CHECK-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; CHECK-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
+; CHECK-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; CHECK-NEXT: kmovb (%rsi), %k0
; CHECK-NEXT: kmovb (%rdx), %k1
; CHECK-NEXT: testb $1, %dil
Modified: llvm/trunk/test/CodeGen/X86/half.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/half.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/half.ll (original)
+++ llvm/trunk/test/CodeGen/X86/half.ll Tue Nov 28 09:15:09 2017
@@ -777,7 +777,7 @@ define void @test_trunc64_vec4(<4 x doub
; BWON-F16C-NEXT: callq __truncdfhf2
; BWON-F16C-NEXT: movl %eax, %r15d
; BWON-F16C-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload
-; BWON-F16C-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; BWON-F16C-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; BWON-F16C-NEXT: vzeroupper
; BWON-F16C-NEXT: callq __truncdfhf2
; BWON-F16C-NEXT: movl %eax, %ebp
Modified: llvm/trunk/test/CodeGen/X86/handle-move.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/handle-move.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/handle-move.ll (original)
+++ llvm/trunk/test/CodeGen/X86/handle-move.ll Tue Nov 28 09:15:09 2017
@@ -5,10 +5,10 @@
; Test the LiveIntervals::handleMove() function.
;
; Moving the DIV32r instruction exercises the regunit update code because
-; %EDX has a live range into the function and is used by the DIV32r.
+; %edx has a live range into the function and is used by the DIV32r.
;
; Here sinking a kill + dead def:
-; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def>, %EDX<imp-def,dead>, %EFLAGS<imp-def,dead>, %EAX<imp-use,kill>, %EDX<imp-use>
+; 144B -> 180B: DIV32r %vreg4, %eax<imp-def>, %edx<imp-def,dead>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use>
; %vreg4: [48r,144r:0) 0 at 48r
; --> [48r,180r:0) 0 at 48r
; DH: [0B,16r:0)[128r,144r:2)[144r,144d:1) 0 at 0B-phi 1 at 144r 2 at 128r
@@ -25,7 +25,7 @@ entry:
}
; Same as above, but moving a kill + live def:
-; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def,dead>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use,kill>, %EDX<imp-use>
+; 144B -> 180B: DIV32r %vreg4, %eax<imp-def,dead>, %edx<imp-def>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use>
; %vreg4: [48r,144r:0) 0 at 48r
; --> [48r,180r:0) 0 at 48r
; DH: [0B,16r:0)[128r,144r:2)[144r,184r:1) 0 at 0B-phi 1 at 144r 2 at 128r
@@ -59,7 +59,7 @@ entry:
}
; Move EFLAGS dead def across another def:
-; handleMove 208B -> 36B: %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
+; handleMove 208B -> 36B: %edx<def> = MOV32r0 %EFLAGS<imp-def,dead>
; EFLAGS: [20r,20d:4)[160r,160d:3)[208r,208d:0)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0 at 208r 1 at 224r 2 at 272r 3 at 160r 4 at 20r 5 at 304r
; --> [20r,20d:4)[36r,36d:0)[160r,160d:3)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0 at 36r 1 at 224r 2 at 272r 3 at 160r 4 at 20r 5 at 304r
;
Modified: llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll (original)
+++ llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll Tue Nov 28 09:15:09 2017
@@ -206,7 +206,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X86-SSE2-NEXT: psrld $16, %xmm1
; X86-SSE2-NEXT: pmaxsw %xmm0, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v8i16:
@@ -216,7 +216,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: pxor %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX-LABEL: test_reduce_v8i16:
@@ -226,7 +226,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, %eax
-; X86-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX-NEXT: retl
;
; X64-SSE2-LABEL: test_reduce_v8i16:
@@ -239,7 +239,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X64-SSE2-NEXT: psrld $16, %xmm1
; X64-SSE2-NEXT: pmaxsw %xmm0, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v8i16:
@@ -249,7 +249,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: pxor %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX-LABEL: test_reduce_v8i16:
@@ -259,7 +259,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vmovd %xmm0, %eax
-; X64-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX-NEXT: retq
%1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp sgt <8 x i16> %a0, %1
@@ -304,7 +304,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-SSE2-NEXT: pandn %xmm0, %xmm1
; X86-SSE2-NEXT: por %xmm2, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v16i8:
@@ -320,7 +320,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pmaxsb %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX-LABEL: test_reduce_v16i8:
@@ -334,7 +334,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX-NEXT: retl
;
; X64-SSE2-LABEL: test_reduce_v16i8:
@@ -366,7 +366,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-SSE2-NEXT: pandn %xmm0, %xmm1
; X64-SSE2-NEXT: por %xmm2, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v16i8:
@@ -382,7 +382,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pmaxsb %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX-LABEL: test_reduce_v16i8:
@@ -396,7 +396,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX-NEXT: retq
%1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp sgt <16 x i8> %a0, %1
@@ -746,7 +746,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-SSE2-NEXT: psrld $16, %xmm1
; X86-SSE2-NEXT: pmaxsw %xmm0, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v16i16:
@@ -757,7 +757,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: pxor %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v16i16:
@@ -769,7 +769,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -782,7 +782,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -797,7 +797,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-SSE2-NEXT: psrld $16, %xmm1
; X64-SSE2-NEXT: pmaxsw %xmm0, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v16i16:
@@ -808,7 +808,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: pxor %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v16i16:
@@ -820,7 +820,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -833,7 +833,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -846,7 +846,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -900,7 +900,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-SSE2-NEXT: pandn %xmm0, %xmm2
; X86-SSE2-NEXT: por %xmm1, %xmm2
; X86-SSE2-NEXT: movd %xmm2, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v32i8:
@@ -917,7 +917,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pmaxsb %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v32i8:
@@ -933,7 +933,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -950,7 +950,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -988,7 +988,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-SSE2-NEXT: pandn %xmm0, %xmm2
; X64-SSE2-NEXT: por %xmm1, %xmm2
; X64-SSE2-NEXT: movd %xmm2, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v32i8:
@@ -1005,7 +1005,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pmaxsb %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v32i8:
@@ -1021,7 +1021,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1038,7 +1038,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1055,7 +1055,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <32 x i8> %a0, <32 x i8> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -1552,7 +1552,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-SSE2-NEXT: psrld $16, %xmm1
; X86-SSE2-NEXT: pmaxsw %xmm0, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v32i16:
@@ -1565,7 +1565,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: pxor %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v32i16:
@@ -1580,7 +1580,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1594,7 +1594,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1611,7 +1611,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-SSE2-NEXT: psrld $16, %xmm1
; X64-SSE2-NEXT: pmaxsw %xmm0, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v32i16:
@@ -1624,7 +1624,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: pxor %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v32i16:
@@ -1639,7 +1639,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1653,7 +1653,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1668,7 +1668,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <32 x i16> %a0, <32 x i16> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -1735,7 +1735,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-SSE2-NEXT: pandn %xmm0, %xmm1
; X86-SSE2-NEXT: por %xmm2, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v64i8:
@@ -1754,7 +1754,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pmaxsb %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v64i8:
@@ -1773,7 +1773,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1791,7 +1791,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1839,7 +1839,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-SSE2-NEXT: pandn %xmm0, %xmm1
; X64-SSE2-NEXT: por %xmm2, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v64i8:
@@ -1858,7 +1858,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pmaxsb %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v64i8:
@@ -1877,7 +1877,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1895,7 +1895,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1914,7 +1914,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpmaxsb %zmm1, %zmm0, %zmm0
; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <64 x i8> %a0, <64 x i8> undef, <64 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
Modified: llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll (original)
+++ llvm/trunk/test/CodeGen/X86/horizontal-reduce-smin.ll Tue Nov 28 09:15:09 2017
@@ -208,7 +208,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X86-SSE2-NEXT: psrld $16, %xmm1
; X86-SSE2-NEXT: pminsw %xmm0, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v8i16:
@@ -218,7 +218,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: pxor %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX-LABEL: test_reduce_v8i16:
@@ -228,7 +228,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, %eax
-; X86-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX-NEXT: retl
;
; X64-SSE2-LABEL: test_reduce_v8i16:
@@ -241,7 +241,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X64-SSE2-NEXT: psrld $16, %xmm1
; X64-SSE2-NEXT: pminsw %xmm0, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v8i16:
@@ -251,7 +251,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: pxor %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX-LABEL: test_reduce_v8i16:
@@ -261,7 +261,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vmovd %xmm0, %eax
-; X64-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX-NEXT: retq
%1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp slt <8 x i16> %a0, %1
@@ -306,7 +306,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-SSE2-NEXT: pandn %xmm0, %xmm1
; X86-SSE2-NEXT: por %xmm2, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v16i8:
@@ -322,7 +322,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pminsb %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX-LABEL: test_reduce_v16i8:
@@ -336,7 +336,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX-NEXT: retl
;
; X64-SSE2-LABEL: test_reduce_v16i8:
@@ -368,7 +368,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-SSE2-NEXT: pandn %xmm0, %xmm1
; X64-SSE2-NEXT: por %xmm2, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v16i8:
@@ -384,7 +384,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pminsb %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX-LABEL: test_reduce_v16i8:
@@ -398,7 +398,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX-NEXT: retq
%1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp slt <16 x i8> %a0, %1
@@ -750,7 +750,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-SSE2-NEXT: psrld $16, %xmm1
; X86-SSE2-NEXT: pminsw %xmm0, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v16i16:
@@ -761,7 +761,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: pxor %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v16i16:
@@ -773,7 +773,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -786,7 +786,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -801,7 +801,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-SSE2-NEXT: psrld $16, %xmm1
; X64-SSE2-NEXT: pminsw %xmm0, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v16i16:
@@ -812,7 +812,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: pxor %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v16i16:
@@ -824,7 +824,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -837,7 +837,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -850,7 +850,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -904,7 +904,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-SSE2-NEXT: pandn %xmm0, %xmm2
; X86-SSE2-NEXT: por %xmm1, %xmm2
; X86-SSE2-NEXT: movd %xmm2, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v32i8:
@@ -921,7 +921,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pminsb %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v32i8:
@@ -937,7 +937,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -954,7 +954,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -992,7 +992,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-SSE2-NEXT: pandn %xmm0, %xmm2
; X64-SSE2-NEXT: por %xmm1, %xmm2
; X64-SSE2-NEXT: movd %xmm2, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v32i8:
@@ -1009,7 +1009,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pminsb %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v32i8:
@@ -1025,7 +1025,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1042,7 +1042,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1059,7 +1059,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <32 x i8> %a0, <32 x i8> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -1554,7 +1554,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-SSE2-NEXT: psrld $16, %xmm1
; X86-SSE2-NEXT: pminsw %xmm0, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v32i16:
@@ -1567,7 +1567,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: pxor %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v32i16:
@@ -1582,7 +1582,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1596,7 +1596,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1613,7 +1613,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-SSE2-NEXT: psrld $16, %xmm1
; X64-SSE2-NEXT: pminsw %xmm0, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v32i16:
@@ -1626,7 +1626,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: pxor %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v32i16:
@@ -1641,7 +1641,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1655,7 +1655,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1670,7 +1670,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <32 x i16> %a0, <32 x i16> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -1737,7 +1737,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-SSE2-NEXT: pandn %xmm0, %xmm1
; X86-SSE2-NEXT: por %xmm2, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v64i8:
@@ -1756,7 +1756,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pminsb %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v64i8:
@@ -1775,7 +1775,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1793,7 +1793,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1841,7 +1841,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-SSE2-NEXT: pandn %xmm0, %xmm1
; X64-SSE2-NEXT: por %xmm2, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v64i8:
@@ -1860,7 +1860,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pminsb %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v64i8:
@@ -1879,7 +1879,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1897,7 +1897,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1916,7 +1916,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpminsb %zmm1, %zmm0, %zmm0
; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <64 x i8> %a0, <64 x i8> undef, <64 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
Modified: llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll (original)
+++ llvm/trunk/test/CodeGen/X86/horizontal-reduce-umax.ll Tue Nov 28 09:15:09 2017
@@ -254,7 +254,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X86-SSE2-NEXT: pandn %xmm0, %xmm3
; X86-SSE2-NEXT: por %xmm2, %xmm3
; X86-SSE2-NEXT: movd %xmm3, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v8i16:
@@ -264,7 +264,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: pxor %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX-LABEL: test_reduce_v8i16:
@@ -274,7 +274,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, %eax
-; X86-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX-NEXT: retl
;
; X64-SSE2-LABEL: test_reduce_v8i16:
@@ -308,7 +308,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X64-SSE2-NEXT: pandn %xmm0, %xmm3
; X64-SSE2-NEXT: por %xmm2, %xmm3
; X64-SSE2-NEXT: movd %xmm3, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v8i16:
@@ -318,7 +318,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: pxor %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX-LABEL: test_reduce_v8i16:
@@ -328,7 +328,7 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vmovd %xmm0, %eax
-; X64-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX-NEXT: retq
%1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp ugt <8 x i16> %a0, %1
@@ -357,7 +357,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-SSE2-NEXT: psrlw $8, %xmm0
; X86-SSE2-NEXT: pmaxub %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v16i8:
@@ -373,7 +373,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pmaxub %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX-LABEL: test_reduce_v16i8:
@@ -387,7 +387,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX-NEXT: retl
;
; X64-SSE2-LABEL: test_reduce_v16i8:
@@ -403,7 +403,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-SSE2-NEXT: psrlw $8, %xmm0
; X64-SSE2-NEXT: pmaxub %xmm1, %xmm0
; X64-SSE2-NEXT: movd %xmm0, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v16i8:
@@ -419,7 +419,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pmaxub %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX-LABEL: test_reduce_v16i8:
@@ -433,7 +433,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX-NEXT: retq
%1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp ugt <16 x i8> %a0, %1
@@ -863,7 +863,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-SSE2-NEXT: pandn %xmm0, %xmm1
; X86-SSE2-NEXT: por %xmm3, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v16i16:
@@ -874,7 +874,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: pxor %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v16i16:
@@ -886,7 +886,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -899,7 +899,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -942,7 +942,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-SSE2-NEXT: pandn %xmm0, %xmm1
; X64-SSE2-NEXT: por %xmm3, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v16i16:
@@ -953,7 +953,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: pxor %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v16i16:
@@ -965,7 +965,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -978,7 +978,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -991,7 +991,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -1025,7 +1025,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-SSE2-NEXT: psrlw $8, %xmm0
; X86-SSE2-NEXT: pmaxub %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v32i8:
@@ -1042,7 +1042,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pmaxub %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v32i8:
@@ -1058,7 +1058,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1075,7 +1075,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1093,7 +1093,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-SSE2-NEXT: psrlw $8, %xmm0
; X64-SSE2-NEXT: pmaxub %xmm1, %xmm0
; X64-SSE2-NEXT: movd %xmm0, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v32i8:
@@ -1110,7 +1110,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pmaxub %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v32i8:
@@ -1126,7 +1126,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1143,7 +1143,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1160,7 +1160,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <32 x i8> %a0, <32 x i8> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -1787,7 +1787,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-SSE2-NEXT: pandn %xmm0, %xmm2
; X86-SSE2-NEXT: por %xmm1, %xmm2
; X86-SSE2-NEXT: movd %xmm2, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v32i16:
@@ -1800,7 +1800,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: pxor %xmm1, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v32i16:
@@ -1815,7 +1815,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1829,7 +1829,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1888,7 +1888,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-SSE2-NEXT: pandn %xmm0, %xmm2
; X64-SSE2-NEXT: por %xmm1, %xmm2
; X64-SSE2-NEXT: movd %xmm2, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v32i16:
@@ -1901,7 +1901,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: pxor %xmm1, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v32i16:
@@ -1916,7 +1916,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1930,7 +1930,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1945,7 +1945,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <32 x i16> %a0, <32 x i16> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -1984,7 +1984,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-SSE2-NEXT: psrlw $8, %xmm0
; X86-SSE2-NEXT: pmaxub %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v64i8:
@@ -2003,7 +2003,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pmaxub %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v64i8:
@@ -2022,7 +2022,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -2040,7 +2040,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -2060,7 +2060,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-SSE2-NEXT: psrlw $8, %xmm0
; X64-SSE2-NEXT: pmaxub %xmm1, %xmm0
; X64-SSE2-NEXT: movd %xmm0, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v64i8:
@@ -2079,7 +2079,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pmaxub %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v64i8:
@@ -2098,7 +2098,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -2116,7 +2116,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -2135,7 +2135,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpmaxub %zmm1, %zmm0, %zmm0
; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <64 x i8> %a0, <64 x i8> undef, <64 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
Modified: llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll (original)
+++ llvm/trunk/test/CodeGen/X86/horizontal-reduce-umin.ll Tue Nov 28 09:15:09 2017
@@ -256,21 +256,21 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X86-SSE2-NEXT: pandn %xmm0, %xmm1
; X86-SSE2-NEXT: por %xmm3, %xmm1
; X86-SSE2-NEXT: movd %xmm1, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v8i16:
; X86-SSE42: ## BB#0:
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX-LABEL: test_reduce_v8i16:
; X86-AVX: ## BB#0:
; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, %eax
-; X86-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX-NEXT: retl
;
; X64-SSE2-LABEL: test_reduce_v8i16:
@@ -304,21 +304,21 @@ define i16 @test_reduce_v8i16(<8 x i16>
; X64-SSE2-NEXT: pandn %xmm0, %xmm1
; X64-SSE2-NEXT: por %xmm3, %xmm1
; X64-SSE2-NEXT: movd %xmm1, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v8i16:
; X64-SSE42: ## BB#0:
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX-LABEL: test_reduce_v8i16:
; X64-AVX: ## BB#0:
; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX-NEXT: vmovd %xmm0, %eax
-; X64-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX-NEXT: retq
%1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp ult <8 x i16> %a0, %1
@@ -347,7 +347,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-SSE2-NEXT: psrlw $8, %xmm0
; X86-SSE2-NEXT: pminub %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v16i8:
@@ -363,7 +363,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pminub %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX-LABEL: test_reduce_v16i8:
@@ -377,7 +377,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX-NEXT: retl
;
; X64-SSE2-LABEL: test_reduce_v16i8:
@@ -393,7 +393,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-SSE2-NEXT: psrlw $8, %xmm0
; X64-SSE2-NEXT: pminub %xmm1, %xmm0
; X64-SSE2-NEXT: movd %xmm0, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v16i8:
@@ -409,7 +409,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pminub %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX-LABEL: test_reduce_v16i8:
@@ -423,7 +423,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %
; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX-NEXT: retq
%1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp ult <16 x i8> %a0, %1
@@ -857,7 +857,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-SSE2-NEXT: pandn %xmm0, %xmm2
; X86-SSE2-NEXT: por %xmm4, %xmm2
; X86-SSE2-NEXT: movd %xmm2, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v16i16:
@@ -865,7 +865,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-SSE42-NEXT: pminuw %xmm1, %xmm0
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v16i16:
@@ -874,7 +874,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-AVX1-NEXT: vpminuw %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -884,7 +884,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X86-AVX2-NEXT: vpminuw %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -927,7 +927,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-SSE2-NEXT: pandn %xmm0, %xmm2
; X64-SSE2-NEXT: por %xmm4, %xmm2
; X64-SSE2-NEXT: movd %xmm2, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v16i16:
@@ -935,7 +935,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-SSE42-NEXT: pminuw %xmm1, %xmm0
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v16i16:
@@ -944,7 +944,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX1-NEXT: vpminuw %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -954,7 +954,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX2-NEXT: vpminuw %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -964,7 +964,7 @@ define i16 @test_reduce_v16i16(<16 x i16
; X64-AVX512-NEXT: vpminuw %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -998,7 +998,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-SSE2-NEXT: psrlw $8, %xmm0
; X86-SSE2-NEXT: pminub %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v32i8:
@@ -1015,7 +1015,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pminub %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v32i8:
@@ -1031,7 +1031,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1048,7 +1048,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1066,7 +1066,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-SSE2-NEXT: psrlw $8, %xmm0
; X64-SSE2-NEXT: pminub %xmm1, %xmm0
; X64-SSE2-NEXT: movd %xmm0, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v32i8:
@@ -1083,7 +1083,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pminub %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v32i8:
@@ -1099,7 +1099,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1116,7 +1116,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1133,7 +1133,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpminub %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <32 x i8> %a0, <32 x i8> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -1758,7 +1758,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-SSE2-NEXT: pandn %xmm0, %xmm4
; X86-SSE2-NEXT: por %xmm2, %xmm4
; X86-SSE2-NEXT: movd %xmm4, %eax
-; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v32i16:
@@ -1768,7 +1768,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-SSE42-NEXT: pminuw %xmm1, %xmm0
; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X86-SSE42-NEXT: movd %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v32i16:
@@ -1780,7 +1780,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-AVX1-NEXT: vpminuw %xmm2, %xmm0, %xmm0
; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1791,7 +1791,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X86-AVX2-NEXT: vpminuw %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1850,7 +1850,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-SSE2-NEXT: pandn %xmm0, %xmm4
; X64-SSE2-NEXT: por %xmm2, %xmm4
; X64-SSE2-NEXT: movd %xmm4, %eax
-; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v32i16:
@@ -1860,7 +1860,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-SSE42-NEXT: pminuw %xmm1, %xmm0
; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0
; X64-SSE42-NEXT: movd %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v32i16:
@@ -1872,7 +1872,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX1-NEXT: vpminuw %xmm2, %xmm0, %xmm0
; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1883,7 +1883,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX2-NEXT: vpminuw %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -1895,7 +1895,7 @@ define i16 @test_reduce_v32i16(<32 x i16
; X64-AVX512-NEXT: vpminuw %xmm1, %xmm0, %xmm0
; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0
; X64-AVX512-NEXT: vmovd %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <32 x i16> %a0, <32 x i16> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -1934,7 +1934,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-SSE2-NEXT: psrlw $8, %xmm0
; X86-SSE2-NEXT: pminub %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v64i8:
@@ -1953,7 +1953,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-SSE42-NEXT: psrlw $8, %xmm0
; X86-SSE42-NEXT: pminub %xmm1, %xmm0
; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-SSE42-NEXT: retl
;
; X86-AVX1-LABEL: test_reduce_v64i8:
@@ -1972,7 +1972,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1990,7 +1990,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X86-AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -2010,7 +2010,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-SSE2-NEXT: psrlw $8, %xmm0
; X64-SSE2-NEXT: pminub %xmm1, %xmm0
; X64-SSE2-NEXT: movd %xmm0, %eax
-; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v64i8:
@@ -2029,7 +2029,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-SSE42-NEXT: psrlw $8, %xmm0
; X64-SSE42-NEXT: pminub %xmm1, %xmm0
; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax
-; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-SSE42-NEXT: retq
;
; X64-AVX1-LABEL: test_reduce_v64i8:
@@ -2048,7 +2048,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -2066,7 +2066,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
;
@@ -2085,7 +2085,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %
; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1
; X64-AVX512-NEXT: vpminub %zmm1, %zmm0, %zmm0
; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax
-; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; X64-AVX512-NEXT: vzeroupper
; X64-AVX512-NEXT: retq
%1 = shufflevector <64 x i8> %a0, <64 x i8> undef, <64 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
Modified: llvm/trunk/test/CodeGen/X86/iabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/iabs.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/iabs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/iabs.ll Tue Nov 28 09:15:09 2017
@@ -41,7 +41,7 @@ define i16 @test_i16(i16 %a) nounwind {
; X86-NO-CMOV-NEXT: sarw $15, %cx
; X86-NO-CMOV-NEXT: addl %ecx, %eax
; X86-NO-CMOV-NEXT: xorl %ecx, %eax
-; X86-NO-CMOV-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; X86-NO-CMOV-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X86-NO-CMOV-NEXT: retl
;
; X86-CMOV-LABEL: test_i16:
Modified: llvm/trunk/test/CodeGen/X86/illegal-bitfield-loadstore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/illegal-bitfield-loadstore.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/illegal-bitfield-loadstore.ll (original)
+++ llvm/trunk/test/CodeGen/X86/illegal-bitfield-loadstore.ll Tue Nov 28 09:15:09 2017
@@ -116,7 +116,7 @@ define void @i56_or(i56* %a) {
; X64-NEXT: movzwl 4(%rdi), %eax
; X64-NEXT: movzbl 6(%rdi), %ecx
; X64-NEXT: movb %cl, 6(%rdi)
-; X64-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
+; X64-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<kill> %rcx<def>
; X64-NEXT: shll $16, %ecx
; X64-NEXT: orl %eax, %ecx
; X64-NEXT: shlq $32, %rcx
@@ -148,7 +148,7 @@ define void @i56_and_or(i56* %a) {
; X64-NEXT: movzwl 4(%rdi), %eax
; X64-NEXT: movzbl 6(%rdi), %ecx
; X64-NEXT: movb %cl, 6(%rdi)
-; X64-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
+; X64-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<kill> %rcx<def>
; X64-NEXT: shll $16, %ecx
; X64-NEXT: orl %eax, %ecx
; X64-NEXT: shlq $32, %rcx
@@ -186,7 +186,7 @@ define void @i56_insert_bit(i56* %a, i1
; X64-NEXT: movzwl 4(%rdi), %ecx
; X64-NEXT: movzbl 6(%rdi), %edx
; X64-NEXT: movb %dl, 6(%rdi)
-; X64-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<kill> %RDX<def>
+; X64-NEXT: # kill: %edx<def> %edx<kill> %rdx<kill> %rdx<def>
; X64-NEXT: shll $16, %edx
; X64-NEXT: orl %ecx, %edx
; X64-NEXT: shlq $32, %rdx
Modified: llvm/trunk/test/CodeGen/X86/imul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/imul.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/imul.ll (original)
+++ llvm/trunk/test/CodeGen/X86/imul.ll Tue Nov 28 09:15:09 2017
@@ -218,7 +218,7 @@ entry:
define i32 @test2(i32 %a) {
; X64-LABEL: test2:
; X64: # BB#0: # %entry
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: movl %edi, %eax
; X64-NEXT: shll $5, %eax
; X64-NEXT: leal (%rax,%rdi), %eax
@@ -239,7 +239,7 @@ entry:
define i32 @test3(i32 %a) {
; X64-LABEL: test3:
; X64: # BB#0: # %entry
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: movl %edi, %eax
; X64-NEXT: shll $5, %eax
; X64-NEXT: leal (%rax,%rdi), %eax
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll Tue Nov 28 09:15:09 2017
@@ -1,133 +1,133 @@
; RUN: not llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx -o /dev/null 2> %t
; RUN: FileCheck %s --input-file %t
-define <4 x float> @testXMM_1(<4 x float> %_xmm0, i32 %_l) {
+define <4 x float> @testxmm_1(<4 x float> %_xmm0, i32 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l, <4 x float> %_xmm0)
ret <4 x float> %0
}
-define <4 x float> @testXMM_2(<4 x float> %_xmm0, i32 %_l) {
+define <4 x float> @testxmm_2(<4 x float> %_xmm0, i32 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "movapd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l)
ret <4 x float> %0
}
-define <4 x float> @testXMM_3(<4 x float> %_xmm0, i32 %_l) {
+define <4 x float> @testxmm_3(<4 x float> %_xmm0, i32 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vmovapd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l)
ret <4 x float> %0
}
-define <4 x float> @testXMM_4(<4 x float> %_xmm0, i32 %_l) {
+define <4 x float> @testxmm_4(<4 x float> %_xmm0, i32 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vmpsadbw $$0, $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l, <4 x float> %_xmm0)
ret <4 x float> %0
}
-define <4 x float> @testXMM_5(<4 x float> %_xmm0, i32 %_l) {
+define <4 x float> @testxmm_5(<4 x float> %_xmm0, i32 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l, i32 %_l)
ret <4 x float> %0
}
-define i32 @testXMM_6(i32 returned %_l) {
+define i32 @testxmm_6(i32 returned %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
tail call void asm sideeffect "vmovd $0, %eax", "v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l)
ret i32 %_l
}
-define <4 x float> @testXMM_7(<4 x float> returned %_xmm0) {
+define <4 x float> @testxmm_7(<4 x float> returned %_xmm0) {
; CHECK: error: inline assembly requires more registers than available
entry:
tail call void asm sideeffect "vmovmskps $0, %eax", "v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0)
ret <4 x float> %_xmm0
}
-define i32 @testXMM_8(<4 x float> %_xmm0, i32 %_l) {
+define i32 @testxmm_8(<4 x float> %_xmm0, i32 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call i32 asm "vmulsd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l, <4 x float> %_xmm0)
ret i32 %0
}
-define <4 x float> @testXMM_9(<4 x float> %_xmm0, i32 %_l) {
+define <4 x float> @testxmm_9(<4 x float> %_xmm0, i32 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vorpd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l, <4 x float> %_xmm0)
ret <4 x float> %0
}
-define <4 x float> @testXMM_10(<4 x float> %_xmm0, i32 %_l) {
+define <4 x float> @testxmm_10(<4 x float> %_xmm0, i32 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "pabsb $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l)
ret <4 x float> %0
}
-define <4 x float> @testXMM_11(<4 x float> %_xmm0, i32 %_l) {
+define <4 x float> @testxmm_11(<4 x float> %_xmm0, i32 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vpabsd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l)
ret <4 x float> %0
}
-define <8 x float> @testYMM_1(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_1(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_2(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_2(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vmovapd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
ret <8 x float> %0
}
-define <8 x float> @testYMM_3(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_3(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_4(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_4(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vorpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vmulps $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_6(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_6(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vmulpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_7(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_7(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vmovups $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
ret <8 x float> %0
}
-define <8 x float> @testYMM_8(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_8(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vmovupd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-avx-v-constraint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-avx-v-constraint.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-avx-v-constraint.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-avx-v-constraint.ll Tue Nov 28 09:15:09 2017
@@ -1,133 +1,133 @@
; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -mattr +avx | FileCheck %s
; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -mattr +avx512f | FileCheck %s
-define <4 x float> @testXMM_1(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_1(<4 x float> %_xmm0, i64 %_l) {
; CHECK: vmovhlps %xmm1, %xmm0, %xmm0
entry:
%0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
ret <4 x float> %0
}
-define <4 x float> @testXMM_2(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_2(<4 x float> %_xmm0, i64 %_l) {
; CHECK: movapd %xmm0, %xmm0
entry:
%0 = tail call <4 x float> asm "movapd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l)
ret <4 x float> %0
}
-define <4 x float> @testXMM_3(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_3(<4 x float> %_xmm0, i64 %_l) {
; CHECK: vmovapd %xmm0, %xmm0
entry:
%0 = tail call <4 x float> asm "vmovapd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l)
ret <4 x float> %0
}
-define <4 x float> @testXMM_4(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_4(<4 x float> %_xmm0, i64 %_l) {
; CHECK: vmpsadbw $0, %xmm1, %xmm0, %xmm0
entry:
%0 = tail call <4 x float> asm "vmpsadbw $$0, $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
ret <4 x float> %0
}
-define <4 x float> @testXMM_5(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_5(<4 x float> %_xmm0, i64 %_l) {
; CHECK: vminpd %xmm0, %xmm0, %xmm0
entry:
%0 = tail call <4 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, i64 %_l)
ret <4 x float> %0
}
-define i64 @testXMM_6(i64 returned %_l) {
+define i64 @testxmm_6(i64 returned %_l) {
; CHECK: vmovd %xmm0, %eax
entry:
tail call void asm sideeffect "vmovd $0, %eax", "v,~{dirflag},~{fpsr},~{flags}"(i64 %_l)
ret i64 %_l
}
-define <4 x float> @testXMM_7(<4 x float> returned %_xmm0) {
+define <4 x float> @testxmm_7(<4 x float> returned %_xmm0) {
; CHECK: vmovmskps %xmm0, %eax
entry:
tail call void asm sideeffect "vmovmskps $0, %rax", "v,~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0)
ret <4 x float> %_xmm0
}
-define i64 @testXMM_8(<4 x float> %_xmm0, i64 %_l) {
+define i64 @testxmm_8(<4 x float> %_xmm0, i64 %_l) {
; CHECK: vmulsd %xmm1, %xmm0, %xmm0
entry:
%0 = tail call i64 asm "vmulsd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
ret i64 %0
}
-define <4 x float> @testXMM_9(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_9(<4 x float> %_xmm0, i64 %_l) {
; CHECK: vorpd %xmm1, %xmm0, %xmm0
entry:
%0 = tail call <4 x float> asm "vorpd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
ret <4 x float> %0
}
-define <4 x float> @testXMM_10(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_10(<4 x float> %_xmm0, i64 %_l) {
; CHECK: pabsb %xmm0, %xmm0
entry:
%0 = tail call <4 x float> asm "pabsb $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l)
ret <4 x float> %0
}
-define <4 x float> @testXMM_11(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_11(<4 x float> %_xmm0, i64 %_l) {
; CHECK: vpabsd %xmm0, %xmm0
entry:
%0 = tail call <4 x float> asm "vpabsd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l)
ret <4 x float> %0
}
-define <8 x float> @testYMM_1(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_1(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: vmovsldup %ymm0, %ymm0
entry:
%0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_2(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_2(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: vmovapd %ymm1, %ymm0
entry:
%0 = tail call <8 x float> asm "vmovapd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
ret <8 x float> %0
}
-define <8 x float> @testYMM_3(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_3(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: vminpd %ymm1, %ymm0, %ymm0
entry:
%0 = tail call <8 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_4(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_4(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: vorpd %ymm1, %ymm0, %ymm0
entry:
%0 = tail call <8 x float> asm "vorpd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: vmulps %ymm1, %ymm0, %ymm0
entry:
%0 = tail call <8 x float> asm "vmulps $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_6(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_6(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: vmulpd %ymm1, %ymm0, %ymm0
entry:
%0 = tail call <8 x float> asm "vmulpd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_7(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_7(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: vmovups %ymm1, %ymm0
entry:
%0 = tail call <8 x float> asm "vmovups $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
ret <8 x float> %0
}
-define <8 x float> @testYMM_8(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_8(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: vmovupd %ymm1, %ymm0
entry:
%0 = tail call <8 x float> asm "vmovupd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll Tue Nov 28 09:15:09 2017
@@ -1,13 +1,13 @@
; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -mattr +avx512f | FileCheck %s
-define <16 x float> @testZMM_1(<16 x float> %_zmm0, <16 x float> %_zmm1) {
+define <16 x float> @testzmm_1(<16 x float> %_zmm0, <16 x float> %_zmm1) {
entry:
; CHECK: vpternlogd $0, %zmm1, %zmm0, %zmm0
%0 = tail call <16 x float> asm "vpternlogd $$0, $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm0)
ret <16 x float> %0
}
-define <16 x float> @testZMM_2(<16 x float> %_zmm0, <16 x float> %_zmm1) {
+define <16 x float> @testzmm_2(<16 x float> %_zmm0, <16 x float> %_zmm1) {
entry:
; CHECK: vpabsq %zmm1, %zmm0
%0 = tail call <16 x float> asm "vpabsq $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1)
@@ -15,7 +15,7 @@ entry:
}
-define <16 x float> @testZMM_3(<16 x float> %_zmm0, <16 x float> %_zmm1) {
+define <16 x float> @testzmm_3(<16 x float> %_zmm0, <16 x float> %_zmm1) {
entry:
; CHECK: vpaddd %zmm1, %zmm1, %zmm0
%0 = tail call <16 x float> asm "vpaddd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm1)
@@ -23,7 +23,7 @@ entry:
}
-define <16 x float> @testZMM_4(<16 x float> %_zmm0, <16 x float> %_zmm1) {
+define <16 x float> @testzmm_4(<16 x float> %_zmm0, <16 x float> %_zmm1) {
entry:
; CHECK: vpaddq %zmm1, %zmm1, %zmm0
%0 = tail call <16 x float> asm "vpaddq $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm1)
@@ -31,7 +31,7 @@ entry:
}
-define <16 x float> @testZMM_5(<16 x float> %_zmm0, <16 x float> %_zmm1) {
+define <16 x float> @testzmm_5(<16 x float> %_zmm0, <16 x float> %_zmm1) {
entry:
; CHECK: vpandd %zmm1, %zmm1, %zmm0
%0 = tail call <16 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm1)
@@ -39,7 +39,7 @@ entry:
}
-define <16 x float> @testZMM_6(<16 x float> %_zmm0, <16 x float> %_zmm1) {
+define <16 x float> @testzmm_6(<16 x float> %_zmm0, <16 x float> %_zmm1) {
entry:
; CHECK: vpandnd %zmm1, %zmm1, %zmm0
%0 = tail call <16 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm1)
@@ -47,7 +47,7 @@ entry:
}
-define <16 x float> @testZMM_7(<16 x float> %_zmm0, <16 x float> %_zmm1) {
+define <16 x float> @testzmm_7(<16 x float> %_zmm0, <16 x float> %_zmm1) {
entry:
; CHECK: vpmaxsd %zmm1, %zmm1, %zmm0
%0 = tail call <16 x float> asm "vpmaxsd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm1)
@@ -55,7 +55,7 @@ entry:
}
-define <16 x float> @testZMM_8(<16 x float> %_zmm0, <16 x float> %_zmm1) {
+define <16 x float> @testzmm_8(<16 x float> %_zmm0, <16 x float> %_zmm1) {
entry:
; CHECK: vmovups %zmm1, %zmm0
%0 = tail call <16 x float> asm "vmovups $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1)
@@ -63,7 +63,7 @@ entry:
}
-define <16 x float> @testZMM_9(<16 x float> %_zmm0, <16 x float> %_zmm1) {
+define <16 x float> @testzmm_9(<16 x float> %_zmm0, <16 x float> %_zmm1) {
entry:
; CHECK: vmovupd %zmm1, %zmm0
%0 = tail call <16 x float> asm "vmovupd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1)
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll Tue Nov 28 09:15:09 2017
@@ -1,7 +1,7 @@
; RUN: not llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx512vl -o /dev/null 2> %t
; RUN: FileCheck %s --input-file %t
-define <4 x float> @testXMM_1(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_1(<4 x float> %_xmm0, i64 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
@@ -9,7 +9,7 @@ entry:
}
-define <4 x float> @testXMM_2(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_2(<4 x float> %_xmm0, i64 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vmovapd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i64 %_l)
@@ -17,7 +17,7 @@ entry:
}
-define <4 x float> @testXMM_3(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_3(<4 x float> %_xmm0, i64 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i64 %_l, i64 %_l)
@@ -25,7 +25,7 @@ entry:
}
-define i64 @testXMM_4(<4 x float> %_xmm0, i64 %_l) {
+define i64 @testxmm_4(<4 x float> %_xmm0, i64 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call i64 asm "vmulsd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
@@ -33,7 +33,7 @@ entry:
}
-define <4 x float> @testXMM_5(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_5(<4 x float> %_xmm0, i64 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vpabsq $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i64 %_l)
@@ -41,7 +41,7 @@ entry:
}
-define <4 x float> @testXMM_6(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_6(<4 x float> %_xmm0, i64 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0, i64 %_l)
@@ -49,7 +49,7 @@ entry:
}
-define <4 x float> @testXMM_7(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_7(<4 x float> %_xmm0, i64 %_l) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <4 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0, i64 %_l)
@@ -57,7 +57,7 @@ entry:
}
-define <8 x float> @testYMM_1(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_1(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
@@ -65,7 +65,7 @@ entry:
}
-define <8 x float> @testYMM_2(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_2(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vmovapd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
@@ -73,7 +73,7 @@ entry:
}
-define <8 x float> @testYMM_3(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_3(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm1)
@@ -81,7 +81,7 @@ entry:
}
-define <8 x float> @testYMM_4(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_4(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vpabsq $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
@@ -89,7 +89,7 @@ entry:
}
-define <8 x float> @testYMM_5(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_5(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
@@ -97,7 +97,7 @@ entry:
}
-define <8 x float> @testYMM_6(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_6(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
@@ -105,7 +105,7 @@ entry:
}
-define <8 x float> @testYMM_7(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_7(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vpminud $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
@@ -113,7 +113,7 @@ entry:
}
-define <8 x float> @testYMM_8(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_8(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vpmaxsd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
@@ -121,7 +121,7 @@ entry:
}
-define <8 x float> @testYMM_9(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_9(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vmovups $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
@@ -129,7 +129,7 @@ entry:
}
-define <8 x float> @testYMM_10(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_10(<8 x float> %_ymm0, <8 x float> %_ymm1) {
; CHECK: error: inline assembly requires more registers than available
entry:
%0 = tail call <8 x float> asm "vmovupd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll Tue Nov 28 09:15:09 2017
@@ -1,118 +1,118 @@
; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -mattr +avx512vl | FileCheck %s
-define <4 x float> @testXMM_1(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_1(<4 x float> %_xmm0, i64 %_l) {
entry:
; CHECK: vmovhlps %xmm17, %xmm16, %xmm16
%0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
ret <4 x float> %0
}
-define <4 x float> @testXMM_2(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_2(<4 x float> %_xmm0, i64 %_l) {
entry:
; CHECK: vmovapd %xmm16, %xmm16
%0 = tail call <4 x float> asm "vmovapd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l)
ret <4 x float> %0
}
-define <4 x float> @testXMM_3(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_3(<4 x float> %_xmm0, i64 %_l) {
entry:
; CHECK: vminpd %xmm16, %xmm16, %xmm16
%0 = tail call <4 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, i64 %_l)
ret <4 x float> %0
}
-define i64 @testXMM_4(<4 x float> %_xmm0, i64 %_l) {
+define i64 @testxmm_4(<4 x float> %_xmm0, i64 %_l) {
entry:
; CHECK: vmulsd %xmm17, %xmm16, %xmm16
%0 = tail call i64 asm "vmulsd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
ret i64 %0
}
-define <4 x float> @testXMM_5(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_5(<4 x float> %_xmm0, i64 %_l) {
entry:
; CHECK: vpabsq %xmm16, %xmm16
%0 = tail call <4 x float> asm "vpabsq $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l)
ret <4 x float> %0
}
-define <4 x float> @testXMM_6(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_6(<4 x float> %_xmm0, i64 %_l) {
entry:
; CHECK: vpandd %xmm16, %xmm17, %xmm16
%0 = tail call <4 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0, i64 %_l)
ret <4 x float> %0
}
-define <4 x float> @testXMM_7(<4 x float> %_xmm0, i64 %_l) {
+define <4 x float> @testxmm_7(<4 x float> %_xmm0, i64 %_l) {
entry:
; CHECK: vpandnd %xmm16, %xmm17, %xmm16
%0 = tail call <4 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0, i64 %_l)
ret <4 x float> %0
}
-define <8 x float> @testYMM_1(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_1(<8 x float> %_ymm0, <8 x float> %_ymm1) {
entry:
; CHECK: vmovsldup %ymm16, %ymm16
%0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
ret <8 x float> %0
}
-define <8 x float> @testYMM_2(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_2(<8 x float> %_ymm0, <8 x float> %_ymm1) {
entry:
; CHECK: vmovapd %ymm16, %ymm16
%0 = tail call <8 x float> asm "vmovapd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
ret <8 x float> %0
}
-define <8 x float> @testYMM_3(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_3(<8 x float> %_ymm0, <8 x float> %_ymm1) {
entry:
; CHECK: vminpd %ymm16, %ymm16, %ymm16
%0 = tail call <8 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm1)
ret <8 x float> %0
}
-define <8 x float> @testYMM_4(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_4(<8 x float> %_ymm0, <8 x float> %_ymm1) {
entry:
; CHECK: vpabsq %ymm16, %ymm16
%0 = tail call <8 x float> asm "vpabsq $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
ret <8 x float> %0
}
-define <8 x float> @testYMM_5(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_5(<8 x float> %_ymm0, <8 x float> %_ymm1) {
entry:
; CHECK: vpandd %ymm16, %ymm17, %ymm16
%0 = tail call <8 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_6(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_6(<8 x float> %_ymm0, <8 x float> %_ymm1) {
entry:
; CHECK: vpandnd %ymm16, %ymm17, %ymm16
%0 = tail call <8 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_7(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_7(<8 x float> %_ymm0, <8 x float> %_ymm1) {
entry:
; CHECK: vpminud %ymm16, %ymm17, %ymm16
%0 = tail call <8 x float> asm "vpminud $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_8(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_8(<8 x float> %_ymm0, <8 x float> %_ymm1) {
entry:
; CHECK: vpmaxsd %ymm16, %ymm17, %ymm16
%0 = tail call <8 x float> asm "vpmaxsd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
ret <8 x float> %0
}
-define <8 x float> @testYMM_9(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_9(<8 x float> %_ymm0, <8 x float> %_ymm1) {
entry:
; CHECK: vmovups %ymm16, %ymm16
%0 = tail call <8 x float> asm "vmovups $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
ret <8 x float> %0
}
-define <8 x float> @testYMM_10(<8 x float> %_ymm0, <8 x float> %_ymm1) {
+define <8 x float> @testymm_10(<8 x float> %_ymm0, <8 x float> %_ymm1) {
entry:
; CHECK: vmovupd %ymm16, %ymm16
%0 = tail call <8 x float> asm "vmovupd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll Tue Nov 28 09:15:09 2017
@@ -437,9 +437,9 @@ entry:
; inline-asm instruction and the ST register was live across another
; inline-asm instruction.
;
-; INLINEASM <es:frndint> [sideeffect] [attdialect], $0:[regdef], %ST0<imp-def,tied5>, $1:[reguse tiedto:$0], %ST0<tied3>, $2:[clobber], %EFLAGS<earlyclobber,imp-def,dead>
-; INLINEASM <es:fldcw $0> [sideeffect] [mayload] [attdialect], $0:[mem], %EAX<undef>, 1, %noreg, 0, %noreg, $1:[clobber], %EFLAGS<earlyclobber,imp-def,dead>
-; %FP0<def> = COPY %ST0
+; INLINEASM <es:frndint> [sideeffect] [attdialect], $0:[regdef], %st0<imp-def,tied5>, $1:[reguse tiedto:$0], %st0<tied3>, $2:[clobber], %eflags<earlyclobber,imp-def,dead>
+; INLINEASM <es:fldcw $0> [sideeffect] [mayload] [attdialect], $0:[mem], %eax<undef>, 1, %noreg, 0, %noreg, $1:[clobber], %eflags<earlyclobber,imp-def,dead>
+; %fp0<def> = COPY %st0
%struct.fpu_t = type { [8 x x86_fp80], x86_fp80, %struct.anon1, %struct.anon2, i32, i8, [15 x i8] }
%struct.anon1 = type { i32, i32, i32 }
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-stack-realign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-stack-realign.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-stack-realign.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-stack-realign.ll Tue Nov 28 09:15:09 2017
@@ -1,6 +1,6 @@
; RUN: not llc -mtriple=i686-pc-win32 < %s 2>&1 | FileCheck %s
-; FIXME: This is miscompiled due to our unconditional use of ESI as the base
+; FIXME: This is miscompiled due to our unconditional use of esi as the base
; pointer.
; XFAIL: *
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll Tue Nov 28 09:15:09 2017
@@ -14,7 +14,7 @@ entry:
; CHECK-DAG: movl 4(%esp), %eax
; CHECK: ## InlineAsm Start
; CHECK: ## InlineAsm End
-; Everything is set up in EAX:EDX, return immediately.
+; Everything is set up in eax:edx, return immediately.
; CHECK-NEXT: retl
; The tied operands are not necessarily in the same order as the defs.
Modified: llvm/trunk/test/CodeGen/X86/lea-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea-3.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lea-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lea-3.ll Tue Nov 28 09:15:09 2017
@@ -36,25 +36,25 @@ define i64 @test2(i64 %a) {
define i32 @test(i32 %a) {
; LNX1-LABEL: test:
; LNX1: # BB#0:
-; LNX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; LNX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; LNX1-NEXT: leal (%rdi,%rdi,2), %eax
; LNX1-NEXT: retq
;
; LNX2-LABEL: test:
; LNX2: # BB#0:
-; LNX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; LNX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; LNX2-NEXT: leal (%rdi,%rdi,2), %eax
; LNX2-NEXT: retq
;
; NACL-LABEL: test:
; NACL: # BB#0:
-; NACL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; NACL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; NACL-NEXT: leal (%rdi,%rdi,2), %eax
; NACL-NEXT: retq
;
; WIN-LABEL: test:
; WIN: # BB#0:
-; WIN-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def>
+; WIN-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def>
; WIN-NEXT: leal (%rcx,%rcx,2), %eax
; WIN-NEXT: retq
%tmp2 = mul i32 %a, 3
Modified: llvm/trunk/test/CodeGen/X86/lea-opt-cse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea-opt-cse3.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lea-opt-cse3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lea-opt-cse3.ll Tue Nov 28 09:15:09 2017
@@ -5,8 +5,8 @@
define i32 @foo(i32 %a, i32 %b) local_unnamed_addr #0 {
; X64-LABEL: foo:
; X64: # BB#0: # %entry
-; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: leal 4(%rdi,%rsi,2), %ecx
; X64-NEXT: leal 4(%rdi,%rsi,4), %eax
; X64-NEXT: imull %ecx, %eax
@@ -33,8 +33,8 @@ entry:
define i32 @foo1(i32 %a, i32 %b) local_unnamed_addr #0 {
; X64-LABEL: foo1:
; X64: # BB#0: # %entry
-; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: leal 4(%rdi,%rsi,4), %ecx
; X64-NEXT: leal 4(%rdi,%rsi,8), %eax
; X64-NEXT: imull %ecx, %eax
@@ -61,8 +61,8 @@ entry:
define i32 @foo1_mult_basic_blocks(i32 %a, i32 %b) local_unnamed_addr #0 {
; X64-LABEL: foo1_mult_basic_blocks:
; X64: # BB#0: # %entry
-; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: leal 4(%rdi,%rsi,4), %ecx
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: cmpl $10, %ecx
@@ -113,8 +113,8 @@ exit:
define i32 @foo1_mult_basic_blocks_illegal_scale(i32 %a, i32 %b) local_unnamed_addr #0 {
; X64-LABEL: foo1_mult_basic_blocks_illegal_scale:
; X64: # BB#0: # %entry
-; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: leal 4(%rdi,%rsi,2), %ecx
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: cmpl $10, %ecx
Modified: llvm/trunk/test/CodeGen/X86/lea32-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea32-schedule.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lea32-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lea32-schedule.ll Tue Nov 28 09:15:09 2017
@@ -14,13 +14,13 @@
define i32 @test_lea_offset(i32) {
; GENERIC-LABEL: test_lea_offset:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal -24(%rdi), %eax # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_lea_offset:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal -24(%rdi), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -32,43 +32,43 @@ define i32 @test_lea_offset(i32) {
;
; SLM-LABEL: test_lea_offset:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal -24(%rdi), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_offset:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal -24(%rdi), %eax # sched: [1:0.50]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_lea_offset:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal -24(%rdi), %eax # sched: [1:0.50]
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_lea_offset:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal -24(%rdi), %eax # sched: [1:0.50]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_lea_offset:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal -24(%rdi), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_offset:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal -24(%rdi), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_offset:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal -24(%rdi), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%2 = add nsw i32 %0, -24
@@ -78,13 +78,13 @@ define i32 @test_lea_offset(i32) {
define i32 @test_lea_offset_big(i32) {
; GENERIC-LABEL: test_lea_offset_big:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_lea_offset_big:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal 1024(%rdi), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -96,43 +96,43 @@ define i32 @test_lea_offset_big(i32) {
;
; SLM-LABEL: test_lea_offset_big:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal 1024(%rdi), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_offset_big:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_lea_offset_big:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50]
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_lea_offset_big:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_lea_offset_big:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_offset_big:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_offset_big:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal 1024(%rdi), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%2 = add nsw i32 %0, 1024
@@ -143,15 +143,15 @@ define i32 @test_lea_offset_big(i32) {
define i32 @test_lea_add(i32, i32) {
; GENERIC-LABEL: test_lea_add:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_lea_add:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal (%rdi,%rsi), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -163,50 +163,50 @@ define i32 @test_lea_add(i32, i32) {
;
; SLM-LABEL: test_lea_add:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal (%rdi,%rsi), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_add:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_lea_add:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_lea_add:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_lea_add:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_add:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%3 = add nsw i32 %1, %0
@@ -216,16 +216,16 @@ define i32 @test_lea_add(i32, i32) {
define i32 @test_lea_add_offset(i32, i32) {
; GENERIC-LABEL: test_lea_add_offset:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; GENERIC-NEXT: addl $16, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_lea_add_offset:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal 16(%rdi,%rsi), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -237,54 +237,54 @@ define i32 @test_lea_add_offset(i32, i32
;
; SLM-LABEL: test_lea_add_offset:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal 16(%rdi,%rsi), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_add_offset:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; SANDY-NEXT: addl $16, %eax # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_lea_add_offset:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; HASWELL-NEXT: addl $16, %eax # sched: [1:0.25]
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_lea_add_offset:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; BROADWELL-NEXT: addl $16, %eax # sched: [1:0.25]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_lea_add_offset:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $16, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_offset:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal 16(%rdi,%rsi), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_add_offset:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal 16(%rdi,%rsi), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%3 = add i32 %0, 16
@@ -295,8 +295,8 @@ define i32 @test_lea_add_offset(i32, i32
define i32 @test_lea_add_offset_big(i32, i32) {
; GENERIC-LABEL: test_lea_add_offset_big:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; GENERIC-NEXT: addl $-4096, %eax # imm = 0xF000
; GENERIC-NEXT: # sched: [1:0.33]
@@ -304,8 +304,8 @@ define i32 @test_lea_add_offset_big(i32,
;
; ATOM-LABEL: test_lea_add_offset_big:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal -4096(%rdi,%rsi), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -317,15 +317,15 @@ define i32 @test_lea_add_offset_big(i32,
;
; SLM-LABEL: test_lea_add_offset_big:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal -4096(%rdi,%rsi), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_add_offset_big:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; SANDY-NEXT: addl $-4096, %eax # imm = 0xF000
; SANDY-NEXT: # sched: [1:0.33]
@@ -333,8 +333,8 @@ define i32 @test_lea_add_offset_big(i32,
;
; HASWELL-LABEL: test_lea_add_offset_big:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; HASWELL-NEXT: addl $-4096, %eax # imm = 0xF000
; HASWELL-NEXT: # sched: [1:0.25]
@@ -342,8 +342,8 @@ define i32 @test_lea_add_offset_big(i32,
;
; BROADWELL-LABEL: test_lea_add_offset_big:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; BROADWELL-NEXT: addl $-4096, %eax # imm = 0xF000
; BROADWELL-NEXT: # sched: [1:0.25]
@@ -351,8 +351,8 @@ define i32 @test_lea_add_offset_big(i32,
;
; SKYLAKE-LABEL: test_lea_add_offset_big:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $-4096, %eax # imm = 0xF000
; SKYLAKE-NEXT: # sched: [1:0.25]
@@ -360,15 +360,15 @@ define i32 @test_lea_add_offset_big(i32,
;
; BTVER2-LABEL: test_lea_add_offset_big:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal -4096(%rdi,%rsi), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_add_offset_big:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal -4096(%rdi,%rsi), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%3 = add i32 %0, -4096
@@ -379,13 +379,13 @@ define i32 @test_lea_add_offset_big(i32,
define i32 @test_lea_mul(i32) {
; GENERIC-LABEL: test_lea_mul:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_lea_mul:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -397,43 +397,43 @@ define i32 @test_lea_mul(i32) {
;
; SLM-LABEL: test_lea_mul:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_mul:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_lea_mul:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_lea_mul:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_lea_mul:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_mul:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_mul:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%2 = mul nsw i32 %0, 3
@@ -443,14 +443,14 @@ define i32 @test_lea_mul(i32) {
define i32 @test_lea_mul_offset(i32) {
; GENERIC-LABEL: test_lea_mul_offset:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; GENERIC-NEXT: addl $-32, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_lea_mul_offset:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal -32(%rdi,%rdi,2), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -462,47 +462,47 @@ define i32 @test_lea_mul_offset(i32) {
;
; SLM-LABEL: test_lea_mul_offset:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal -32(%rdi,%rdi,2), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_mul_offset:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; SANDY-NEXT: addl $-32, %eax # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_lea_mul_offset:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; HASWELL-NEXT: addl $-32, %eax # sched: [1:0.25]
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_lea_mul_offset:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; BROADWELL-NEXT: addl $-32, %eax # sched: [1:0.25]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_lea_mul_offset:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $-32, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_mul_offset:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal -32(%rdi,%rdi,2), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_mul_offset:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal -32(%rdi,%rdi,2), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%2 = mul nsw i32 %0, 3
@@ -513,7 +513,7 @@ define i32 @test_lea_mul_offset(i32) {
define i32 @test_lea_mul_offset_big(i32) {
; GENERIC-LABEL: test_lea_mul_offset_big:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50]
; GENERIC-NEXT: addl $10000, %eax # imm = 0x2710
; GENERIC-NEXT: # sched: [1:0.33]
@@ -521,7 +521,7 @@ define i32 @test_lea_mul_offset_big(i32)
;
; ATOM-LABEL: test_lea_mul_offset_big:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal 10000(%rdi,%rdi,8), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -533,13 +533,13 @@ define i32 @test_lea_mul_offset_big(i32)
;
; SLM-LABEL: test_lea_mul_offset_big:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal 10000(%rdi,%rdi,8), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_mul_offset_big:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50]
; SANDY-NEXT: addl $10000, %eax # imm = 0x2710
; SANDY-NEXT: # sched: [1:0.33]
@@ -547,7 +547,7 @@ define i32 @test_lea_mul_offset_big(i32)
;
; HASWELL-LABEL: test_lea_mul_offset_big:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50]
; HASWELL-NEXT: addl $10000, %eax # imm = 0x2710
; HASWELL-NEXT: # sched: [1:0.25]
@@ -555,7 +555,7 @@ define i32 @test_lea_mul_offset_big(i32)
;
; BROADWELL-LABEL: test_lea_mul_offset_big:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50]
; BROADWELL-NEXT: addl $10000, %eax # imm = 0x2710
; BROADWELL-NEXT: # sched: [1:0.25]
@@ -563,7 +563,7 @@ define i32 @test_lea_mul_offset_big(i32)
;
; SKYLAKE-LABEL: test_lea_mul_offset_big:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $10000, %eax # imm = 0x2710
; SKYLAKE-NEXT: # sched: [1:0.25]
@@ -571,13 +571,13 @@ define i32 @test_lea_mul_offset_big(i32)
;
; BTVER2-LABEL: test_lea_mul_offset_big:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal 10000(%rdi,%rdi,8), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_mul_offset_big:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal 10000(%rdi,%rdi,8), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%2 = mul nsw i32 %0, 9
@@ -588,15 +588,15 @@ define i32 @test_lea_mul_offset_big(i32)
define i32 @test_lea_add_scale(i32, i32) {
; GENERIC-LABEL: test_lea_add_scale:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_lea_add_scale:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -608,50 +608,50 @@ define i32 @test_lea_add_scale(i32, i32)
;
; SLM-LABEL: test_lea_add_scale:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_add_scale:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_lea_add_scale:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50]
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_lea_add_scale:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_lea_add_scale:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_scale:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_add_scale:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%3 = shl i32 %1, 1
@@ -662,16 +662,16 @@ define i32 @test_lea_add_scale(i32, i32)
define i32 @test_lea_add_scale_offset(i32, i32) {
; GENERIC-LABEL: test_lea_add_scale_offset:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50]
; GENERIC-NEXT: addl $96, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_lea_add_scale_offset:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal 96(%rdi,%rsi,4), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -683,54 +683,54 @@ define i32 @test_lea_add_scale_offset(i3
;
; SLM-LABEL: test_lea_add_scale_offset:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal 96(%rdi,%rsi,4), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_add_scale_offset:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50]
; SANDY-NEXT: addl $96, %eax # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_lea_add_scale_offset:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50]
; HASWELL-NEXT: addl $96, %eax # sched: [1:0.25]
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_lea_add_scale_offset:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50]
; BROADWELL-NEXT: addl $96, %eax # sched: [1:0.25]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_lea_add_scale_offset:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $96, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_scale_offset:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal 96(%rdi,%rsi,4), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_add_scale_offset:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal 96(%rdi,%rsi,4), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%3 = shl i32 %1, 2
@@ -742,8 +742,8 @@ define i32 @test_lea_add_scale_offset(i3
define i32 @test_lea_add_scale_offset_big(i32, i32) {
; GENERIC-LABEL: test_lea_add_scale_offset_big:
; GENERIC: # BB#0:
-; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; GENERIC-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50]
; GENERIC-NEXT: addl $-1200, %eax # imm = 0xFB50
; GENERIC-NEXT: # sched: [1:0.33]
@@ -751,8 +751,8 @@ define i32 @test_lea_add_scale_offset_bi
;
; ATOM-LABEL: test_lea_add_scale_offset_big:
; ATOM: # BB#0:
-; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ATOM-NEXT: leal -1200(%rdi,%rsi,8), %eax # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50]
@@ -764,15 +764,15 @@ define i32 @test_lea_add_scale_offset_bi
;
; SLM-LABEL: test_lea_add_scale_offset_big:
; SLM: # BB#0:
-; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SLM-NEXT: leal -1200(%rdi,%rsi,8), %eax # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_lea_add_scale_offset_big:
; SANDY: # BB#0:
-; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SANDY-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50]
; SANDY-NEXT: addl $-1200, %eax # imm = 0xFB50
; SANDY-NEXT: # sched: [1:0.33]
@@ -780,8 +780,8 @@ define i32 @test_lea_add_scale_offset_bi
;
; HASWELL-LABEL: test_lea_add_scale_offset_big:
; HASWELL: # BB#0:
-; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; HASWELL-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50]
; HASWELL-NEXT: addl $-1200, %eax # imm = 0xFB50
; HASWELL-NEXT: # sched: [1:0.25]
@@ -789,8 +789,8 @@ define i32 @test_lea_add_scale_offset_bi
;
; BROADWELL-LABEL: test_lea_add_scale_offset_big:
; BROADWELL: # BB#0:
-; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BROADWELL-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50]
; BROADWELL-NEXT: addl $-1200, %eax # imm = 0xFB50
; BROADWELL-NEXT: # sched: [1:0.25]
@@ -798,8 +798,8 @@ define i32 @test_lea_add_scale_offset_bi
;
; SKYLAKE-LABEL: test_lea_add_scale_offset_big:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; SKYLAKE-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $-1200, %eax # imm = 0xFB50
; SKYLAKE-NEXT: # sched: [1:0.25]
@@ -807,15 +807,15 @@ define i32 @test_lea_add_scale_offset_bi
;
; BTVER2-LABEL: test_lea_add_scale_offset_big:
; BTVER2: # BB#0:
-; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; BTVER2-NEXT: leal -1200(%rdi,%rsi,8), %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_lea_add_scale_offset_big:
; ZNVER1: # BB#0:
-; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; ZNVER1-NEXT: leal -1200(%rdi,%rsi,8), %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%3 = shl i32 %1, 3
Modified: llvm/trunk/test/CodeGen/X86/loop-search.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/loop-search.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/loop-search.ll (original)
+++ llvm/trunk/test/CodeGen/X86/loop-search.ll Tue Nov 28 09:15:09 2017
@@ -25,15 +25,15 @@ define zeroext i1 @search(i32 %needle, i
; ### FIXME: BB#3 and LBB0_1 should be merged
; CHECK-NEXT: ## BB#3:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
; CHECK-NEXT: LBB0_1:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
; CHECK-NEXT: LBB0_6:
; CHECK-NEXT: movb $1, %al
-; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: retq
entry:
%cmp5 = icmp sgt i32 %count, 0
Modified: llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll Tue Nov 28 09:15:09 2017
@@ -13,7 +13,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a
; GENERIC-NEXT: lzcntw (%rsi), %cx
; GENERIC-NEXT: lzcntw %di, %ax
; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33]
-; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_ctlz_i16:
@@ -21,7 +21,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a
; HASWELL-NEXT: lzcntw (%rsi), %cx # sched: [3:1.00]
; HASWELL-NEXT: lzcntw %di, %ax # sched: [3:1.00]
; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; HASWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; HASWELL-NEXT: retq # sched: [2:1.00]
;
; BROADWELL-LABEL: test_ctlz_i16:
@@ -29,7 +29,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a
; BROADWELL-NEXT: lzcntw (%rsi), %cx # sched: [8:1.00]
; BROADWELL-NEXT: lzcntw %di, %ax # sched: [3:1.00]
; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; BROADWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_ctlz_i16:
@@ -37,7 +37,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a
; SKYLAKE-NEXT: lzcntw (%rsi), %cx # sched: [8:1.00]
; SKYLAKE-NEXT: lzcntw %di, %ax # sched: [3:1.00]
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKYLAKE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_ctlz_i16:
@@ -45,7 +45,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a
; BTVER2-NEXT: lzcntw (%rsi), %cx
; BTVER2-NEXT: lzcntw %di, %ax
; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
-; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; BTVER2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_ctlz_i16:
@@ -53,7 +53,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a
; ZNVER1-NEXT: lzcntw (%rsi), %cx # sched: [6:0.50]
; ZNVER1-NEXT: lzcntw %di, %ax # sched: [2:0.25]
; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; ZNVER1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load i16, i16 *%a1
%2 = tail call i16 @llvm.ctlz.i16( i16 %1, i1 false )
Modified: llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll Tue Nov 28 09:15:09 2017
@@ -84,7 +84,7 @@ define i16 @test_zext_cmp3(i16 %a, i16 %
; ALL-NEXT: sete %cl
; ALL-NEXT: orb %al, %cl
; ALL-NEXT: movzbl %cl, %eax
-; ALL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; ALL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; ALL-NEXT: retq
%cmp = icmp eq i16 %a, 0
%cmp1 = icmp eq i16 %b, 0
@@ -128,7 +128,7 @@ define i32 @test_zext_cmp5(i64 %a, i64 %
; FASTLZCNT-NEXT: lzcntq %rsi, %rax
; FASTLZCNT-NEXT: orl %ecx, %eax
; FASTLZCNT-NEXT: shrl $6, %eax
-; FASTLZCNT-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
+; FASTLZCNT-NEXT: # kill: %eax<def> %eax<kill> %rax<kill>
; FASTLZCNT-NEXT: retq
;
; NOFASTLZCNT-LABEL: test_zext_cmp5:
@@ -267,7 +267,7 @@ define i32 @test_zext_cmp9(i32 %a, i64 %
; FASTLZCNT-NEXT: shrl $5, %ecx
; FASTLZCNT-NEXT: shrl $6, %eax
; FASTLZCNT-NEXT: orl %ecx, %eax
-; FASTLZCNT-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
+; FASTLZCNT-NEXT: # kill: %eax<def> %eax<kill> %rax<kill>
; FASTLZCNT-NEXT: retq
;
; NOFASTLZCNT-LABEL: test_zext_cmp9:
Modified: llvm/trunk/test/CodeGen/X86/machine-cse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-cse.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/machine-cse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/machine-cse.ll Tue Nov 28 09:15:09 2017
@@ -50,8 +50,8 @@ declare void @printf(...) nounwind
define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
; CHECK-LABEL: commute:
; CHECK: # BB#0: # %entry
-; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
-; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
+; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; CHECK-NEXT: leal -1(%rdi), %eax
; CHECK-NEXT: cmpl $2, %eax
; CHECK-NEXT: ja .LBB1_4
@@ -64,7 +64,7 @@ define void @commute(i32 %test_case, i32
; CHECK-NEXT: imull %edi, %esi
; CHECK-NEXT: leal (%rsi,%rsi,2), %esi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<kill>
+; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<kill>
; CHECK-NEXT: callq printf
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: .p2align 4, 0x90
Modified: llvm/trunk/test/CodeGen/X86/machine-outliner-tailcalls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-outliner-tailcalls.ll?rev=319187&r1=319186&r2=319187&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/machine-outliner-tailcalls.ll (original)
+++ llvm/trunk/test/CodeGen/X86/machine-outliner-tailcalls.ll Tue Nov 28 09:15:09 2017
@@ -32,4 +32,4 @@ attributes #0 = { noredzone nounwind ssp
; CHECK-LABEL: l_OUTLINED_FUNCTION_0:
; CHECK: movl $0, (%rax)
; CHECK-NEXT: movl $1, %edi
-; CHECK-NEXT: jmp _ext
\ No newline at end of file
+; CHECK-NEXT: jmp _ext
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