[llvm] r319065 - [X86][AVX512] Tag AVX512 PACKSS/PACKUS/PMADDWD/PMADDUBSW instructions with SSE_PACK/SSE_PMADD schedule classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 27 10:14:18 PST 2017
Author: rksimon
Date: Mon Nov 27 10:14:18 2017
New Revision: 319065
URL: http://llvm.org/viewvc/llvm-project?rev=319065&view=rev
Log:
[X86][AVX512] Tag AVX512 PACKSS/PACKUS/PMADDWD/PMADDUBSW instructions with SSE_PACK/SSE_PMADD schedule classes
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=319065&r1=319064&r2=319065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Mon Nov 27 10:14:18 2017
@@ -4313,7 +4313,8 @@ defm VPMULTISHIFTQB : avx512_binop_all<0
X86multishift, HasVBMI, 0>, T8PD;
multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
- X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
+ X86VectorVTInfo _Src, X86VectorVTInfo _Dst,
+ OpndItins itins> {
defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
(ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
OpcodeStr,
@@ -4321,57 +4322,60 @@ multiclass avx512_packs_rmb<bits<8> opc,
"$src1, ${src2}"##_Src.BroadcastStr,
(_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
(_Src.VT (X86VBroadcast
- (_Src.ScalarLdFrag addr:$src2))))))>,
- EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
+ (_Src.ScalarLdFrag addr:$src2)))))),
+ itins.rm>, EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>,
+ Sched<[itins.Sched.Folded, ReadAfterLd]>;
}
multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
SDNode OpNode,X86VectorVTInfo _Src,
- X86VectorVTInfo _Dst, bit IsCommutable = 0> {
+ X86VectorVTInfo _Dst, OpndItins itins,
+ bit IsCommutable = 0> {
defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
(ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
"$src2, $src1","$src1, $src2",
(_Dst.VT (OpNode
(_Src.VT _Src.RC:$src1),
(_Src.VT _Src.RC:$src2))),
- NoItinerary, IsCommutable>,
- EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
+ itins.rr, IsCommutable>,
+ EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V, Sched<[itins.Sched]>;
defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
(ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
"$src2, $src1", "$src1, $src2",
(_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
- (bitconvert (_Src.LdFrag addr:$src2))))>,
- EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
+ (bitconvert (_Src.LdFrag addr:$src2)))), itins.rm>,
+ EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>,
+ Sched<[itins.Sched.Folded, ReadAfterLd]>;
}
multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
SDNode OpNode> {
let Predicates = [HasBWI] in
defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
- v32i16_info>,
+ v32i16_info, SSE_PACK>,
avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
- v32i16_info>, EVEX_V512;
+ v32i16_info, SSE_PACK>, EVEX_V512;
let Predicates = [HasBWI, HasVLX] in {
defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
- v16i16x_info>,
+ v16i16x_info, SSE_PACK>,
avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
- v16i16x_info>, EVEX_V256;
+ v16i16x_info, SSE_PACK>, EVEX_V256;
defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
- v8i16x_info>,
+ v8i16x_info, SSE_PACK>,
avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
- v8i16x_info>, EVEX_V128;
+ v8i16x_info, SSE_PACK>, EVEX_V128;
}
}
multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
SDNode OpNode> {
let Predicates = [HasBWI] in
defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
- v64i8_info>, EVEX_V512, VEX_WIG;
+ v64i8_info, SSE_PACK>, EVEX_V512, VEX_WIG;
let Predicates = [HasBWI, HasVLX] in {
defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
- v32i8x_info>, EVEX_V256, VEX_WIG;
+ v32i8x_info, SSE_PACK>, EVEX_V256, VEX_WIG;
defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
- v16i8x_info>, EVEX_V128, VEX_WIG;
+ v16i8x_info, SSE_PACK>, EVEX_V128, VEX_WIG;
}
}
@@ -4380,12 +4384,12 @@ multiclass avx512_vpmadd<bits<8> opc, st
AVX512VLVectorVTInfo _Dst, bit IsCommutable = 0> {
let Predicates = [HasBWI] in
defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
- _Dst.info512, IsCommutable>, EVEX_V512;
+ _Dst.info512, SSE_PMADD, IsCommutable>, EVEX_V512;
let Predicates = [HasBWI, HasVLX] in {
defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
- _Dst.info256, IsCommutable>, EVEX_V256;
+ _Dst.info256, SSE_PMADD, IsCommutable>, EVEX_V256;
defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
- _Dst.info128, IsCommutable>, EVEX_V128;
+ _Dst.info128, SSE_PMADD, IsCommutable>, EVEX_V128;
}
}
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=319065&r1=319064&r2=319065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Nov 27 10:14:18 2017
@@ -199,6 +199,11 @@ def SSE_INTALU_ITINS_SHUFF_P : OpndItins
IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
>;
+let Sched = WriteShuffle in
+def SSE_PACK : OpndItins<
+ IIC_SSE_PACK, IIC_SSE_PACK
+>;
+
let Sched = WriteMPSAD in
def DEFAULT_ITINS_MPSADSCHED : OpndItins<
IIC_ALU_NONMEM, IIC_ALU_MEM
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