[PATCH] D40343: AMDGPU: Do not combine loads/store across physreg defs
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 27 10:14:19 PST 2017
arsenm added inline comments.
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Comment at: lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:359
+ // tracking physreg defs and uses. This should only affect M0 in
+ // practice.
+ return false;
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There could also be a call instruction, and the function may modify m0 or anything else
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Comment at: test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll:185
; on 16 bank LDS chips.
; GCN-LABEL: {{^}}v_interp_p1_bank16_bug:
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Can you add a test with a no inline call to make sure that works correctly?
https://reviews.llvm.org/D40343
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