[llvm] r318955 - [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 24 07:37:14 PST 2017
Author: dpreobra
Date: Fri Nov 24 07:37:14 2017
New Revision: 318955
URL: http://llvm.org/viewvc/llvm-project?rev=318955&view=rev
Log:
[AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16
See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629
Reviewers: artem.tamazov, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D39488
Modified:
llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s
llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
Modified: llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td?rev=318955&r1=318954&r2=318955&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td Fri Nov 24 07:37:14 2017
@@ -424,6 +424,7 @@ def V_MAD_F16 : VOP3Inst <"v_mad_f16", V
def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
+def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
}
let SubtargetPredicate = isGFX9 in {
@@ -431,11 +432,11 @@ def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_
def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
def V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
+def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>;
} // End SubtargetPredicate = isGFX9
def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
-def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
} // End isCommutable = 1
} // End SubtargetPredicate = Has16BitInsts
@@ -686,6 +687,11 @@ multiclass VOP3_F16_Real_vi<bits<10> op>
VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
}
+multiclass VOP3Interp_F16_Real_vi<bits<10> op> {
+ def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
+ VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
+}
+
} // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI"
let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
@@ -706,6 +712,14 @@ multiclass VOP3OpSel_F16_Real_gfx9<bits<
}
}
+multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
+ def _vi : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
+ VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
+ VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
+ let AsmString = AsmName # ps.AsmOperands;
+ }
+}
+
multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
@@ -767,18 +781,21 @@ defm V_MAD_U16 : VOP3_F16_Real_
defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>;
defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>;
defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>;
+defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>;
defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">;
defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">;
defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">;
defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">;
defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">;
+defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">;
defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;
defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">;
defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
+defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">;
defm V_ADD_I32_gfx9 : VOP3_Real_gfx9 <0x29c, "v_add_i32">;
defm V_SUB_I32_gfx9 : VOP3_Real_gfx9 <0x29d, "v_sub_i32">;
@@ -789,7 +806,6 @@ defm V_INTERP_MOV_F32_e64 : VOP3Interp_R
defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>;
defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>;
-defm V_INTERP_P2_F16 : VOP3Interp_Real_vi <0x276>;
defm V_ADD_F64 : VOP3_Real_vi <0x280>;
defm V_MUL_F64 : VOP3_Real_vi <0x281>;
defm V_MIN_F64 : VOP3_Real_vi <0x282>;
Modified: llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s?rev=318955&r1=318954&r2=318955&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s Fri Nov 24 07:37:14 2017
@@ -385,3 +385,39 @@ v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1
v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
// GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x04,0xd2,0x01,0x05,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3
+// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, -v2, attr0.x, v3
+// GFX9: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p2_f16 v5, v2, attr0.x, |v3|
+// GFX9: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x77,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.w, v3
+// GFX9: v_interp_p2_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x77,0xd2,0xc0,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 high
+// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
+// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr31.x, v3
+// GFX9: v_interp_p2_legacy_f16 v5, v2, attr31.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3
+// GFX9: v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3|
+// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.w, v3
+// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high
+// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp
+// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt?rev=318955&r1=318954&r2=318955&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt Fri Nov 24 07:37:14 2017
@@ -629,3 +629,39 @@
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04
+
+# GFX9: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x44]
+0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x44
+
+# GFX9: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x77,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x04,0x77,0xd2,0x00,0x04,0x0e,0x04
+
+# GFX9: v_interp_p2_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x77,0xd2,0xc0,0x04,0x0e,0x04]
+0x05,0x00,0x77,0xd2,0xc0,0x04,0x0e,0x04
+
+# GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x05,0x0e,0x04]
+0x05,0x00,0x77,0xd2,0x00,0x05,0x0e,0x04
+
+# GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04
+
+# GFX9: v_interp_p2_legacy_f16 v5, v2, attr31.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04]
+0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04
+
+# GFX9: v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
+0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44
+
+# GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04
+
+# GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
+0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04
+
+# GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
+0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04
+
+# GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04
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