[llvm] r318954 - [AVR] Use the short form of 'clr <reg>'

[Dylan McKay via llvm-commits]

Author: dylanmckay
Date: Fri Nov 24 07:36:43 2017
New Revision: 318954

URL: http://llvm.org/viewvc/llvm-project?rev=318954&view=rev
Log:
[AVR] Use the short form of 'clr <reg>'

r318895 made it so that the simpler instruction aliases are printed
rather than their expanded form.

Modified:
    llvm/trunk/test/CodeGen/AVR/interrupts.ll
    llvm/trunk/test/CodeGen/AVR/mul.ll
    llvm/trunk/test/CodeGen/AVR/zext.ll
    llvm/trunk/test/MC/AVR/inst-clr.s

Modified: llvm/trunk/test/CodeGen/AVR/interrupts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/interrupts.ll?rev=318954&r1=318953&r2=318954&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/interrupts.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/interrupts.ll Fri Nov 24 07:36:43 2017
@@ -7,7 +7,7 @@ define avr_intrcc void @interrupt_handle
 ; CHECK-NEXT: push r1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: push r0
-; CHECK: eor r0, r0
+; CHECK: clr r0
 ; CHECK: pop r0
 ; CHECK-NEXT: out 63, r0
 ; CHECK-NEXT: pop r1
@@ -23,7 +23,7 @@ define avr_signalcc void @signal_handler
 ; CHECK-NEXT: push r1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: push r0
-; CHECK: eor r0, r0
+; CHECK: clr r0
 ; CHECK: pop r0
 ; CHECK-NEXT: out 63, r0
 ; CHECK-NEXT: pop r1

Modified: llvm/trunk/test/CodeGen/AVR/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/mul.ll?rev=318954&r1=318953&r2=318954&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/mul.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/mul.ll Fri Nov 24 07:36:43 2017
@@ -3,7 +3,7 @@
 define i8 @mult8(i8 %a, i8 %b) {
 ; CHECK-LABEL: mult8:
 ; CHECK: muls r22, r24
-; CHECK: eor  r1, r1
+; CHECK: clr r1
 ; CHECK: mov  r24, r0
   %mul = mul i8 %b, %a
   ret i8 %mul
@@ -16,10 +16,10 @@ define i16 @mult16(i16 %a, i16 %b) {
 ; CHECK: mul  r22, r24
 ; CHECK: mov  r19, r0
 ; CHECK: mov  r20, r1
-; CHECK: eor  r1,  r1
+; CHECK: clr r1
 ; CHECK: add  r20, r18
 ; CHECK: muls r23, r24
-; CHECK: eor  r1,  r1
+; CHECK: clr r1
 ; CHECK: mov  r22, r0
 ; CHECK: add  r22, r20
 ; :TODO: finish after reworking shift instructions

Modified: llvm/trunk/test/CodeGen/AVR/zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/zext.ll?rev=318954&r1=318953&r2=318954&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/zext.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/zext.ll Fri Nov 24 07:36:43 2017
@@ -4,27 +4,27 @@
 ; eor R25, R25
 define i16 @zext1(i8 %x) {
 ; CHECK-LABEL: zext1:
-; CHECK: eor r25, r25
+; CHECK: clr r25
   %1 = zext i8 %x to i16
   ret i16 %1
 }
 
 ; zext R25:R24, R20
 ; mov R24, R20
-; eor R25, R25
+; clr R25
 define i16 @zext2(i8 %x, i8 %y) {
 ; CHECK-LABEL: zext2:
 ; CHECK: mov r24, r22
-; CHECK: eor r25, r25
+; CHECK: clr r25
   %1 = zext i8 %y to i16
   ret i16 %1
 }
 
 ; zext R25:R24, R24
-; eor R25, R25
+; clr R25
 define i16 @zext_i1(i1 %x) {
 ; CHECK-LABEL: zext_i1:
-; CHECK: eor r25, r25
+; CHECK: clr r25
   %1 = zext i1 %x to i16
   ret i16 %1
 }

Modified: llvm/trunk/test/MC/AVR/inst-clr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AVR/inst-clr.s?rev=318954&r1=318953&r2=318954&view=diff
==============================================================================
--- llvm/trunk/test/MC/AVR/inst-clr.s (original)
+++ llvm/trunk/test/MC/AVR/inst-clr.s Fri Nov 24 07:36:43 2017
@@ -8,7 +8,8 @@ foo:
   clr r5
   clr r0
 
-; CHECK: eor r2,  r2                  ; encoding: [0x22,0x24]
-; CHECK: eor r12, r12                 ; encoding: [0xcc,0x24]
-; CHECK: eor r5,  r5                  ; encoding: [0x55,0x24]
-; CHECK: eor r0,  r0                  ; encoding: [0x00,0x24]
+; CHECK: clr r2                  ; encoding: [0x22,0x24]
+; CHECK: clr r12                 ; encoding: [0xcc,0x24]
+; CHECK: clr r5                  ; encoding: [0x55,0x24]
+; CHECK: clr r0                  ; encoding: [0x00,0x24]
+