[PATCH] D40360: [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen updated this revision to Diff 124058.
sdesmalen added a comment.

Merged together 'isSVEDataVectorRegOfWidth()' and 'isSVEPredicateVectorRegOfWidth()'.
The benefit of this may not necessarily be obvious for this patch, but future patches will add 'isSVE<restricted register class>RegOfWidth()', at which point it will only require an extra line to the switch statement.


https://reviews.llvm.org/D40360

Files:
  lib/Target/AArch64/AArch64RegisterInfo.td
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

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