[llvm] r318352 - Add backend name to Target to enable runtime info to be fed back into TableGen
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 15 15:55:44 PST 2017
Author: dsanders
Date: Wed Nov 15 15:55:44 2017
New Revision: 318352
URL: http://llvm.org/viewvc/llvm-project?rev=318352&view=rev
Log:
Add backend name to Target to enable runtime info to be fed back into TableGen
Summary:
Make it possible to feed runtime information back to tablegen to enable
profile-guided tablegen-eration, detection of untested tablegen definitions, etc.
Being a cross-compiler by nature, LLVM will potentially collect data for multiple
architectures (e.g. when running 'ninja check'). We therefore need a way for
TableGen to figure out what data applies to the backend it is generating at the
time. This patch achieves that by including the name of the 'def X : Target ...'
for the backend in the TargetRegistry.
Reviewers: qcolombet
Reviewed By: qcolombet
Subscribers: jholewinski, arsenm, jyknight, aditya_nandakumar, sdardis, nemanjai, ab, nhaehnle, t.p.northover, javed.absar, qcolombet, llvm-commits, fedor.sergeev
Differential Revision: https://reviews.llvm.org/D39742
Modified:
llvm/trunk/include/llvm/Support/TargetRegistry.h
llvm/trunk/lib/Support/TargetRegistry.cpp
llvm/trunk/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
llvm/trunk/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
llvm/trunk/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
llvm/trunk/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
llvm/trunk/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
llvm/trunk/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
llvm/trunk/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
llvm/trunk/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
llvm/trunk/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
llvm/trunk/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
llvm/trunk/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
Modified: llvm/trunk/include/llvm/Support/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetRegistry.h?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetRegistry.h (original)
+++ llvm/trunk/include/llvm/Support/TargetRegistry.h Wed Nov 15 15:55:44 2017
@@ -187,6 +187,10 @@ private:
/// ShortDesc - A short description of the target.
const char *ShortDesc;
+ /// BackendName - The name of the backend implementation. This must match the
+ /// name of the 'def X : Target ...' in TableGen.
+ const char *BackendName;
+
/// HasJIT - Whether this target supports the JIT.
bool HasJIT;
@@ -279,6 +283,9 @@ public:
/// getShortDescription - Get a short description of the target.
const char *getShortDescription() const { return ShortDesc; }
+ /// getBackendName - Get the backend name.
+ const char *getBackendName() const { return BackendName; }
+
/// @}
/// @name Feature Predicates
/// @{
@@ -645,10 +652,15 @@ struct TargetRegistry {
/// @param Name - The target name. This should be a static string.
/// @param ShortDesc - A short target description. This should be a static
/// string.
+ /// @param BackendName - The name of the backend. This should be a static
+ /// string that is the same for all targets that share a backend
+ /// implementation and must match the name used in the 'def X : Target ...' in
+ /// TableGen.
/// @param ArchMatchFn - The arch match checking function for this target.
/// @param HasJIT - Whether the target supports JIT code
/// generation.
static void RegisterTarget(Target &T, const char *Name, const char *ShortDesc,
+ const char *BackendName,
Target::ArchMatchFnTy ArchMatchFn,
bool HasJIT = false);
@@ -883,8 +895,10 @@ struct TargetRegistry {
template <Triple::ArchType TargetArchType = Triple::UnknownArch,
bool HasJIT = false>
struct RegisterTarget {
- RegisterTarget(Target &T, const char *Name, const char *Desc) {
- TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch, HasJIT);
+ RegisterTarget(Target &T, const char *Name, const char *Desc,
+ const char *BackendName) {
+ TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
+ HasJIT);
}
static bool getArchMatch(Triple::ArchType Arch) {
Modified: llvm/trunk/lib/Support/TargetRegistry.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetRegistry.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Support/TargetRegistry.cpp (original)
+++ llvm/trunk/lib/Support/TargetRegistry.cpp Wed Nov 15 15:55:44 2017
@@ -86,9 +86,9 @@ const Target *TargetRegistry::lookupTarg
return &*I;
}
-void TargetRegistry::RegisterTarget(Target &T,
- const char *Name,
+void TargetRegistry::RegisterTarget(Target &T, const char *Name,
const char *ShortDesc,
+ const char *BackendName,
Target::ArchMatchFnTy ArchMatchFn,
bool HasJIT) {
assert(Name && ShortDesc && ArchMatchFn &&
@@ -105,6 +105,7 @@ void TargetRegistry::RegisterTarget(Targ
T.Name = Name;
T.ShortDesc = ShortDesc;
+ T.BackendName = BackendName;
T.ArchMatchFn = ArchMatchFn;
T.HasJIT = HasJIT;
}
Modified: llvm/trunk/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -29,11 +29,11 @@ extern "C" void LLVMInitializeAArch64Tar
// Now register the "arm64" name for use with "-march". We don't want it to
// take possession of the Triple::aarch64 tag though.
TargetRegistry::RegisterTarget(getTheARM64Target(), "arm64",
- "ARM64 (little endian)",
+ "ARM64 (little endian)", "AArch64",
[](Triple::ArchType) { return false; }, true);
RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z(
- getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)");
+ getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)", "AArch64");
RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W(
- getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)");
+ getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)", "AArch64");
}
Modified: llvm/trunk/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -31,7 +31,7 @@ Target &llvm::getTheGCNTarget() {
/// \brief Extern function to initialize the targets for the AMDGPU backend
extern "C" void LLVMInitializeAMDGPUTargetInfo() {
RegisterTarget<Triple::r600, false> R600(getTheAMDGPUTarget(), "r600",
- "AMD GPUs HD2XXX-HD6XXX");
+ "AMD GPUs HD2XXX-HD6XXX", "AMDGPU");
RegisterTarget<Triple::amdgcn, false> GCN(getTheGCNTarget(), "amdgcn",
- "AMD GCN GPUs");
+ "AMD GCN GPUs", "AMDGPU");
}
Modified: llvm/trunk/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -30,12 +30,12 @@ Target &llvm::getTheThumbBETarget() {
extern "C" void LLVMInitializeARMTargetInfo() {
RegisterTarget<Triple::arm, /*HasJIT=*/true> X(getTheARMLETarget(), "arm",
- "ARM");
+ "ARM", "ARM");
RegisterTarget<Triple::armeb, /*HasJIT=*/true> Y(getTheARMBETarget(), "armeb",
- "ARM (big endian)");
+ "ARM (big endian)", "ARM");
RegisterTarget<Triple::thumb, /*HasJIT=*/true> A(getTheThumbLETarget(),
- "thumb", "Thumb");
+ "thumb", "Thumb", "ARM");
RegisterTarget<Triple::thumbeb, /*HasJIT=*/true> B(
- getTheThumbBETarget(), "thumbeb", "Thumb (big endian)");
+ getTheThumbBETarget(), "thumbeb", "Thumb (big endian)", "ARM");
}
Modified: llvm/trunk/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -28,9 +28,10 @@ Target &getTheBPFTarget() {
extern "C" void LLVMInitializeBPFTargetInfo() {
TargetRegistry::RegisterTarget(getTheBPFTarget(), "bpf", "BPF (host endian)",
- [](Triple::ArchType) { return false; }, true);
- RegisterTarget<Triple::bpfel, /*HasJIT=*/true> X(getTheBPFleTarget(), "bpfel",
- "BPF (little endian)");
+ "BPF", [](Triple::ArchType) { return false; },
+ true);
+ RegisterTarget<Triple::bpfel, /*HasJIT=*/true> X(
+ getTheBPFleTarget(), "bpfel", "BPF (little endian)", "BPF");
RegisterTarget<Triple::bpfeb, /*HasJIT=*/true> Y(getTheBPFbeTarget(), "bpfeb",
- "BPF (big endian)");
+ "BPF (big endian)", "BPF");
}
Modified: llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -18,6 +18,6 @@ Target &llvm::getTheHexagonTarget() {
}
extern "C" void LLVMInitializeHexagonTargetInfo() {
- RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(getTheHexagonTarget(),
- "hexagon", "Hexagon");
+ RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(
+ getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");
}
Modified: llvm/trunk/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -21,5 +21,6 @@ Target &getTheLanaiTarget() {
} // namespace llvm
extern "C" void LLVMInitializeLanaiTargetInfo() {
- RegisterTarget<Triple::lanai> X(getTheLanaiTarget(), "lanai", "Lanai");
+ RegisterTarget<Triple::lanai> X(getTheLanaiTarget(), "lanai", "Lanai",
+ "Lanai");
}
Modified: llvm/trunk/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -19,5 +19,5 @@ Target &llvm::getTheMSP430Target() {
extern "C" void LLVMInitializeMSP430TargetInfo() {
RegisterTarget<Triple::msp430> X(getTheMSP430Target(), "msp430",
- "MSP430 [experimental]");
+ "MSP430 [experimental]", "MSP430");
}
Modified: llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -32,17 +32,17 @@ Target &llvm::getTheMips64elTarget() {
extern "C" void LLVMInitializeMipsTargetInfo() {
RegisterTarget<Triple::mips,
/*HasJIT=*/true>
- X(getTheMipsTarget(), "mips", "Mips");
+ X(getTheMipsTarget(), "mips", "Mips", "Mips");
RegisterTarget<Triple::mipsel,
/*HasJIT=*/true>
- Y(getTheMipselTarget(), "mipsel", "Mipsel");
+ Y(getTheMipselTarget(), "mipsel", "Mipsel", "Mips");
RegisterTarget<Triple::mips64,
/*HasJIT=*/true>
- A(getTheMips64Target(), "mips64", "Mips64 [experimental]");
+ A(getTheMips64Target(), "mips64", "Mips64 [experimental]", "Mips");
RegisterTarget<Triple::mips64el,
/*HasJIT=*/true>
- B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]");
+ B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]", "Mips");
}
Modified: llvm/trunk/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -23,7 +23,7 @@ Target &llvm::getTheNVPTXTarget64() {
extern "C" void LLVMInitializeNVPTXTargetInfo() {
RegisterTarget<Triple::nvptx> X(getTheNVPTXTarget32(), "nvptx",
- "NVIDIA PTX 32-bit");
+ "NVIDIA PTX 32-bit", "NVPTX");
RegisterTarget<Triple::nvptx64> Y(getTheNVPTXTarget64(), "nvptx64",
- "NVIDIA PTX 64-bit");
+ "NVIDIA PTX 64-bit", "NVPTX");
}
Modified: llvm/trunk/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -27,11 +27,11 @@ Target &llvm::getThePPC64LETarget() {
extern "C" void LLVMInitializePowerPCTargetInfo() {
RegisterTarget<Triple::ppc, /*HasJIT=*/true> X(getThePPC32Target(), "ppc32",
- "PowerPC 32");
+ "PowerPC 32", "PPC");
RegisterTarget<Triple::ppc64, /*HasJIT=*/true> Y(getThePPC64Target(), "ppc64",
- "PowerPC 64");
+ "PowerPC 64", "PPC");
RegisterTarget<Triple::ppc64le, /*HasJIT=*/true> Z(
- getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE");
+ getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE", "PPC");
}
Modified: llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -27,9 +27,9 @@ Target &llvm::getTheSparcelTarget() {
extern "C" void LLVMInitializeSparcTargetInfo() {
RegisterTarget<Triple::sparc, /*HasJIT=*/true> X(getTheSparcTarget(), "sparc",
- "Sparc");
- RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(getTheSparcV9Target(),
- "sparcv9", "Sparc V9");
- RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(getTheSparcelTarget(),
- "sparcel", "Sparc LE");
+ "Sparc", "Sparc");
+ RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(
+ getTheSparcV9Target(), "sparcv9", "Sparc V9", "Sparc");
+ RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(
+ getTheSparcelTarget(), "sparcel", "Sparc LE", "Sparc");
}
Modified: llvm/trunk/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -18,6 +18,6 @@ Target &llvm::getTheSystemZTarget() {
}
extern "C" void LLVMInitializeSystemZTargetInfo() {
- RegisterTarget<Triple::systemz, /*HasJIT=*/true> X(getTheSystemZTarget(),
- "systemz", "SystemZ");
+ RegisterTarget<Triple::systemz, /*HasJIT=*/true> X(
+ getTheSystemZTarget(), "systemz", "SystemZ", "SystemZ");
}
Modified: llvm/trunk/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/TargetInfo/X86TargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/TargetInfo/X86TargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/TargetInfo/X86TargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -22,8 +22,8 @@ Target &llvm::getTheX86_64Target() {
extern "C" void LLVMInitializeX86TargetInfo() {
RegisterTarget<Triple::x86, /*HasJIT=*/true> X(
- getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above");
+ getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above", "X86");
RegisterTarget<Triple::x86_64, /*HasJIT=*/true> Y(
- getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64");
+ getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64", "X86");
}
Modified: llvm/trunk/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp?rev=318352&r1=318351&r2=318352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp Wed Nov 15 15:55:44 2017
@@ -18,5 +18,6 @@ Target &llvm::getTheXCoreTarget() {
}
extern "C" void LLVMInitializeXCoreTargetInfo() {
- RegisterTarget<Triple::xcore> X(getTheXCoreTarget(), "xcore", "XCore");
+ RegisterTarget<Triple::xcore> X(getTheXCoreTarget(), "xcore", "XCore",
+ "XCore");
}
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