[PATCH] D40034: [DAGCombine] Enable more srl + load combines

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
Herald added a subscriber: javed.absar.

Change the calculation for the desired ValueType for non-sign extending loads, as in those cases we don't care about the higher bits. This creates a smaller ExtVT and allows for such combinations as:

      

(srl (zextload i16, [addr]), 8) -> (zextload i8, [addr + 1])


https://reviews.llvm.org/D40034

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/shift-combine.ll

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