[PATCH] D39840: [MC][X86] Code padding for performance stability - Branch instructions and targets alignment

[Zvi Rackover via Phabricator via llvm-commits]

zvi added inline comments.


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Comment at: lib/Target/X86/MCTargetDesc/X86MCCodePadder.cpp:70
+      // Immidiate jmps
+      opcode == JAE_1 || opcode == JAE_2 || opcode == JAE_4 || opcode == JA_1 ||
+      opcode == JA_2 || opcode == JA_4 || opcode == JBE_1 || opcode == JBE_2 ||
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Is it possible to encode this info in the .td's with something like isConditionalBranch=1?


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Comment at: lib/Target/X86/MCTargetDesc/X86MCCodePadder.cpp:108
+static bool isCall(const MCInst &Inst) {
+  unsigned int opcode = Inst.getOpcode();
+  return
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This info should already be encoded in the MCDesc look for something like MCID::Call, so instead o f looking for explicit opcode check if this attribute is set. Or does this function look only for a subset of the call instructions?


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Comment at: lib/Target/X86/MCTargetDesc/X86MCCodePadder.h:23
+
+/// The X86-specific class incharge of all code padding decisions for the X86
+/// target.
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*in charge


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Comment at: test/CodeGen/X86/branch-instructions-end-of-16B-chunk-perf-nops.mir:1
+# RUN: llc -mcpu=haswell -filetype=obj -start-before stack-protector -O2 %s -o - | llvm-objdump -d - | FileCheck %s
+
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1. Please commit this file as a NFC change and rebase patch so the diff will be more apparent.
2. Please add a negative tests.


Repository:
  rL LLVM

https://reviews.llvm.org/D39840