[PATCH] D39840: [MC][X86] Code padding for performance stability - Branch instructions and targets alignment

[Omer Paparo Bivas via Phabricator via llvm-commits]

opaparo created this revision.
Herald added a subscriber: mgorny.

Adding X86-specific code padding (the X86MCCodePadder class) that will utilize the previously introduced code padding infrastructure <https://reviews.llvm.org/D34393>.

The Intel optimization reference manual <https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf> states that:

> When executing code from the legacy decode pipeline, direct branches that are mostly taken should have all their instruction bytes in a 16B aligned chunk of memory and nearer the end of that 16B aligned chunk.

(Rule 12 under section 3.4.1.5 "Code Alignment").

In this patch a new policy is introduced, which implements this rule by inserting MCPaddingFragments before branches and branch targets and returning positive penalty weight for 16 Byte windows that contain the said situation.


Repository:
  rL LLVM

https://reviews.llvm.org/D39840

Files:
  lib/MC/MCCodePadder.cpp
  lib/Target/X86/MCTargetDesc/CMakeLists.txt
  lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
  lib/Target/X86/MCTargetDesc/X86MCCodePadder.cpp
  lib/Target/X86/MCTargetDesc/X86MCCodePadder.h
  test/CodeGen/X86/branch-instructions-end-of-16B-chunk-perf-nops.mir

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