[PATCH] D31025: [Docs] Add tablegen backend for target opcode documentatio

[Oliver Stannard via Phabricator via llvm-commits]

olista01 updated this revision to Diff 122233.
olista01 added reviewers: rovka, MatzeB.
olista01 added a comment.

Instead of only printing the operands that appear in the assembly string (some of which correspond to more then one MachineOperand), print a flattened list of operands. Kristof's example instruction now generates this documentation:

  VST1d64TPseudoWB\_fixed
  =======================
  
  Flags: ``mayStore``, ``isPredicable``, ``hasExtraSrcRegAllocReq``, ``isCodeGenOnly``
  
  * DEF ``GPR:$wb``
  
  * USE ``addrmode6/GPR:$addr.addr``
  
  * USE ``addrmode6/i32imm:$addr.align``
  
  * USE ``QQPR:$src``
  
  * USE ``pred/i32imm:$p.anon0``
  
  * USE ``pred/i32imm:$p.anon1``
  
  Constraints: ``$addr.addr = $wb``
  
  Predicates: ``HasNEON``


Repository:
  rL LLVM

https://reviews.llvm.org/D31025

Files:
  utils/TableGen/CMakeLists.txt
  utils/TableGen/InstrDocsEmitter.cpp
  utils/TableGen/TableGen.cpp
  utils/TableGen/TableGenBackends.h

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