[PATCH] D31025: [Docs] Add tablegen backend for target opcode documentatio

[Kristof Beyls via Phabricator via llvm-commits]

kristof.beyls added a comment.

I wanted to look at the documentation produced for a specific instruction today, as part of investigation PR35157.
I wanted to understand what the operands of VST1d64TPseudoWB_fixed are in the Arm backend.
After downloading this patch and building/running it; I saw it produced the following documentation for that instruction:

  VST1d64TPseudoWB\_fixed
  =======================
  
  Flags: ``mayStore``, ``isPredicable``, ``hasExtraSrcRegAllocReq``, ``isCodeGenOnly``
  
  * DEF ``GPR:$wb``
  
  * USE ``addrmode6:$addr`` (**tied to wb**)
  
  * USE ``QQPR:$src``
  
  * USE ``pred:$p``
  
  Predicates: ``HasNEON``

However, this doesn't seem to print all of the operands. It seemingly only prints the operands that are represented somehow in the assembly representation of the instruction?
When looking in ARMGenInstrInfo.inc, for the same instruction, I find (after formatting and adding a few comments to improve readability):

    { 2209,
      /*NumOperands*/     6,
      /*NumDefs*/ 1,
      /*Size*/    4,
      /*SchedClass*/      646,
      /*Flags*/   0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq),
      /*TSFlags*/ 0x10006ULL,
      /*ImplicitUses*/ nullptr,
      /*ImplicitDefs*/ nullptr,
      /*MCOperandInfo* */OperandInfo275,
      /*DeprecatedFeature*/ -1 ,
      /*?*/ nullptr },  // Inst #2209 = VST1d64TPseudoWB_fixed
  ....
  static const MCOperandInfo OperandInfo275[] = {
    { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) },
    { -1, 0, MCOI::OPERAND_MEMORY, 0 },
    { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
    { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
  };

This shows the instruction has 6 operands, 2 more than the 4 operands printed in the documentation.
Could the output in the documentation be adapted so that it prints all operands?


Repository:
  rL LLVM

https://reviews.llvm.org/D31025