[PATCH] D38196: [AArch64] Avoid interleaved SIMD store instructions for Exynos

[Kristof Beyls via Phabricator via llvm-commits]

kristof.beyls added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:151-154
+// This is used to cache instruction replacement decisions within function
+// units and across function units so that we can save on accessing the
+// latency tables.
+std::map<unsigned, bool> SIMDInstrTable;
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Making this a global variable indeed very probably isn't acceptable.
However, I was thinking to have this be a member variable of the AArch64SIMDInstrOpt MachineFunctionPass.
Wouldn't that still allow to cache/reuse this table between different calls of "runOnMachineFunction"?
I still haven't had time to check if this pattern shows up anywhere else in any other Pass.


https://reviews.llvm.org/D38196