[PATCH] D39415: [ARMISelLowering] Better handling of NEON load/store for sequential memory regions

[Renato Golin via Phabricator via llvm-commits]

rengolin added inline comments.


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Comment at: test/CodeGen/ARM/misched-fusion-aes.ll:79
 ; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QC]]
+; CHECK: aese.8 {{q[0-9][0-9]?}}, {{q[0-9][0-9]?}}
 ; CHECK: aese.8 [[QD:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
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fhahn wrote:
> rengolin wrote:
> > evgeny777 wrote:
> > > rengolin wrote:
> > > > why would these change?
> > > IR is compiled into a mixture of aesXX and vldXX instructions which are being scheduled differently after this patch is applied. I checked manually that parameters passed to each aesXX instruction are identical (though I can't guarantee that I didn't make any mistake, of course :)
> > Right, I expected as much. And you can't just ignore those lines because the QD, QE etc. will not match.
> > 
> > Hopefully, simplifying the IR could make the extra AES instructions unnecessary and we end up with a static pattern.
> I think we could replace the last 3 AESE instructions (lines 57, 59, 61), which only combine the results of the previous computations and have no AESMC instructions to pair with. But as long as the number of AESE/ASEMC pairs does not change, the position of the 3 left-over AESE instructions is nothing to be too concerned about IMO.
Sure, I'm not worried about their position, just trying to future-proof the test, so we don't need to keep shuffling them on code-gen changes.


Repository:
  rL LLVM

https://reviews.llvm.org/D39415