[llvm] r316860 - [X86] Remove combine that turns X86ISD::LSUB into X86ISD::LADD. Update patterns that depended on this.
Hal Finkel via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 29 09:42:07 PDT 2017
Hi, Craig,
Were some of the tests in test/CodeGen/X86/atomic-eflags-reuse.ll
already incorrect? If not, can you please add a test case that
demonstrates when the transformation is incorrect. Gor provided a nice
reduced test case in https://bugs.llvm.org/show_bug.cgi?id=35068#c1
Can we check whether the carry flag is being used (by checking for uses
of the second result of the X86ISD::SUB)? It looks like, in Gor's
reduced test case, we have:
t15: i32,i32 = X86ISD::SUB t21, Constant:i32<1>
t18: ch = X86ISD::BRCOND t21:1, BasicBlock:ch<End 0x497a1d8>,
Constant:i8<0>, t15:1
Thanks again,
Hal
On 10/29/2017 01:51 AM, Craig Topper via llvm-commits wrote:
> Author: ctopper
> Date: Sat Oct 28 23:51:04 2017
> New Revision: 316860
>
> URL: http://llvm.org/viewvc/llvm-project?rev=316860&view=rev
> Log:
> [X86] Remove combine that turns X86ISD::LSUB into X86ISD::LADD. Update patterns that depended on this.
>
> If the carry flag is being used, this transformation isn't safe.
>
> This does prevent some test cases from using DEC now, but I'll try to look into that separately.
>
> Fixes PR35068.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86InstrCompiler.td
> llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=316860&r1=316859&r2=316860&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Oct 28 23:51:04 2017
> @@ -36254,26 +36254,6 @@ static SDValue combineVSZext(SDNode *N,
> return SDValue();
> }
>
> -/// Canonicalize (LSUB p, 1) -> (LADD p, -1).
> -static SDValue combineLockSub(SDNode *N, SelectionDAG &DAG,
> - const X86Subtarget &Subtarget) {
> - SDValue Chain = N->getOperand(0);
> - SDValue LHS = N->getOperand(1);
> - SDValue RHS = N->getOperand(2);
> - MVT VT = RHS.getSimpleValueType();
> - SDLoc DL(N);
> -
> - auto *C = dyn_cast<ConstantSDNode>(RHS);
> - if (!C || C->getZExtValue() != 1)
> - return SDValue();
> -
> - RHS = DAG.getConstant(-1, DL, VT);
> - MachineMemOperand *MMO = cast<MemSDNode>(N)->getMemOperand();
> - return DAG.getMemIntrinsicNode(X86ISD::LADD, DL,
> - DAG.getVTList(MVT::i32, MVT::Other),
> - {Chain, LHS, RHS}, VT, MMO);
> -}
> -
> static SDValue combineTestM(SDNode *N, SelectionDAG &DAG,
> const X86Subtarget &Subtarget) {
> SDValue Op0 = N->getOperand(0);
> @@ -36592,7 +36572,6 @@ SDValue X86TargetLowering::PerformDAGCom
> case ISD::FMA: return combineFMA(N, DAG, Subtarget);
> case ISD::MGATHER:
> case ISD::MSCATTER: return combineGatherScatter(N, DAG);
> - case X86ISD::LSUB: return combineLockSub(N, DAG, Subtarget);
> case X86ISD::TESTM: return combineTestM(N, DAG, Subtarget);
> case X86ISD::PCMPEQ:
> case X86ISD::PCMPGT: return combineVectorCompare(N, DAG, Subtarget);
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=316860&r1=316859&r2=316860&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Sat Oct 28 23:51:04 2017
> @@ -593,7 +593,7 @@ def Int_MemBarrier : I<0, Pseudo, (outs)
> // ImmOpc8 corresponds to the mi8 version of the instruction
> // ImmMod corresponds to the instruction format of the mi and mi8 versions
> multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
> - Format ImmMod, SDPatternOperator Op, string mnemonic> {
> + Format ImmMod, SDNode Op, string mnemonic> {
> let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
> SchedRW = [WriteALULd, WriteRMW] in {
>
> @@ -696,31 +696,31 @@ defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x
> defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">;
>
> multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
> - int Increment, string mnemonic> {
> + SDNode Op, string mnemonic> {
> let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
> SchedRW = [WriteALULd, WriteRMW] in {
> def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
> !strconcat(mnemonic, "{b}\t$dst"),
> - [(set EFLAGS, (X86lock_add addr:$dst, (i8 Increment)))],
> + [(set EFLAGS, (Op addr:$dst, (i8 1)))],
> IIC_UNARY_MEM>, LOCK;
> def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
> !strconcat(mnemonic, "{w}\t$dst"),
> - [(set EFLAGS, (X86lock_add addr:$dst, (i16 Increment)))],
> + [(set EFLAGS, (Op addr:$dst, (i16 1)))],
> IIC_UNARY_MEM>, OpSize16, LOCK;
> def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
> !strconcat(mnemonic, "{l}\t$dst"),
> - [(set EFLAGS, (X86lock_add addr:$dst, (i32 Increment)))],
> + [(set EFLAGS, (Op addr:$dst, (i32 1)))],
> IIC_UNARY_MEM>, OpSize32, LOCK;
> def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
> !strconcat(mnemonic, "{q}\t$dst"),
> - [(set EFLAGS, (X86lock_add addr:$dst, (i64 Increment)))],
> + [(set EFLAGS, (Op addr:$dst, (i64 1)))],
> IIC_UNARY_MEM>, LOCK;
> }
> }
>
> let Predicates = [UseIncDec] in {
> -defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, 1, "inc">;
> -defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, -1, "dec">;
> +defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, X86lock_add, "inc">;
> +defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, X86lock_sub, "dec">;
> }
>
> // Atomic compare and swap.
>
> Modified: llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll?rev=316860&r1=316859&r2=316860&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll Sat Oct 28 23:51:04 2017
> @@ -32,7 +32,7 @@ entry:
> define i32 @test_sub_1_cmov_sle(i64* %p, i32 %a0, i32 %a1) #0 {
> ; CHECK-LABEL: test_sub_1_cmov_sle:
> ; CHECK: # BB#0: # %entry
> -; CHECK-NEXT: lock decq (%rdi)
> +; CHECK-NEXT: lock addq $-1, (%rdi)
> ; CHECK-NEXT: cmovgel %edx, %esi
> ; CHECK-NEXT: movl %esi, %eax
> ; CHECK-NEXT: retq
> @@ -46,7 +46,7 @@ entry:
> define i32 @test_sub_1_cmov_sgt(i64* %p, i32 %a0, i32 %a1) #0 {
> ; CHECK-LABEL: test_sub_1_cmov_sgt:
> ; CHECK: # BB#0: # %entry
> -; CHECK-NEXT: lock decq (%rdi)
> +; CHECK-NEXT: lock addq $-1, (%rdi)
> ; CHECK-NEXT: cmovll %edx, %esi
> ; CHECK-NEXT: movl %esi, %eax
> ; CHECK-NEXT: retq
> @@ -76,7 +76,7 @@ entry:
> define i8 @test_sub_1_setcc_sgt(i64* %p) #0 {
> ; CHECK-LABEL: test_sub_1_setcc_sgt:
> ; CHECK: # BB#0: # %entry
> -; CHECK-NEXT: lock decq (%rdi)
> +; CHECK-NEXT: lock addq $-1, (%rdi)
> ; CHECK-NEXT: setge %al
> ; CHECK-NEXT: retq
> entry:
>
>
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--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory
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