[PATCH] D39192: [ARM] processInstruction must return true if it makes a change

[Oliver Stannard via Phabricator via llvm-commits]

olista01 created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

This function must return true if it makes a change, because MatchAndEmitInstruction calls it repeatedly until no further change are made.

No tests because we happen to not hit any of these cases at the moment, but that's just luck.


Repository:
  rL LLVM

https://reviews.llvm.org/D39192

Files:
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp


Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8421,6 +8421,7 @@
       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
       TmpInst.addOperand(Inst.getOperand(3));
       Inst = TmpInst;
+      return true;
     }
     break;
   case ARM::t2ADDri12:
@@ -8431,16 +8432,16 @@
       break;
     Inst.setOpcode(ARM::t2ADDri);
     Inst.addOperand(MCOperand::createReg(0)); // cc_out
-    break;
+    return true;
   case ARM::t2SUBri12:
     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
     // mnemonic was used (not "subw"), encoding T3 is preferred.
     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
       break;
     Inst.setOpcode(ARM::t2SUBri);
     Inst.addOperand(MCOperand::createReg(0)); // cc_out
-    break;
+    return true;
   case ARM::tADDi8:
     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred


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