[llvm] r316237 - [globalisel][tablegen] Fix small spelling nits. NFC
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 20 15:52:45 PDT 2017
Hi Galina,
Something strange is happening on one of your bots (llvm-clang-x86_64-expensive-checks-win). After this commit, it didn't re-run tablegen as we've found in the past so I forced a clean build as usual. However, now it's failing to run the cmake step successfully due to a missing LLVMBuild.txt (see http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/5612/steps/cmake-configure/logs/stdio <http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/5612/steps/cmake-configure/logs/stdio>). I'd hazard a guess that the actual problem is related to the '/' that's in the path and that the clean build has only made a pre-existing problem visible. Could you take a look?
> On 20 Oct 2017, at 13:55, Daniel Sanders via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>
> Author: dsanders
> Date: Fri Oct 20 13:55:29 2017
> New Revision: 316237
>
> URL: http://llvm.org/viewvc/llvm-project?rev=316237&view=rev
> Log:
> [globalisel][tablegen] Fix small spelling nits. NFC
>
> ComplexRendererFn -> ComplexRendererFns
> Corrected a couple lingering references to tied operands that were missed.
>
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
> llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
> llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
> llvm/trunk/test/TableGen/GlobalISelEmitter.td
> llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h?rev=316237&r1=316236&r2=316237&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h Fri Oct 20 13:55:29 2017
> @@ -276,13 +276,13 @@ public:
> virtual bool select(MachineInstr &I) const = 0;
>
> protected:
> - using ComplexRendererFn =
> + using ComplexRendererFns =
> Optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
> using RecordedMIVector = SmallVector<MachineInstr *, 4>;
> using NewMIVector = SmallVector<MachineInstrBuilder, 4>;
>
> struct MatcherState {
> - std::vector<ComplexRendererFn::value_type> Renderers;
> + std::vector<ComplexRendererFns::value_type> Renderers;
> RecordedMIVector MIs;
>
> MatcherState(unsigned MaxRenderers);
>
> Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h?rev=316237&r1=316236&r2=316237&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h Fri Oct 20 13:55:29 2017
> @@ -297,7 +297,7 @@ bool InstructionSelector::executeMatchTa
> << "), ComplexPredicateID=" << ComplexPredicateID << ")\n");
> assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
> // FIXME: Use std::invoke() when it's available.
> - ComplexRendererFn Renderer =
> + ComplexRendererFns Renderer =
> (ISel.*MatcherInfo.ComplexPredicates[ComplexPredicateID])(
> State.MIs[InsnID]->getOperand(OpIdx));
> if (Renderer.hasValue())
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=316237&r1=316236&r2=316237&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Fri Oct 20 13:55:29 2017
> @@ -64,31 +64,31 @@ private:
> bool selectCompareBranch(MachineInstr &I, MachineFunction &MF,
> MachineRegisterInfo &MRI) const;
>
> - ComplexRendererFn selectArithImmed(MachineOperand &Root) const;
> + ComplexRendererFns selectArithImmed(MachineOperand &Root) const;
>
> - ComplexRendererFn selectAddrModeUnscaled(MachineOperand &Root,
> - unsigned Size) const;
> + ComplexRendererFns selectAddrModeUnscaled(MachineOperand &Root,
> + unsigned Size) const;
>
> - ComplexRendererFn selectAddrModeUnscaled8(MachineOperand &Root) const {
> + ComplexRendererFns selectAddrModeUnscaled8(MachineOperand &Root) const {
> return selectAddrModeUnscaled(Root, 1);
> }
> - ComplexRendererFn selectAddrModeUnscaled16(MachineOperand &Root) const {
> + ComplexRendererFns selectAddrModeUnscaled16(MachineOperand &Root) const {
> return selectAddrModeUnscaled(Root, 2);
> }
> - ComplexRendererFn selectAddrModeUnscaled32(MachineOperand &Root) const {
> + ComplexRendererFns selectAddrModeUnscaled32(MachineOperand &Root) const {
> return selectAddrModeUnscaled(Root, 4);
> }
> - ComplexRendererFn selectAddrModeUnscaled64(MachineOperand &Root) const {
> + ComplexRendererFns selectAddrModeUnscaled64(MachineOperand &Root) const {
> return selectAddrModeUnscaled(Root, 8);
> }
> - ComplexRendererFn selectAddrModeUnscaled128(MachineOperand &Root) const {
> + ComplexRendererFns selectAddrModeUnscaled128(MachineOperand &Root) const {
> return selectAddrModeUnscaled(Root, 16);
> }
>
> - ComplexRendererFn selectAddrModeIndexed(MachineOperand &Root,
> - unsigned Size) const;
> + ComplexRendererFns selectAddrModeIndexed(MachineOperand &Root,
> + unsigned Size) const;
> template <int Width>
> - ComplexRendererFn selectAddrModeIndexed(MachineOperand &Root) const {
> + ComplexRendererFns selectAddrModeIndexed(MachineOperand &Root) const {
> return selectAddrModeIndexed(Root, Width / 8);
> }
>
> @@ -1373,7 +1373,7 @@ bool AArch64InstructionSelector::select(
> /// SelectArithImmed - Select an immediate value that can be represented as
> /// a 12-bit value shifted left by either 0 or 12. If so, return true with
> /// Val set to the 12-bit value and Shift set to the shifter operand.
> -InstructionSelector::ComplexRendererFn
> +InstructionSelector::ComplexRendererFns
> AArch64InstructionSelector::selectArithImmed(MachineOperand &Root) const {
> MachineInstr &MI = *Root.getParent();
> MachineBasicBlock &MBB = *MI.getParent();
> @@ -1423,7 +1423,7 @@ AArch64InstructionSelector::selectArithI
> /// immediate addressing mode. The "Size" argument is the size in bytes of the
> /// memory reference, which is needed here to know what is valid for a scaled
> /// immediate.
> -InstructionSelector::ComplexRendererFn
> +InstructionSelector::ComplexRendererFns
> AArch64InstructionSelector::selectAddrModeUnscaled(MachineOperand &Root,
> unsigned Size) const {
> MachineRegisterInfo &MRI =
> @@ -1467,7 +1467,7 @@ AArch64InstructionSelector::selectAddrMo
> /// Select a "register plus scaled unsigned 12-bit immediate" address. The
> /// "Size" argument is the size in bytes of the memory reference, which
> /// determines the scale.
> -InstructionSelector::ComplexRendererFn
> +InstructionSelector::ComplexRendererFns
> AArch64InstructionSelector::selectAddrModeIndexed(MachineOperand &Root,
> unsigned Size) const {
> MachineRegisterInfo &MRI =
>
> Modified: llvm/trunk/test/TableGen/GlobalISelEmitter.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/GlobalISelEmitter.td?rev=316237&r1=316236&r2=316237&view=diff
> ==============================================================================
> --- llvm/trunk/test/TableGen/GlobalISelEmitter.td (original)
> +++ llvm/trunk/test/TableGen/GlobalISelEmitter.td Fri Oct 20 13:55:29 2017
> @@ -53,7 +53,7 @@ def HasC : Predicate<"Subtarget->hasC()"
>
> // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
> // CHECK-NEXT: mutable MatcherState State;
> -// CHECK-NEXT: typedef ComplexRendererFn(MyTargetInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
> +// CHECK-NEXT: typedef ComplexRendererFns(MyTargetInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
> // CHECK-NEXT: const MatcherInfoTy<PredicateBitset, ComplexMatcherMemFn> MatcherInfo;
> // CHECK-NEXT: static MyTargetInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
> // CHECK-NEXT: #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
>
> Modified: llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=316237&r1=316236&r2=316237&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp Fri Oct 20 13:55:29 2017
> @@ -672,7 +672,7 @@ public:
> /// but OPM_Int must have priority over OPM_RegBank since constant integers
> /// are represented by a virtual register defined by a G_CONSTANT instruction.
> enum PredicateKind {
> - OPM_Tie,
> + OPM_SameOperand,
> OPM_ComplexPattern,
> OPM_IntrinsicID,
> OPM_Instruction,
> @@ -724,14 +724,14 @@ PredicateListMatcher<OperandPredicateMat
> /// Generates code to check that a register operand is defined by the same exact
> /// one as another.
> class SameOperandMatcher : public OperandPredicateMatcher {
> - std::string TiedTo;
> + std::string MatchingName;
>
> public:
> - SameOperandMatcher(StringRef TiedTo)
> - : OperandPredicateMatcher(OPM_Tie), TiedTo(TiedTo) {}
> + SameOperandMatcher(StringRef MatchingName)
> + : OperandPredicateMatcher(OPM_SameOperand), MatchingName(MatchingName) {}
>
> static bool classof(const OperandPredicateMatcher *P) {
> - return P->getKind() == OPM_Tie;
> + return P->getKind() == OPM_SameOperand;
> }
>
> void emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule,
> @@ -2094,7 +2094,7 @@ void SameOperandMatcher::emitPredicateOp
> RuleMatcher &Rule,
> unsigned InsnVarID,
> unsigned OpIdx) const {
> - const OperandMatcher &OtherOM = Rule.getOperandMatcher(TiedTo);
> + const OperandMatcher &OtherOM = Rule.getOperandMatcher(MatchingName);
> unsigned OtherInsnVarID = Rule.getInsnVarID(OtherOM.getInstructionMatcher());
>
> Table << MatchTable::Opcode("GIM_CheckIsSameOperand")
> @@ -2982,7 +2982,7 @@ void GlobalISelEmitter::run(raw_ostream
> OS << "#ifdef GET_GLOBALISEL_TEMPORARIES_DECL\n"
> << " mutable MatcherState State;\n"
> << " typedef "
> - "ComplexRendererFn("
> + "ComplexRendererFns("
> << Target.getName()
> << "InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;\n"
> << " const MatcherInfoTy<PredicateBitset, ComplexMatcherMemFn> "
>
>
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