[llvm] r316101 - [Hexagon] New HVX target features.
Vlad Tsyrklevich via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 18 13:56:06 PDT 2017
Hey Sumanth, this change seems to have broken a number of buildbots, e.g.
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/8887/steps/check-clang%20asan/logs/stdio
On Wed, Oct 18, 2017 at 11:07 AM Sumanth Gundapaneni via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: sgundapa
> Date: Wed Oct 18 11:07:07 2017
> New Revision: 316101
>
> URL: http://llvm.org/viewvc/llvm-project?rev=316101&view=rev
> Log:
> [Hexagon] New HVX target features.
>
> This patch lets the llvm tools handle the new HVX target features that
> are added by frontend (clang). The target-features are of the form
> "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode
> HVX.
> "hvx-double" is an alias to "hvx-length128b" and is soon will be
> deprecated.
> The hvx version target feature is upgated form "+hvx" to
> "+hvxv{version_number}.
> Eg: "+hvxv62"
>
> For the correct HVX code generation, the user must use the following
> target features.
> For 64B mode: "+hvxv62" "+hvx-length64b"
> For 128B mode: "+hvxv62" "+hvx-length128b"
>
> Clang picks a default length if none is specified. If for some reason,
> no hvx-length is specified to llvm, the compilation will bail out.
> There is a corresponding clang patch.
>
> Differential Revision: https://reviews.llvm.org/D38851
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/Hexagon.td
> llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td
> llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
> llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll
> llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll
> llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll
> llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll
> llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll
> llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll
> llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll
> llvm/trunk/test/CodeGen/Hexagon/bit-has.ll
> llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll
> llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll
> llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll
> llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll
> llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll
> llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll
> llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll
> llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll
> llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll
> llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll
> llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
> llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll
> llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll
> llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll
> llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll
> llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll
> llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
> llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
> llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll
> llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
> llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll
> llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll
> llvm/trunk/test/CodeGen/Hexagon/fminmax.ll
> llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll
> llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll
> llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll
> llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll
>
> llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll
> llvm/trunk/test/CodeGen/Hexagon/hvx-nontemporal.ll
> llvm/trunk/test/CodeGen/Hexagon/hwloop-noreturn-call.ll
> llvm/trunk/test/CodeGen/Hexagon/hwloop-preh.ll
> llvm/trunk/test/CodeGen/Hexagon/inline-asm-qv.ll
> llvm/trunk/test/CodeGen/Hexagon/inline-asm-vecpred128.ll
> llvm/trunk/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll
> llvm/trunk/test/CodeGen/Hexagon/intrinsics/byte-store.ll
> llvm/trunk/test/CodeGen/Hexagon/intrinsics/system_user.ll
> llvm/trunk/test/CodeGen/Hexagon/jt-in-text.ll
> llvm/trunk/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
> llvm/trunk/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
> llvm/trunk/test/CodeGen/Hexagon/loop-prefetch.ll
> llvm/trunk/test/CodeGen/Hexagon/lower-extract-subvector.ll
> llvm/trunk/test/CodeGen/Hexagon/memops-stack.ll
>
> llvm/trunk/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll
> llvm/trunk/test/CodeGen/Hexagon/multi-cycle.ll
> llvm/trunk/test/CodeGen/Hexagon/newify-crash.ll
> llvm/trunk/test/CodeGen/Hexagon/newvaluejump3.ll
> llvm/trunk/test/CodeGen/Hexagon/peephole-kill-flags.ll
> llvm/trunk/test/CodeGen/Hexagon/plt-rel.ll
> llvm/trunk/test/CodeGen/Hexagon/post-inc-aa-metadata.ll
> llvm/trunk/test/CodeGen/Hexagon/propagate-vcombine.ll
> llvm/trunk/test/CodeGen/Hexagon/rdf-def-mask.ll
> llvm/trunk/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll
> llvm/trunk/test/CodeGen/Hexagon/rdf-inline-asm.ll
> llvm/trunk/test/CodeGen/Hexagon/reg-scavengebug-3.ll
> llvm/trunk/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll
> llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir
> llvm/trunk/test/CodeGen/Hexagon/regalloc-block-overlap.ll
> llvm/trunk/test/CodeGen/Hexagon/select-instr-align.ll
> llvm/trunk/test/CodeGen/Hexagon/stack-align-reset.ll
> llvm/trunk/test/CodeGen/Hexagon/store-shift.ll
> llvm/trunk/test/CodeGen/Hexagon/switch-lut-explicit-section.ll
> llvm/trunk/test/CodeGen/Hexagon/switch-lut-function-section.ll
> llvm/trunk/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll
> llvm/trunk/test/CodeGen/Hexagon/switch-lut-text-section.ll
> llvm/trunk/test/CodeGen/Hexagon/undo-dag-shift.ll
> llvm/trunk/test/CodeGen/Hexagon/v60-cur.ll
> llvm/trunk/test/CodeGen/Hexagon/v60-vsel1.ll
> llvm/trunk/test/CodeGen/Hexagon/v60Intrins.ll
> llvm/trunk/test/CodeGen/Hexagon/v60Vasr.ll
> llvm/trunk/test/CodeGen/Hexagon/v60small.ll
> llvm/trunk/test/CodeGen/Hexagon/v6vec-vprint.ll
> llvm/trunk/test/CodeGen/Hexagon/vassign-to-combine.ll
> llvm/trunk/test/CodeGen/Hexagon/vdmpy-halide-test.ll
> llvm/trunk/test/CodeGen/Hexagon/vec-pred-spill1.ll
> llvm/trunk/test/CodeGen/Hexagon/vec-vararg-align.ll
> llvm/trunk/test/CodeGen/Hexagon/vector-align.ll
> llvm/trunk/test/CodeGen/Hexagon/vload-postinc-sel.ll
> llvm/trunk/test/CodeGen/Hexagon/vmpa-halide-test.ll
> llvm/trunk/test/CodeGen/Hexagon/vpack_eo.ll
> llvm/trunk/test/CodeGen/Hexagon/vselect-pseudo.ll
> llvm/trunk/test/MC/Hexagon/align.s
> llvm/trunk/test/MC/Hexagon/double-vector-producer.s
> llvm/trunk/test/MC/Hexagon/test.s
> llvm/trunk/test/MC/Hexagon/v60-alu.s
> llvm/trunk/test/MC/Hexagon/v60-misc.s
> llvm/trunk/test/MC/Hexagon/v60-permute.s
> llvm/trunk/test/MC/Hexagon/v60-shift.s
> llvm/trunk/test/MC/Hexagon/v60-vcmp.s
> llvm/trunk/test/MC/Hexagon/v60-vmem.s
> llvm/trunk/test/MC/Hexagon/v60-vmpy-acc.s
> llvm/trunk/test/MC/Hexagon/v60-vmpy1.s
> llvm/trunk/test/MC/Hexagon/v60lookup.s
> llvm/trunk/test/MC/Hexagon/v62_all.s
>
> llvm/trunk/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
> llvm/trunk/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll
>
> Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Wed Oct 18 11:07:07 2017
> @@ -25,10 +25,31 @@ include "llvm/Target/Target.td"
> include "HexagonDepArch.td"
>
> // Hexagon ISA Extensions
> -def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true",
> - "Hexagon HVX instructions">;
> -def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps",
> "true",
> - "Hexagon HVX Double instructions">;
> +def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
> + "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
> +def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
> + "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
> + [ExtensionHVXV60]>;
> +def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
> + "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
> + [ExtensionHVXV60,
> + ExtensionHVXV62]>;
> +def ExtensionHVX64B
> + : SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true",
> + "Hexagon HVX 64B instructions",
> + [ExtensionHVXV60, ExtensionHVXV62]>;
> +def ExtensionHVX128B
> + : SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true",
> + "Hexagon HVX 128B instructions",
> + [ExtensionHVXV60, ExtensionHVXV62]>;
> +
> +// This is an alias to ExtensionHVX128B to accept the hvx-double as
> +// an acceptable subtarget feature.
> +def ExtensionHVXDbl
> + : SubtargetFeature<"hvx-double", "UseHVX128BOps", "true",
> + "Hexagon HVX 128B instructions",
> + [ExtensionHVXV60, ExtensionHVXV62]>;
> +
> def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls",
> "true",
> "Use constant-extended calls">;
>
> @@ -38,14 +59,21 @@ def FeatureLongCalls: SubtargetFeature<"
>
> def UseMEMOP : Predicate<"HST->useMemOps()">;
> def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">;
> -def UseHVXDbl : Predicate<"HST->useHVXDblOps()">,
> - AssemblerPredicate<"ExtensionHVXDbl">;
> -def UseHVXSgl : Predicate<"HST->useHVXSglOps()">;
> -def UseHVX : Predicate<"HST->useHVXSglOps()
> ||HST->useHVXDblOps()">,
> - AssemblerPredicate<"ExtensionHVX">;
> -
> -def Hvx64 : HwMode<"+hvx,-hvx-double">;
> -def Hvx128 : HwMode<"+hvx,+hvx-double">;
> +def UseHVX64B : Predicate<"HST->useHVX64BOps()">,
> + AssemblerPredicate<"ExtensionHVX64B">;
> +def UseHVX128B : Predicate<"HST->useHVX128BOps()">,
> + AssemblerPredicate<"ExtensionHVX128B">;
> +def UseHVX : Predicate<"HST->useHVXOps()">,
> + AssemblerPredicate<"ExtensionHVXV60">;
> +def UseHVXV60 : Predicate<"HST->useHVXOps()">,
> + AssemblerPredicate<"ExtensionHVXV60">;
> +def UseHVXV62 : Predicate<"HST->useHVXOps()">,
> + AssemblerPredicate<"ExtensionHVXV62">;
> +
> +def Hvx64 : HwMode<"+hvx-length64b">;
> +def Hvx64old : HwMode<"-hvx-double">;
> +def Hvx128 : HwMode<"+hvx-length128b">;
> +def Hvx128old : HwMode<"+hvx-double">;
>
>
> //===----------------------------------------------------------------------===//
> // Classes used for relation maps.
> @@ -274,9 +302,9 @@ def : Proc<"hexagonv5", HexagonModelV4,
> def : Proc<"hexagonv55", HexagonModelV55,
> [ArchV4, ArchV5, ArchV55]>;
> def : Proc<"hexagonv60", HexagonModelV60,
> - [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>;
> + [ArchV4, ArchV5, ArchV55, ArchV60]>;
> def : Proc<"hexagonv62", HexagonModelV62,
> - [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ExtensionHVX]>;
> + [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62]>;
>
>
> //===----------------------------------------------------------------------===//
> // Declare the target which we are implementing
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Oct 18
> 11:07:07 2017
> @@ -357,7 +357,7 @@ static bool CC_HexagonVector(unsigned Va
> auto &MF = State.getMachineFunction();
> auto &HST = MF.getSubtarget<HexagonSubtarget>();
>
> - if (HST.useHVXSglOps() &&
> + if (HST.useHVX64BOps() &&
> (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT ==
> MVT::v32i16 ||
> LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
> if (unsigned Reg = State.AllocateReg(VecLstS)) {
> @@ -368,7 +368,7 @@ static bool CC_HexagonVector(unsigned Va
> State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT,
> LocInfo));
> return false;
> }
> - if (HST.useHVXSglOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32
> ||
> + if (HST.useHVX64BOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32
> ||
> LocVT == MVT::v64i16 || LocVT ==
> MVT::v128i8)) {
> if (unsigned Reg = State.AllocateReg(VecLstD)) {
> State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT,
> LocInfo));
> @@ -379,8 +379,8 @@ static bool CC_HexagonVector(unsigned Va
> return false;
> }
> // 128B Mode
> - if (HST.useHVXDblOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32
> ||
> - LocVT == MVT::v128i16 || LocVT ==
> MVT::v256i8)) {
> + if (HST.useHVX128BOps() && (LocVT == MVT::v32i64 || LocVT ==
> MVT::v64i32 ||
> + LocVT == MVT::v128i16 || LocVT ==
> MVT::v256i8)) {
> if (unsigned Reg = State.AllocateReg(VecLstD)) {
> State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT,
> LocInfo));
> return false;
> @@ -389,7 +389,7 @@ static bool CC_HexagonVector(unsigned Va
> State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT,
> LocInfo));
> return false;
> }
> - if (HST.useHVXDblOps() &&
> + if (HST.useHVX128BOps() &&
> (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT ==
> MVT::v64i16 ||
> LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
> if (unsigned Reg = State.AllocateReg(VecLstS)) {
> @@ -437,7 +437,7 @@ static bool RetCC_Hexagon(unsigned ValNo
> LocInfo = CCValAssign::Full;
> } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
> LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
> - (LocVT == MVT::v1024i1 && HST.useHVXDblOps())) {
> + (LocVT == MVT::v1024i1 && HST.useHVX128BOps())) {
> LocVT = MVT::v32i32;
> ValVT = MVT::v32i32;
> LocInfo = CCValAssign::Full;
> @@ -507,7 +507,7 @@ static bool RetCC_HexagonVector(unsigned
> return false;
> }
> } else if (LocVT == MVT::v32i32) {
> - unsigned Req = HST.useHVXDblOps() ? Hexagon::V0 : Hexagon::W0;
> + unsigned Req = HST.useHVX128BOps() ? Hexagon::V0 : Hexagon::W0;
> if (unsigned Reg = State.AllocateReg(Req)) {
> State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT,
> LocInfo));
> return false;
> @@ -827,9 +827,9 @@ HexagonTargetLowering::LowerCall(TargetL
> DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
> // V6 vectors passed by value have 64 or 128 byte alignment depending
> // on whether we are 64 byte vector mode or 128 byte.
> - bool UseHVXDbl = Subtarget.useHVXDblOps();
> + bool UseHVX128B = Subtarget.useHVX128BOps();
> assert(Subtarget.useHVXOps());
> - const unsigned ObjAlign = UseHVXDbl ? 128 : 64;
> + const unsigned ObjAlign = UseHVX128B ? 128 : 64;
> LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
> MFI.ensureMaxAlignment(LargestAlignSeen);
> }
> @@ -940,15 +940,15 @@ static bool getIndexedAddressParts(SDNod
>
> auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
>
> - bool ValidHVXDblType =
> - HST.useHVXDblOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
> - VT == MVT::v64i16 || VT == MVT::v128i8);
> + bool ValidHVX128BType =
> + HST.useHVX128BOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
> + VT == MVT::v64i16 || VT == MVT::v128i8);
> bool ValidHVXType =
> - HST.useHVXSglOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
> + HST.useHVX64BOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
> VT == MVT::v32i16 || VT == MVT::v64i8);
>
> - if (ValidHVXDblType || ValidHVXType ||
> - VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT ==
> MVT::i8) {
> + if (ValidHVX128BType || ValidHVXType || VT == MVT::i64 || VT ==
> MVT::i32 ||
> + VT == MVT::i16 || VT == MVT::i8) {
> IsInc = (Ptr->getOpcode() == ISD::ADD);
> Base = Ptr->getOperand(0);
> Offset = Ptr->getOperand(1);
> @@ -1182,7 +1182,7 @@ SDValue HexagonTargetLowering::LowerForm
> RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
> RegInfo.addLiveIn(VA.getLocReg(), VReg);
> InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
> - } else if (Subtarget.useHVXDblOps() &&
> + } else if (Subtarget.useHVX128BOps() &&
> ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
> RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
> unsigned VReg =
> @@ -1197,7 +1197,7 @@ SDValue HexagonTargetLowering::LowerForm
> RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
> RegInfo.addLiveIn(VA.getLocReg(), VReg);
> InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
> - } else if (Subtarget.useHVXDblOps() &&
> + } else if (Subtarget.useHVX128BOps() &&
> ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
> RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
> unsigned VReg =
> @@ -1743,7 +1743,7 @@ HexagonTargetLowering::HexagonTargetLowe
> }
>
> if (Subtarget.hasV60TOps()) {
> - if (Subtarget.useHVXSglOps()) {
> + if (Subtarget.useHVX64BOps()) {
> addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass);
> addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
> addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
> @@ -1753,7 +1753,7 @@ HexagonTargetLowering::HexagonTargetLowe
> addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
> addRegisterClass(MVT::v16i64, &Hexagon::HvxWRRegClass);
> addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass);
> - } else if (Subtarget.useHVXDblOps()) {
> + } else if (Subtarget.useHVX128BOps()) {
> addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass);
> addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass);
> addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass);
> @@ -1992,7 +1992,7 @@ HexagonTargetLowering::HexagonTargetLowe
> setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
>
> if (Subtarget.useHVXOps()) {
> - if (Subtarget.useHVXSglOps()) {
> + if (Subtarget.useHVX64BOps()) {
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom);
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom);
> @@ -2004,7 +2004,7 @@ HexagonTargetLowering::HexagonTargetLowe
> setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom);
> setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom);
> setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
> - } else if (Subtarget.useHVXDblOps()) {
> + } else if (Subtarget.useHVX128BOps()) {
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom);
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom);
> @@ -2082,13 +2082,13 @@ HexagonTargetLowering::HexagonTargetLowe
> setIndexedStoreAction(ISD::POST_INC, VT, Legal);
> }
>
> - if (Subtarget.useHVXSglOps()) {
> + if (Subtarget.useHVX64BOps()) {
> for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
> MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {
> setIndexedLoadAction(ISD::POST_INC, VT, Legal);
> setIndexedStoreAction(ISD::POST_INC, VT, Legal);
> }
> - } else if (Subtarget.useHVXDblOps()) {
> + } else if (Subtarget.useHVX128BOps()) {
> for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64,
> MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) {
> setIndexedLoadAction(ISD::POST_INC, VT, Legal);
> @@ -2353,8 +2353,8 @@ HexagonTargetLowering::LowerVECTOR_SHUFF
> size_t MaskLen = Mask.size();
> unsigned SizeInBits = VT.getScalarSizeInBits() * MaskLen;
>
> - if ((Subtarget.useHVXSglOps() && SizeInBits == 64 * 8) ||
> - (Subtarget.useHVXDblOps() && SizeInBits == 128 * 8)) {
> + if ((Subtarget.useHVX64BOps() && SizeInBits == 64 * 8) ||
> + (Subtarget.useHVX128BOps() && SizeInBits == 128 * 8)) {
> StridedLoadKind Pattern = isStridedLoad(Mask);
> if (Pattern == StridedLoadKind::NoPattern)
> return SDValue();
> @@ -2617,11 +2617,11 @@ HexagonTargetLowering::LowerCONCAT_VECTO
> return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1),
> Vec0);
>
> if (UseHVX) {
> - assert((Width == 64*8 && Subtarget.useHVXSglOps()) ||
> - (Width == 128*8 && Subtarget.useHVXDblOps()));
> + assert((Width == 64 * 8 && Subtarget.useHVX64BOps()) ||
> + (Width == 128 * 8 && Subtarget.useHVX128BOps()));
> SDValue Vec1 = Op.getOperand(1);
> - MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32;
> - MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32;
> + MVT OpTy = Subtarget.useHVX64BOps() ? MVT::v16i32 : MVT::v32i32;
> + MVT ReTy = Subtarget.useHVX64BOps() ? MVT::v32i32 : MVT::v64i32;
> SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
> SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
> SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);
> @@ -2667,7 +2667,7 @@ HexagonTargetLowering::LowerEXTRACT_SUBV
> EVT VT = Op.getOperand(0).getValueType();
> SDLoc dl(Op);
> bool UseHVX = Subtarget.useHVXOps();
> - bool UseHVXSgl = Subtarget.useHVXSglOps();
> + bool UseHVX64B = Subtarget.useHVX64BOps();
> // Just in case...
>
> if (!VT.isVector() || !UseHVX)
> @@ -2675,7 +2675,7 @@ HexagonTargetLowering::LowerEXTRACT_SUBV
>
> EVT ResVT = Op.getValueType();
> unsigned ResSize = ResVT.getSizeInBits();
> - unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8);
> + unsigned VectorSizeInBits = UseHVX64B ? (64 * 8) : (128 * 8);
> unsigned OpSize = VT.getSizeInBits();
>
> // We deal only with cases where the result is the vector size
> @@ -3001,7 +3001,7 @@ HexagonTargetLowering::getRegForInlineAs
> case 512:
> return std::make_pair(0U, &Hexagon::HvxVRRegClass);
> case 1024:
> - if (Subtarget.hasV60TOps() && Subtarget.useHVXDblOps())
> + if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps())
> return std::make_pair(0U, &Hexagon::HvxVRRegClass);
> return std::make_pair(0U, &Hexagon::HvxWRRegClass);
> case 2048:
> @@ -3204,7 +3204,7 @@ HexagonTargetLowering::findRepresentativ
> case MVT::v32i32:
> case MVT::v16i64:
> if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
> - Subtarget.useHVXDblOps())
> + Subtarget.useHVX128BOps())
> RRC = &Hexagon::HvxVRRegClass;
> else
> RRC = &Hexagon::HvxWRRegClass;
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td Wed Oct 18 11:07:07 2017
> @@ -427,7 +427,7 @@ class LDrivv_template<RegisterClass RC,
> def PS_vloadrw_ai: LDrivv_template<HvxWR, V6_vL32b_ai>,
> Requires<[HasV60T,UseHVX]>;
> def PS_vloadrw_nt_ai: LDrivv_template<HvxWR, V6_vL32b_nt_ai>,
> - Requires<[HasV60T,UseHVXSgl]>;
> + Requires<[HasV60T,UseHVX]>;
> def PS_vloadrwu_ai: LDrivv_template<HvxWR, V6_vL32Ub_ai>,
> Requires<[HasV60T,UseHVX]>;
>
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Wed Oct 18
> 11:07:07 2017
> @@ -216,25 +216,33 @@ let Namespace = "Hexagon" in {
>
> // HVX types
>
> -def VecI1 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
> - [v512i1, v1024i1, v512i1]>;
> -def VecI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
> - [v64i8, v128i8, v64i8]>;
> -def VecI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
> - [v32i16, v64i16, v32i16]>;
> -def VecI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
> - [v16i32, v32i32, v16i32]>;
> -def VecI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
> - [v8i64, v16i64, v8i64]>;
> -def VecPI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
> - [v128i8, v256i8, v128i8]>;
> -def VecPI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
> - [v64i16, v128i16, v64i16]>;
> -def VecPI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
> - [v32i32, v64i32, v32i32]>;
> -def VecPI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
> - [v16i64, v32i64, v16i64]>;
> -
> +def VecI1
> + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old,
> DefaultMode],
> + [v512i1, v512i1, v1024i1, v1024i1, v512i1]>;
> +def VecI8
> + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old,
> DefaultMode],
> + [v64i8, v64i8, v128i8, v128i8, v64i8]>;
> +def VecI16
> + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old,
> DefaultMode],
> + [v32i16, v32i16, v64i16, v64i16, v32i16]>;
> +def VecI32
> + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old,
> DefaultMode],
> + [v16i32, v16i32, v32i32, v32i32, v16i32]>;
> +def VecI64
> + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old,
> DefaultMode],
> + [v8i64, v8i64, v16i64, v16i64, v8i64]>;
> +def VecPI8
> + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old,
> DefaultMode],
> + [v128i8, v128i8, v256i8, v256i8, v128i8]>;
> +def VecPI16
> + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old,
> DefaultMode],
> + [v64i16, v64i16, v128i16, v128i16, v64i16]>;
> +def VecPI32
> + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old,
> DefaultMode],
> + [v32i32, v32i32, v64i32, v64i32, v32i32]>;
> +def VecPI64
> + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old,
> DefaultMode],
> + [v16i64, v16i64, v32i64, v32i64, v16i64]>;
>
> // Register classes.
> //
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Wed Oct 18 11:07:07
> 2017
> @@ -53,14 +53,6 @@ static cl::opt<bool> EnableIEEERndNear("
> static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
> cl::Hidden, cl::ZeroOrMore, cl::init(true));
>
> -static cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double",
> - cl::Hidden, cl::ZeroOrMore, cl::init(false),
> - cl::desc("Enable Hexagon Double Vector eXtensions"));
> -
> -static cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx",
> - cl::Hidden, cl::ZeroOrMore, cl::init(false),
> - cl::desc("Enable Hexagon Vector eXtensions"));
> -
> static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
> cl::Hidden, cl::ZeroOrMore, cl::init(false));
>
> @@ -126,8 +118,8 @@ HexagonSubtarget::initializeSubtargetDep
> else
> llvm_unreachable("Unrecognized Hexagon processor version");
>
> - UseHVXOps = false;
> - UseHVXDblOps = false;
> + UseHVX128BOps = false;
> + UseHVX64BOps = false;
> UseLongCalls = false;
>
> UseMemOps = DisableMemOps ? false : EnableMemOps;
> @@ -136,10 +128,6 @@ HexagonSubtarget::initializeSubtargetDep
>
> ParseSubtargetFeatures(CPUString, FS);
>
> - if (EnableHexagonHVX.getPosition())
> - UseHVXOps = EnableHexagonHVX;
> - if (EnableHexagonHVXDouble.getPosition())
> - UseHVXDblOps = EnableHexagonHVXDouble;
> if (OverrideLongCalls.getPosition())
> UseLongCalls = OverrideLongCalls;
>
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h Wed Oct 18 11:07:07
> 2017
> @@ -46,12 +46,13 @@ class Triple;
> class HexagonSubtarget : public HexagonGenSubtargetInfo {
> virtual void anchor();
>
> - bool UseMemOps, UseHVXOps, UseHVXDblOps;
> + bool UseMemOps, UseHVX64BOps, UseHVX128BOps;
> bool UseLongCalls;
> bool ModeIEEERndNear;
>
> public:
> Hexagon::ArchEnum HexagonArchVersion;
> + Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::V4;
> /// True if the target should use Back-Skip-Back scheduling. This is the
> /// default for V60.
> bool UseBSBScheduling;
> @@ -138,9 +139,9 @@ public:
> }
>
> bool modeIEEERndNear() const { return ModeIEEERndNear; }
> - bool useHVXOps() const { return UseHVXOps; }
> - bool useHVXDblOps() const { return UseHVXOps && UseHVXDblOps; }
> - bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; }
> + bool useHVXOps() const { return HexagonHVXVersion >
> Hexagon::ArchEnum::V4; }
> + bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
> + bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
> bool useLongCalls() const { return UseLongCalls; }
> bool usePredicatedCalls() const;
>
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Wed
> Oct 18 11:07:07 2017
> @@ -288,7 +288,7 @@ MCSubtargetInfo *Hexagon_MC::createHexag
> }
>
> MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName,
> ArchFS);
> - if (X->getFeatureBits()[Hexagon::ExtensionHVXDbl]) {
> + if (X->getFeatureBits()[Hexagon::ExtensionHVX128B]) {
> llvm::FeatureBitset Features = X->getFeatureBits();
> X->setFeatureBits(Features.set(Hexagon::ExtensionHVX));
> }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll Wed Oct 18
> 11:07:07 2017
> @@ -187,7 +187,7 @@ entry:
> }
>
> attributes #0 = { nounwind readnone }
> -attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx" }
> +attributes #1 = { "target-cpu"="hexagonv60"
> "target-features"="+hvxv60,+hvx-length64b" }
> attributes #2 = { nounwind }
>
> !llvm.module.flags = !{!0}
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll Wed Oct 18 11:07:07
> 2017
> @@ -30,4 +30,4 @@ b9:
> ret i32 %v10
> }
>
> -attributes #0 = { nounwind optsize "target-cpu"="hexagonv60"
> "target-features"="-hvx-double,-long-calls" }
> +attributes #0 = { nounwind optsize "target-cpu"="hexagonv60"
> "target-features"="-hvxv60,-long-calls" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll Wed Oct 18
> 11:07:07 2017
> @@ -32,4 +32,4 @@ b0:
> ; Function Attrs: nounwind
> declare void @printf(i8* nocapture readonly, ...) local_unnamed_addr #0
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="-hvx,-long-calls" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll Wed Oct 18 11:07:07
> 2017
> @@ -14,4 +14,4 @@ entry:
> ret i32 %and2
> }
>
> -attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60"
> "target-features"="-hvx,-hvx-double" }
> +attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60"
> "target-features"="-hvx" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll Wed Oct 18 11:07:07 2017
> @@ -53,5 +53,5 @@ declare i32 @llvm.hexagon.A2.sath(i32) #
> declare i32 @llvm.hexagon.A2.satub(i32) #1
> declare i32 @llvm.hexagon.A2.satuh(i32) #1
>
> -attributes #0 = { nounwind readnone "target-cpu"="hexagonv60"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { nounwind readnone "target-cpu"="hexagonv60"
> "target-features"="-hvx,-long-calls" }
> attributes #1 = { nounwind readnone }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll Wed Oct 18 11:07:07
> 2017
> @@ -19,5 +19,5 @@ b5:
>
> declare double @fabs(double) #1
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="-hvx,-long-calls" }
> +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60"
> "target-features"="-hvx,-long-calls" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll Wed Oct 18 11:07:07 2017
> @@ -72,4 +72,4 @@ entry:
> ret i32 %bf.ashr
> }
>
> -attributes #0 = { noinline norecurse nounwind readnone
> "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { noinline norecurse nounwind readnone
> "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/bit-has.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-has.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/bit-has.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/bit-has.ll Wed Oct 18 11:07:07 2017
> @@ -60,5 +60,5 @@ b23:
>
> declare i32 @llvm.hexagon.A2.sath(i32) #1
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv5"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv5"
> "target-features"="-hvx,-long-calls" }
> attributes #1 = { nounwind readnone }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll Wed Oct 18
> 11:07:07 2017
> @@ -24,7 +24,7 @@ for.end:
> declare hidden i64 @danny(i32*, i32* nocapture readonly
> dereferenceable(4)) #1 align 2
> declare hidden i32 @sammy(i32* nocapture, i32) #0 align 2
>
> -attributes #0 = { nounwind optsize "disable-tail-calls"="false"
> "less-precise-fpmad"="false" "no-frame-pointer-elim"="true"
> "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
> "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> -attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false"
> "less-precise-fpmad"="false" "no-frame-pointer-elim"="true"
> "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
> "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> +attributes #0 = { nounwind optsize "disable-tail-calls"="false"
> "less-precise-fpmad"="false" "no-frame-pointer-elim"="true"
> "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
> "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> +attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false"
> "less-precise-fpmad"="false" "no-frame-pointer-elim"="true"
> "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
> "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> attributes #2 = { optsize }
>
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll Wed Oct 18 11:07:07 2017
> @@ -190,7 +190,7 @@ declare i64 @llvm.hexagon.M2.mpyd.ll.s1(
> declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
> declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
>
> -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false"
> "use-soft-float"="false" }
> +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,,+hvx-length64b" "unsafe-fp-math"="false"
> "use-soft-float"="false" }
> attributes #1 = { argmemonly nounwind }
> attributes #2 = { nounwind readnone }
>
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll Wed Oct 18
> 11:07:07 2017
> @@ -24,4 +24,4 @@ entry:
>
>
> attributes #0 = { nounwind readnone }
> -attributes #1 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,+hvx-double" }
> +attributes #1 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,+hvx-length128b" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll Wed Oct 18
> 11:07:07 2017
> @@ -17,5 +17,5 @@ entry:
> ; Function Attrs: nounwind readnone
> declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvxv60,+hvx-length64b" }
> attributes #1 = { nounwind readnone }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll Wed Oct 18 11:07:07
> 2017
> @@ -39,6 +39,6 @@ b14:
>
> declare i32 @bar(i32) local_unnamed_addr #0
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,-hvx-double,-long-calls" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvxv60,+hvx-length64b,-long-calls" }
>
> !0 = !{!"branch_weights", i32 1, i32 2000}
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll Wed Oct 18
> 11:07:07 2017
> @@ -68,4 +68,4 @@ b19:
> unreachable
> }
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv55"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv55"
> "target-features"="-hvx,-long-calls" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll Wed Oct 18 11:07:07 2017
> @@ -39,5 +39,5 @@ declare i8* @__cxa_begin_catch(i8*)
>
> declare void @__cxa_end_catch()
>
> -attributes #0 = { "disable-tail-calls"="false"
> "less-precise-fpmad"="false" "no-frame-pointer-elim"="true"
> "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-jump-tables"="false" "no-nans-fp-math"="false"
> "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60"
> "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false"
> "use-soft-float"="false" }
> +attributes #0 = { "disable-tail-calls"="false"
> "less-precise-fpmad"="false" "no-frame-pointer-elim"="true"
> "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-jump-tables"="false" "no-nans-fp-math"="false"
> "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60"
> "target-features"="-hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }
> attributes #1 = { nounwind }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll Wed Oct 18
> 11:07:07 2017
> @@ -17,4 +17,4 @@ entry:
> ret i16 %a
> }
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="-hvx-double,-long-calls" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="-hvx,-long-calls" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll Wed Oct 18 11:07:07
> 2017
> @@ -1,6 +1,6 @@
> -; RUN: llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic < %s |
> FileCheck %s
> +; RUN: opt -relocation-model pic -march=hexagon -mcpu=hexagonv60 -O2 -S <
> %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic
>
> -; CHECK: @PCREL
> +; CHECK: jumpr
>
> target datalayout =
> "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
> target triple = "hexagon-unknown--elf"
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll Wed Oct 18
> 11:07:07 2017
> @@ -103,8 +103,8 @@ declare i32 @llvm.hexagon.S2.asr.r.r.sat
> declare i32 @llvm.hexagon.A2.aslh(i32) #2
> declare void @foo(i16*, i32*, i16*, i16 signext, i16 signext, i16
> signext) local_unnamed_addr #3
>
> -attributes #0 = { nounwind optsize "target-cpu"="hexagonv55"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { nounwind optsize "target-cpu"="hexagonv55"
> "target-features"="-hvx,-long-calls" }
> attributes #1 = { argmemonly nounwind }
> attributes #2 = { nounwind readnone }
> -attributes #3 = { optsize "target-cpu"="hexagonv55"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #3 = { optsize "target-cpu"="hexagonv55"
> "target-features"="-hvx,-long-calls" }
> attributes #4 = { nounwind optsize }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll Wed Oct 18
> 11:07:07 2017
> @@ -14,4 +14,4 @@ entry:
> declare <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32>, <32 x i32>)
> declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>,
> <32 x i32>)
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx-double" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvxv60,+hvx-length128b" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll Wed Oct 18
> 11:07:07 2017
> @@ -1,4 +1,4 @@
> -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
> +; RUN: llc -O2 -march=hexagon -mcpu=hexagonv62< %s | FileCheck %s
> ; CHECK: ParseFunc:
> ; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]])
> ; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]]
> @@ -126,6 +126,7 @@ sw.epilog:
> ; Function Attrs: nounwind
> declare void @snprintf(i8* nocapture, i32, i8* nocapture readonly, ...)
> local_unnamed_addr #1
>
> -attributes #0 = { nounwind
> "correctly-rounded-divide-sqrt-fp-math"="false"
> "disable-tail-calls"="false" "less-precise-fpmad"="false"
> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
> "no-infs-fp-math"="false" "no-jump-tables"="false"
> "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false"
> "stack-protector-buffer-size"="8" "target-features"="+hvx"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> -attributes #1 = { nounwind
> "correctly-rounded-divide-sqrt-fp-math"="false"
> "disable-tail-calls"="false" "less-precise-fpmad"="false"
> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
> "no-infs-fp-math"="false" "no-nans-fp-math"="false"
> "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8"
> "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }
> +attributes #0 = { nounwind
> "correctly-rounded-divide-sqrt-fp-math"="false"
> "disable-tail-calls"="false" "less-precise-fpmad"="false"
> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
> "no-infs-fp-math"="false" "no-jump-tables"="false"
> "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false"
> "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62"
> "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false"
> "use-soft-float"="false" }
> +attributes #1 = { nounwind
> "correctly-rounded-divide-sqrt-fp-math"="false"
> "disable-tail-calls"="false" "less-precise-fpmad"="false"
> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
> "no-infs-fp-math"="false" "no-nans-fp-math"="false"
> "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8"
> "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> attributes #2 = { nounwind }
> +
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll Wed Oct 18
> 11:07:07 2017
> @@ -82,7 +82,7 @@ declare i64 @llvm.hexagon.A2.addp(i64, i
> declare i64 @llvm.hexagon.A2.subp(i64, i64) #1
> <https://maps.google.com/?q=i64,+i64)+%231&entry=gmail&source=g>
> declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
>
> -attributes #0 = { nounwind readonly "target-cpu"="hexagonv60"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { nounwind readonly "target-cpu"="hexagonv60"
> "target-features"="-hvx,-long-calls" }
> attributes #1 = { nounwind readnone }
>
> !0 = !{!1, !1, i64
> <https://maps.google.com/?q=1,+i64&entry=gmail&source=g> 0}
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll Wed Oct 18 11:07:07
> 2017
> @@ -66,4 +66,4 @@ for.end:
> ret void
> }
>
> -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,-hvx-double" }
> +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvxv60,+hvx-length64b" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll Wed Oct 18
> 11:07:07 2017
> @@ -31,7 +31,7 @@ b5:
> declare <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1
> declare <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1>) #1
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,+hvx-double" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,+hvx-length128b" }
> attributes #1 = { nounwind readnone }
> attributes #2 = { nounwind }
>
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll Wed Oct 18
> 11:07:07 2017
> @@ -139,5 +139,5 @@ declare <64 x i32> @llvm.hexagon.V6.vmpy
>
> declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,+hvx-double" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,+hvx-length128b" }
> attributes #1 = { nounwind readnone }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll Wed Oct 18
> 11:07:07 2017
> @@ -51,4 +51,4 @@ b23:
> ret void
> }
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv5"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv5"
> "target-features"="-hvx,-long-calls" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll Wed Oct
> 18 11:07:07 2017
> @@ -42,4 +42,4 @@ b20:
> br label %b1
> }
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv55"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv55"
> "target-features"="-hvx,-long-calls" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll Wed Oct 18
> 11:07:07 2017
> @@ -48,6 +48,6 @@ declare <32 x i32> @llvm.hexagon.V6.hi.1
> declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #2
> declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x
> i32>, i32) #2
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx" }
> -attributes #1 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx-double" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvxv60,+hvx-length64b" }
> +attributes #1 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvxv60,+hvx-length128b" }
> attributes #2 = { nounwind readnone }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll Wed Oct 18
> 11:07:07 2017
> @@ -91,5 +91,5 @@ b22:
>
> attributes #0 = { nounwind }
> attributes #1 = { nounwind readnone }
> -attributes #2 = { nounwind "reciprocal-estimates"="none"
> "target-cpu"="hexagonv60" "target-features"="+hvx-double" }
> +attributes #2 = { nounwind "reciprocal-estimates"="none"
> "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
> attributes #3 = { nobuiltin nounwind }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll Wed Oct 18
> 11:07:07 2017
> @@ -210,7 +210,7 @@ b34:
> br i1 %v146, label %b33, label %b34
> }
>
> -attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx-double" }
> +attributes #0 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvxv60,+hvx-length128b" }
> attributes #1 = { nounwind readnone }
> attributes #2 = { nounwind }
> attributes #3 = { nobuiltin nounwind }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll Wed Oct 18 11:07:07
> 2017
> @@ -76,4 +76,4 @@ b21:
> br i1 %v23, label %b13, label %b10
> }
>
> -attributes #0 = { norecurse "target-cpu"="hexagonv60"
> "target-features"="-hvx,-hvx-double,-long-calls" }
> +attributes #0 = { norecurse "target-cpu"="hexagonv60"
> "target-features"="-hvx,-long-calls" }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/fminmax.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/fminmax.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/fminmax.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/fminmax.ll Wed Oct 18 11:07:07 2017
> @@ -22,6 +22,6 @@ entry:
> declare float @fminf(float, float) #0
> declare float @fmaxf(float, float) #0
>
> -attributes #0 = { nounwind readnone "disable-tail-calls"="false"
> "less-precise-fpmad"="false" "no-frame-pointer-elim"="true"
> "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
> "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> +attributes #0 = { nounwind readnone "disable-tail-calls"="false"
> "less-precise-fpmad"="false" "no-frame-pointer-elim"="true"
> "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
> "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> attributes #1 = { nounwind readnone }
>
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll Wed Oct 18
> 11:07:07 2017
> @@ -156,7 +156,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmpa
> declare <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32>, <16 x i32>,
> i32) #0
>
> attributes #0 = { nounwind readnone }
> -attributes #1 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvx,-hvx-double" }
> +attributes #1 = { nounwind "target-cpu"="hexagonv60"
> "target-features"="+hvxv60,+hvx-length64b" }
>
> !1 = !{!2, !2, i64
> <https://maps.google.com/?q=2,+i64&entry=gmail&source=g> 0}
> !2 = !{!"omnipotent char", !3, i64
> <https://maps.google.com/?q=3,+i64&entry=gmail&source=g> 0}
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll Wed Oct 18 11:07:07
> 2017
> @@ -18,7 +18,7 @@ entry:
> ; Function Attrs: nounwind readnone speculatable
> declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
>
> -attributes #0 = { nounwind "disable-tail-calls"="true"
> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
> "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5"
> "target-features"="-hvx-double,-long-calls" }
> +attributes #0 = { nounwind "disable-tail-calls"="true"
> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
> "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5"
> "target-features"="-hvx,-long-calls" }
> attributes #1 = { nounwind readnone speculatable }
>
> !llvm.dbg.cu = !{!0}
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll Wed Oct 18 11:07:07
> 2017
> @@ -19,7 +19,7 @@ entry:
> ; Function Attrs: nounwind readnone speculatable
> declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
>
> -attributes #0 = { nounwind "disable-tail-calls"="true"
> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
> "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5"
> "target-features"="-hvx-double,-long-calls" }
> +attributes #0 = { nounwind "disable-tail-calls"="true"
> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
> "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5"
> "target-features"=",-hvx,-long-calls" }
> attributes #1 = { nounwind readnone speculatable }
>
> !llvm.dbg.cu = !{!0}
>
> Modified:
> llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll?rev=316101&r1=316100&r2=316101&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll
> (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll
> Wed Oct 18 11:07:07 2017
> @@ -73,7 +73,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmax
> ; Function Attrs: nounwind readnone
> declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>,
> i32) #1
>
> -attributes #0 = { nounwind
> "correctly-rounded-divide-sqrt-fp-math"="false"
> "disable-tail-calls"="false" "less-precise-fpmad"="false"
> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
> "no-infs-fp-math"="false" "no-jump-tables"="false"
> "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false"
> "no-trapping-math"="false" "stack-protector-buffer-size"="8"
> "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> +attributes #0 = { nounwind
> "correctly-rounded-divide-sqrt-fp-math"="false"
> "disable-tail-calls"="false" "less-precise-fpmad"="false"
> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
> "no-infs-fp-math"="false" "no-jump-tables"="false"
> "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false"
> "no-trapping-math"="false" "stack-protector-buffer-size"="8"
> "target-cpu"="hexagonv60"
> "target-features"="+hvx,+hvx-length128b,-long-calls"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> attributes #1 = { nounwind readnone }
>
> !llvm.ident = !{!0}
>
> Modified:
> llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll?rev=316101&r1=316100&r2=316101&view=diff
> ===================================
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