<div dir="ltr">Hey Sumanth, this change seems to have broken a number of buildbots, e.g. <a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/8887/steps/check-clang%20asan/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/8887/steps/check-clang%20asan/logs/stdio</a></div><br><div class="gmail_quote"><div dir="ltr">On Wed, Oct 18, 2017 at 11:07 AM Sumanth Gundapaneni via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: sgundapa<br>
Date: Wed Oct 18 11:07:07 2017<br>
New Revision: 316101<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=316101&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=316101&view=rev</a><br>
Log:<br>
[Hexagon] New HVX target features.<br>
<br>
This patch lets the llvm tools handle the new HVX target features that<br>
are added by frontend (clang). The target-features are of the form<br>
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.<br>
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.<br>
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.<br>
Eg: "+hvxv62"<br>
<br>
For the correct HVX code generation, the user must use the following<br>
target features.<br>
For 64B mode: "+hvxv62" "+hvx-length64b"<br>
For 128B mode: "+hvxv62" "+hvx-length128b"<br>
<br>
Clang picks a default length if none is specified. If for some reason,<br>
no hvx-length is specified to llvm, the compilation will bail out.<br>
There is a corresponding clang patch.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D38851" rel="noreferrer" target="_blank">https://reviews.llvm.org/D38851</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/Hexagon.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp<br>
llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll<br>
llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll<br>
llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll<br>
llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll<br>
llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll<br>
llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll<br>
llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll<br>
llvm/trunk/test/CodeGen/Hexagon/bit-has.ll<br>
llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll<br>
llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll<br>
llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll<br>
llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll<br>
llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll<br>
llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll<br>
llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll<br>
llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll<br>
llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll<br>
llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll<br>
llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll<br>
llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll<br>
llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll<br>
llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll<br>
llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll<br>
llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll<br>
llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll<br>
llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll<br>
llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll<br>
llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll<br>
llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll<br>
llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll<br>
llvm/trunk/test/CodeGen/Hexagon/fminmax.ll<br>
llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll<br>
llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll<br>
llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll<br>
llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll<br>
llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll<br>
llvm/trunk/test/CodeGen/Hexagon/hvx-nontemporal.ll<br>
llvm/trunk/test/CodeGen/Hexagon/hwloop-noreturn-call.ll<br>
llvm/trunk/test/CodeGen/Hexagon/hwloop-preh.ll<br>
llvm/trunk/test/CodeGen/Hexagon/inline-asm-qv.ll<br>
llvm/trunk/test/CodeGen/Hexagon/inline-asm-vecpred128.ll<br>
llvm/trunk/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll<br>
llvm/trunk/test/CodeGen/Hexagon/intrinsics/byte-store.ll<br>
llvm/trunk/test/CodeGen/Hexagon/intrinsics/system_user.ll<br>
llvm/trunk/test/CodeGen/Hexagon/jt-in-text.ll<br>
llvm/trunk/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll<br>
llvm/trunk/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll<br>
llvm/trunk/test/CodeGen/Hexagon/loop-prefetch.ll<br>
llvm/trunk/test/CodeGen/Hexagon/lower-extract-subvector.ll<br>
llvm/trunk/test/CodeGen/Hexagon/memops-stack.ll<br>
llvm/trunk/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll<br>
llvm/trunk/test/CodeGen/Hexagon/multi-cycle.ll<br>
llvm/trunk/test/CodeGen/Hexagon/newify-crash.ll<br>
llvm/trunk/test/CodeGen/Hexagon/newvaluejump3.ll<br>
llvm/trunk/test/CodeGen/Hexagon/peephole-kill-flags.ll<br>
llvm/trunk/test/CodeGen/Hexagon/plt-rel.ll<br>
llvm/trunk/test/CodeGen/Hexagon/post-inc-aa-metadata.ll<br>
llvm/trunk/test/CodeGen/Hexagon/propagate-vcombine.ll<br>
llvm/trunk/test/CodeGen/Hexagon/rdf-def-mask.ll<br>
llvm/trunk/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll<br>
llvm/trunk/test/CodeGen/Hexagon/rdf-inline-asm.ll<br>
llvm/trunk/test/CodeGen/Hexagon/reg-scavengebug-3.ll<br>
llvm/trunk/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll<br>
llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir<br>
llvm/trunk/test/CodeGen/Hexagon/regalloc-block-overlap.ll<br>
llvm/trunk/test/CodeGen/Hexagon/select-instr-align.ll<br>
llvm/trunk/test/CodeGen/Hexagon/stack-align-reset.ll<br>
llvm/trunk/test/CodeGen/Hexagon/store-shift.ll<br>
llvm/trunk/test/CodeGen/Hexagon/switch-lut-explicit-section.ll<br>
llvm/trunk/test/CodeGen/Hexagon/switch-lut-function-section.ll<br>
llvm/trunk/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll<br>
llvm/trunk/test/CodeGen/Hexagon/switch-lut-text-section.ll<br>
llvm/trunk/test/CodeGen/Hexagon/undo-dag-shift.ll<br>
llvm/trunk/test/CodeGen/Hexagon/v60-cur.ll<br>
llvm/trunk/test/CodeGen/Hexagon/v60-vsel1.ll<br>
llvm/trunk/test/CodeGen/Hexagon/v60Intrins.ll<br>
llvm/trunk/test/CodeGen/Hexagon/v60Vasr.ll<br>
llvm/trunk/test/CodeGen/Hexagon/v60small.ll<br>
llvm/trunk/test/CodeGen/Hexagon/v6vec-vprint.ll<br>
llvm/trunk/test/CodeGen/Hexagon/vassign-to-combine.ll<br>
llvm/trunk/test/CodeGen/Hexagon/vdmpy-halide-test.ll<br>
llvm/trunk/test/CodeGen/Hexagon/vec-pred-spill1.ll<br>
llvm/trunk/test/CodeGen/Hexagon/vec-vararg-align.ll<br>
llvm/trunk/test/CodeGen/Hexagon/vector-align.ll<br>
llvm/trunk/test/CodeGen/Hexagon/vload-postinc-sel.ll<br>
llvm/trunk/test/CodeGen/Hexagon/vmpa-halide-test.ll<br>
llvm/trunk/test/CodeGen/Hexagon/vpack_eo.ll<br>
llvm/trunk/test/CodeGen/Hexagon/vselect-pseudo.ll<br>
llvm/trunk/test/MC/Hexagon/align.s<br>
llvm/trunk/test/MC/Hexagon/double-vector-producer.s<br>
llvm/trunk/test/MC/Hexagon/test.s<br>
llvm/trunk/test/MC/Hexagon/v60-alu.s<br>
llvm/trunk/test/MC/Hexagon/v60-misc.s<br>
llvm/trunk/test/MC/Hexagon/v60-permute.s<br>
llvm/trunk/test/MC/Hexagon/v60-shift.s<br>
llvm/trunk/test/MC/Hexagon/v60-vcmp.s<br>
llvm/trunk/test/MC/Hexagon/v60-vmem.s<br>
llvm/trunk/test/MC/Hexagon/v60-vmpy-acc.s<br>
llvm/trunk/test/MC/Hexagon/v60-vmpy1.s<br>
llvm/trunk/test/MC/Hexagon/v60lookup.s<br>
llvm/trunk/test/MC/Hexagon/v62_all.s<br>
llvm/trunk/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll<br>
llvm/trunk/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Wed Oct 18 11:07:07 2017<br>
@@ -25,10 +25,31 @@ include "llvm/Target/Target.td"<br>
include "HexagonDepArch.td"<br>
<br>
// Hexagon ISA Extensions<br>
-def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true",<br>
- "Hexagon HVX instructions">;<br>
-def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true",<br>
- "Hexagon HVX Double instructions">;<br>
+def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",<br>
+ "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;<br>
+def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",<br>
+ "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",<br>
+ [ExtensionHVXV60]>;<br>
+def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",<br>
+ "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",<br>
+ [ExtensionHVXV60,<br>
+ ExtensionHVXV62]>;<br>
+def ExtensionHVX64B<br>
+ : SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true",<br>
+ "Hexagon HVX 64B instructions",<br>
+ [ExtensionHVXV60, ExtensionHVXV62]>;<br>
+def ExtensionHVX128B<br>
+ : SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true",<br>
+ "Hexagon HVX 128B instructions",<br>
+ [ExtensionHVXV60, ExtensionHVXV62]>;<br>
+<br>
+// This is an alias to ExtensionHVX128B to accept the hvx-double as<br>
+// an acceptable subtarget feature.<br>
+def ExtensionHVXDbl<br>
+ : SubtargetFeature<"hvx-double", "UseHVX128BOps", "true",<br>
+ "Hexagon HVX 128B instructions",<br>
+ [ExtensionHVXV60, ExtensionHVXV62]>;<br>
+<br>
def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",<br>
"Use constant-extended calls">;<br>
<br>
@@ -38,14 +59,21 @@ def FeatureLongCalls: SubtargetFeature<"<br>
<br>
def UseMEMOP : Predicate<"HST->useMemOps()">;<br>
def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">;<br>
-def UseHVXDbl : Predicate<"HST->useHVXDblOps()">,<br>
- AssemblerPredicate<"ExtensionHVXDbl">;<br>
-def UseHVXSgl : Predicate<"HST->useHVXSglOps()">;<br>
-def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">,<br>
- AssemblerPredicate<"ExtensionHVX">;<br>
-<br>
-def Hvx64 : HwMode<"+hvx,-hvx-double">;<br>
-def Hvx128 : HwMode<"+hvx,+hvx-double">;<br>
+def UseHVX64B : Predicate<"HST->useHVX64BOps()">,<br>
+ AssemblerPredicate<"ExtensionHVX64B">;<br>
+def UseHVX128B : Predicate<"HST->useHVX128BOps()">,<br>
+ AssemblerPredicate<"ExtensionHVX128B">;<br>
+def UseHVX : Predicate<"HST->useHVXOps()">,<br>
+ AssemblerPredicate<"ExtensionHVXV60">;<br>
+def UseHVXV60 : Predicate<"HST->useHVXOps()">,<br>
+ AssemblerPredicate<"ExtensionHVXV60">;<br>
+def UseHVXV62 : Predicate<"HST->useHVXOps()">,<br>
+ AssemblerPredicate<"ExtensionHVXV62">;<br>
+<br>
+def Hvx64 : HwMode<"+hvx-length64b">;<br>
+def Hvx64old : HwMode<"-hvx-double">;<br>
+def Hvx128 : HwMode<"+hvx-length128b">;<br>
+def Hvx128old : HwMode<"+hvx-double">;<br>
<br>
//===----------------------------------------------------------------------===//<br>
// Classes used for relation maps.<br>
@@ -274,9 +302,9 @@ def : Proc<"hexagonv5", HexagonModelV4,<br>
def : Proc<"hexagonv55", HexagonModelV55,<br>
[ArchV4, ArchV5, ArchV55]>;<br>
def : Proc<"hexagonv60", HexagonModelV60,<br>
- [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>;<br>
+ [ArchV4, ArchV5, ArchV55, ArchV60]>;<br>
def : Proc<"hexagonv62", HexagonModelV62,<br>
- [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ExtensionHVX]>;<br>
+ [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62]>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
// Declare the target which we are implementing<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Oct 18 11:07:07 2017<br>
@@ -357,7 +357,7 @@ static bool CC_HexagonVector(unsigned Va<br>
auto &MF = State.getMachineFunction();<br>
auto &HST = MF.getSubtarget<HexagonSubtarget>();<br>
<br>
- if (HST.useHVXSglOps() &&<br>
+ if (HST.useHVX64BOps() &&<br>
(LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||<br>
LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {<br>
if (unsigned Reg = State.AllocateReg(VecLstS)) {<br>
@@ -368,7 +368,7 @@ static bool CC_HexagonVector(unsigned Va<br>
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));<br>
return false;<br>
}<br>
- if (HST.useHVXSglOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 ||<br>
+ if (HST.useHVX64BOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 ||<br>
LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) {<br>
if (unsigned Reg = State.AllocateReg(VecLstD)) {<br>
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));<br>
@@ -379,8 +379,8 @@ static bool CC_HexagonVector(unsigned Va<br>
return false;<br>
}<br>
// 128B Mode<br>
- if (HST.useHVXDblOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 ||<br>
- LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) {<br>
+ if (HST.useHVX128BOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 ||<br>
+ LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) {<br>
if (unsigned Reg = State.AllocateReg(VecLstD)) {<br>
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));<br>
return false;<br>
@@ -389,7 +389,7 @@ static bool CC_HexagonVector(unsigned Va<br>
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));<br>
return false;<br>
}<br>
- if (HST.useHVXDblOps() &&<br>
+ if (HST.useHVX128BOps() &&<br>
(LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||<br>
LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {<br>
if (unsigned Reg = State.AllocateReg(VecLstS)) {<br>
@@ -437,7 +437,7 @@ static bool RetCC_Hexagon(unsigned ValNo<br>
LocInfo = CCValAssign::Full;<br>
} else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||<br>
LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||<br>
- (LocVT == MVT::v1024i1 && HST.useHVXDblOps())) {<br>
+ (LocVT == MVT::v1024i1 && HST.useHVX128BOps())) {<br>
LocVT = MVT::v32i32;<br>
ValVT = MVT::v32i32;<br>
LocInfo = CCValAssign::Full;<br>
@@ -507,7 +507,7 @@ static bool RetCC_HexagonVector(unsigned<br>
return false;<br>
}<br>
} else if (LocVT == MVT::v32i32) {<br>
- unsigned Req = HST.useHVXDblOps() ? Hexagon::V0 : Hexagon::W0;<br>
+ unsigned Req = HST.useHVX128BOps() ? Hexagon::V0 : Hexagon::W0;<br>
if (unsigned Reg = State.AllocateReg(Req)) {<br>
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));<br>
return false;<br>
@@ -827,9 +827,9 @@ HexagonTargetLowering::LowerCall(TargetL<br>
DEBUG(dbgs() << "Function needs byte stack align due to call args\n");<br>
// V6 vectors passed by value have 64 or 128 byte alignment depending<br>
// on whether we are 64 byte vector mode or 128 byte.<br>
- bool UseHVXDbl = Subtarget.useHVXDblOps();<br>
+ bool UseHVX128B = Subtarget.useHVX128BOps();<br>
assert(Subtarget.useHVXOps());<br>
- const unsigned ObjAlign = UseHVXDbl ? 128 : 64;<br>
+ const unsigned ObjAlign = UseHVX128B ? 128 : 64;<br>
LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);<br>
MFI.ensureMaxAlignment(LargestAlignSeen);<br>
}<br>
@@ -940,15 +940,15 @@ static bool getIndexedAddressParts(SDNod<br>
<br>
auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());<br>
<br>
- bool ValidHVXDblType =<br>
- HST.useHVXDblOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 ||<br>
- VT == MVT::v64i16 || VT == MVT::v128i8);<br>
+ bool ValidHVX128BType =<br>
+ HST.useHVX128BOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 ||<br>
+ VT == MVT::v64i16 || VT == MVT::v128i8);<br>
bool ValidHVXType =<br>
- HST.useHVXSglOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 ||<br>
+ HST.useHVX64BOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 ||<br>
VT == MVT::v32i16 || VT == MVT::v64i8);<br>
<br>
- if (ValidHVXDblType || ValidHVXType ||<br>
- VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {<br>
+ if (ValidHVX128BType || ValidHVXType || VT == MVT::i64 || VT == MVT::i32 ||<br>
+ VT == MVT::i16 || VT == MVT::i8) {<br>
IsInc = (Ptr->getOpcode() == ISD::ADD);<br>
Base = Ptr->getOperand(0);<br>
Offset = Ptr->getOperand(1);<br>
@@ -1182,7 +1182,7 @@ SDValue HexagonTargetLowering::LowerForm<br>
RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);<br>
RegInfo.addLiveIn(VA.getLocReg(), VReg);<br>
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));<br>
- } else if (Subtarget.useHVXDblOps() &&<br>
+ } else if (Subtarget.useHVX128BOps() &&<br>
((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||<br>
RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {<br>
unsigned VReg =<br>
@@ -1197,7 +1197,7 @@ SDValue HexagonTargetLowering::LowerForm<br>
RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);<br>
RegInfo.addLiveIn(VA.getLocReg(), VReg);<br>
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));<br>
- } else if (Subtarget.useHVXDblOps() &&<br>
+ } else if (Subtarget.useHVX128BOps() &&<br>
((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||<br>
RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {<br>
unsigned VReg =<br>
@@ -1743,7 +1743,7 @@ HexagonTargetLowering::HexagonTargetLowe<br>
}<br>
<br>
if (Subtarget.hasV60TOps()) {<br>
- if (Subtarget.useHVXSglOps()) {<br>
+ if (Subtarget.useHVX64BOps()) {<br>
addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass);<br>
addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);<br>
addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);<br>
@@ -1753,7 +1753,7 @@ HexagonTargetLowering::HexagonTargetLowe<br>
addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);<br>
addRegisterClass(MVT::v16i64, &Hexagon::HvxWRRegClass);<br>
addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass);<br>
- } else if (Subtarget.useHVXDblOps()) {<br>
+ } else if (Subtarget.useHVX128BOps()) {<br>
addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass);<br>
addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass);<br>
addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass);<br>
@@ -1992,7 +1992,7 @@ HexagonTargetLowering::HexagonTargetLowe<br>
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);<br>
<br>
if (Subtarget.useHVXOps()) {<br>
- if (Subtarget.useHVXSglOps()) {<br>
+ if (Subtarget.useHVX64BOps()) {<br>
setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);<br>
setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom);<br>
setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom);<br>
@@ -2004,7 +2004,7 @@ HexagonTargetLowering::HexagonTargetLowe<br>
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom);<br>
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom);<br>
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);<br>
- } else if (Subtarget.useHVXDblOps()) {<br>
+ } else if (Subtarget.useHVX128BOps()) {<br>
setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom);<br>
setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);<br>
setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom);<br>
@@ -2082,13 +2082,13 @@ HexagonTargetLowering::HexagonTargetLowe<br>
setIndexedStoreAction(ISD::POST_INC, VT, Legal);<br>
}<br>
<br>
- if (Subtarget.useHVXSglOps()) {<br>
+ if (Subtarget.useHVX64BOps()) {<br>
for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,<br>
MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {<br>
setIndexedLoadAction(ISD::POST_INC, VT, Legal);<br>
setIndexedStoreAction(ISD::POST_INC, VT, Legal);<br>
}<br>
- } else if (Subtarget.useHVXDblOps()) {<br>
+ } else if (Subtarget.useHVX128BOps()) {<br>
for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64,<br>
MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) {<br>
setIndexedLoadAction(ISD::POST_INC, VT, Legal);<br>
@@ -2353,8 +2353,8 @@ HexagonTargetLowering::LowerVECTOR_SHUFF<br>
size_t MaskLen = Mask.size();<br>
unsigned SizeInBits = VT.getScalarSizeInBits() * MaskLen;<br>
<br>
- if ((Subtarget.useHVXSglOps() && SizeInBits == 64 * 8) ||<br>
- (Subtarget.useHVXDblOps() && SizeInBits == 128 * 8)) {<br>
+ if ((Subtarget.useHVX64BOps() && SizeInBits == 64 * 8) ||<br>
+ (Subtarget.useHVX128BOps() && SizeInBits == 128 * 8)) {<br>
StridedLoadKind Pattern = isStridedLoad(Mask);<br>
if (Pattern == StridedLoadKind::NoPattern)<br>
return SDValue();<br>
@@ -2617,11 +2617,11 @@ HexagonTargetLowering::LowerCONCAT_VECTO<br>
return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0);<br>
<br>
if (UseHVX) {<br>
- assert((Width == 64*8 && Subtarget.useHVXSglOps()) ||<br>
- (Width == 128*8 && Subtarget.useHVXDblOps()));<br>
+ assert((Width == 64 * 8 && Subtarget.useHVX64BOps()) ||<br>
+ (Width == 128 * 8 && Subtarget.useHVX128BOps()));<br>
SDValue Vec1 = Op.getOperand(1);<br>
- MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32;<br>
- MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32;<br>
+ MVT OpTy = Subtarget.useHVX64BOps() ? MVT::v16i32 : MVT::v32i32;<br>
+ MVT ReTy = Subtarget.useHVX64BOps() ? MVT::v32i32 : MVT::v64i32;<br>
SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);<br>
SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);<br>
SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);<br>
@@ -2667,7 +2667,7 @@ HexagonTargetLowering::LowerEXTRACT_SUBV<br>
EVT VT = Op.getOperand(0).getValueType();<br>
SDLoc dl(Op);<br>
bool UseHVX = Subtarget.useHVXOps();<br>
- bool UseHVXSgl = Subtarget.useHVXSglOps();<br>
+ bool UseHVX64B = Subtarget.useHVX64BOps();<br>
// Just in case...<br>
<br>
if (!VT.isVector() || !UseHVX)<br>
@@ -2675,7 +2675,7 @@ HexagonTargetLowering::LowerEXTRACT_SUBV<br>
<br>
EVT ResVT = Op.getValueType();<br>
unsigned ResSize = ResVT.getSizeInBits();<br>
- unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8);<br>
+ unsigned VectorSizeInBits = UseHVX64B ? (64 * 8) : (128 * 8);<br>
unsigned OpSize = VT.getSizeInBits();<br>
<br>
// We deal only with cases where the result is the vector size<br>
@@ -3001,7 +3001,7 @@ HexagonTargetLowering::getRegForInlineAs<br>
case 512:<br>
return std::make_pair(0U, &Hexagon::HvxVRRegClass);<br>
case 1024:<br>
- if (Subtarget.hasV60TOps() && Subtarget.useHVXDblOps())<br>
+ if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps())<br>
return std::make_pair(0U, &Hexagon::HvxVRRegClass);<br>
return std::make_pair(0U, &Hexagon::HvxWRRegClass);<br>
case 2048:<br>
@@ -3204,7 +3204,7 @@ HexagonTargetLowering::findRepresentativ<br>
case MVT::v32i32:<br>
case MVT::v16i64:<br>
if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&<br>
- Subtarget.useHVXDblOps())<br>
+ Subtarget.useHVX128BOps())<br>
RRC = &Hexagon::HvxVRRegClass;<br>
else<br>
RRC = &Hexagon::HvxWRRegClass;<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td Wed Oct 18 11:07:07 2017<br>
@@ -427,7 +427,7 @@ class LDrivv_template<RegisterClass RC,<br>
def PS_vloadrw_ai: LDrivv_template<HvxWR, V6_vL32b_ai>,<br>
Requires<[HasV60T,UseHVX]>;<br>
def PS_vloadrw_nt_ai: LDrivv_template<HvxWR, V6_vL32b_nt_ai>,<br>
- Requires<[HasV60T,UseHVXSgl]>;<br>
+ Requires<[HasV60T,UseHVX]>;<br>
def PS_vloadrwu_ai: LDrivv_template<HvxWR, V6_vL32Ub_ai>,<br>
Requires<[HasV60T,UseHVX]>;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Wed Oct 18 11:07:07 2017<br>
@@ -216,25 +216,33 @@ let Namespace = "Hexagon" in {<br>
<br>
// HVX types<br>
<br>
-def VecI1 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],<br>
- [v512i1, v1024i1, v512i1]>;<br>
-def VecI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],<br>
- [v64i8, v128i8, v64i8]>;<br>
-def VecI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],<br>
- [v32i16, v64i16, v32i16]>;<br>
-def VecI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],<br>
- [v16i32, v32i32, v16i32]>;<br>
-def VecI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],<br>
- [v8i64, v16i64, v8i64]>;<br>
-def VecPI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],<br>
- [v128i8, v256i8, v128i8]>;<br>
-def VecPI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],<br>
- [v64i16, v128i16, v64i16]>;<br>
-def VecPI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],<br>
- [v32i32, v64i32, v32i32]>;<br>
-def VecPI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],<br>
- [v16i64, v32i64, v16i64]>;<br>
-<br>
+def VecI1<br>
+ : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],<br>
+ [v512i1, v512i1, v1024i1, v1024i1, v512i1]>;<br>
+def VecI8<br>
+ : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],<br>
+ [v64i8, v64i8, v128i8, v128i8, v64i8]>;<br>
+def VecI16<br>
+ : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],<br>
+ [v32i16, v32i16, v64i16, v64i16, v32i16]>;<br>
+def VecI32<br>
+ : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],<br>
+ [v16i32, v16i32, v32i32, v32i32, v16i32]>;<br>
+def VecI64<br>
+ : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],<br>
+ [v8i64, v8i64, v16i64, v16i64, v8i64]>;<br>
+def VecPI8<br>
+ : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],<br>
+ [v128i8, v128i8, v256i8, v256i8, v128i8]>;<br>
+def VecPI16<br>
+ : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],<br>
+ [v64i16, v64i16, v128i16, v128i16, v64i16]>;<br>
+def VecPI32<br>
+ : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],<br>
+ [v32i32, v32i32, v64i32, v64i32, v32i32]>;<br>
+def VecPI64<br>
+ : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],<br>
+ [v16i64, v16i64, v32i64, v32i64, v16i64]>;<br>
<br>
// Register classes.<br>
//<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Wed Oct 18 11:07:07 2017<br>
@@ -53,14 +53,6 @@ static cl::opt<bool> EnableIEEERndNear("<br>
static cl::opt<bool> EnableBSBSched("enable-bsb-sched",<br>
cl::Hidden, cl::ZeroOrMore, cl::init(true));<br>
<br>
-static cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double",<br>
- cl::Hidden, cl::ZeroOrMore, cl::init(false),<br>
- cl::desc("Enable Hexagon Double Vector eXtensions"));<br>
-<br>
-static cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx",<br>
- cl::Hidden, cl::ZeroOrMore, cl::init(false),<br>
- cl::desc("Enable Hexagon Vector eXtensions"));<br>
-<br>
static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",<br>
cl::Hidden, cl::ZeroOrMore, cl::init(false));<br>
<br>
@@ -126,8 +118,8 @@ HexagonSubtarget::initializeSubtargetDep<br>
else<br>
llvm_unreachable("Unrecognized Hexagon processor version");<br>
<br>
- UseHVXOps = false;<br>
- UseHVXDblOps = false;<br>
+ UseHVX128BOps = false;<br>
+ UseHVX64BOps = false;<br>
UseLongCalls = false;<br>
<br>
UseMemOps = DisableMemOps ? false : EnableMemOps;<br>
@@ -136,10 +128,6 @@ HexagonSubtarget::initializeSubtargetDep<br>
<br>
ParseSubtargetFeatures(CPUString, FS);<br>
<br>
- if (EnableHexagonHVX.getPosition())<br>
- UseHVXOps = EnableHexagonHVX;<br>
- if (EnableHexagonHVXDouble.getPosition())<br>
- UseHVXDblOps = EnableHexagonHVXDouble;<br>
if (OverrideLongCalls.getPosition())<br>
UseLongCalls = OverrideLongCalls;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h Wed Oct 18 11:07:07 2017<br>
@@ -46,12 +46,13 @@ class Triple;<br>
class HexagonSubtarget : public HexagonGenSubtargetInfo {<br>
virtual void anchor();<br>
<br>
- bool UseMemOps, UseHVXOps, UseHVXDblOps;<br>
+ bool UseMemOps, UseHVX64BOps, UseHVX128BOps;<br>
bool UseLongCalls;<br>
bool ModeIEEERndNear;<br>
<br>
public:<br>
Hexagon::ArchEnum HexagonArchVersion;<br>
+ Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::V4;<br>
/// True if the target should use Back-Skip-Back scheduling. This is the<br>
/// default for V60.<br>
bool UseBSBScheduling;<br>
@@ -138,9 +139,9 @@ public:<br>
}<br>
<br>
bool modeIEEERndNear() const { return ModeIEEERndNear; }<br>
- bool useHVXOps() const { return UseHVXOps; }<br>
- bool useHVXDblOps() const { return UseHVXOps && UseHVXDblOps; }<br>
- bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; }<br>
+ bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }<br>
+ bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }<br>
+ bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }<br>
bool useLongCalls() const { return UseLongCalls; }<br>
bool usePredicatedCalls() const;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Wed Oct 18 11:07:07 2017<br>
@@ -288,7 +288,7 @@ MCSubtargetInfo *Hexagon_MC::createHexag<br>
}<br>
<br>
MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);<br>
- if (X->getFeatureBits()[Hexagon::ExtensionHVXDbl]) {<br>
+ if (X->getFeatureBits()[Hexagon::ExtensionHVX128B]) {<br>
llvm::FeatureBitset Features = X->getFeatureBits();<br>
X->setFeatureBits(Features.set(Hexagon::ExtensionHVX));<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/SUnit-boundary-prob.ll Wed Oct 18 11:07:07 2017<br>
@@ -187,7 +187,7 @@ entry:<br>
}<br>
<br>
attributes #0 = { nounwind readnone }<br>
-attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx" }<br>
+attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }<br>
attributes #2 = { nounwind }<br>
<br>
!llvm.module.flags = !{!0}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-at.ll Wed Oct 18 11:07:07 2017<br>
@@ -30,4 +30,4 @@ b9:<br>
ret i32 %v10<br>
}<br>
<br>
-attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvxv60,-long-calls" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit-src.ll Wed Oct 18 11:07:07 2017<br>
@@ -32,4 +32,4 @@ b0:<br>
; Function Attrs: nounwind<br>
declare void @printf(i8* nocapture readonly, ...) local_unnamed_addr #0<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/bit-bitsplit.ll Wed Oct 18 11:07:07 2017<br>
@@ -14,4 +14,4 @@ entry:<br>
ret i32 %and2<br>
}<br>
<br>
-attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" }<br>
+attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/bit-ext-sat.ll Wed Oct 18 11:07:07 2017<br>
@@ -53,5 +53,5 @@ declare i32 @llvm.hexagon.A2.sath(i32) #<br>
declare i32 @llvm.hexagon.A2.satub(i32) #1<br>
declare i32 @llvm.hexagon.A2.satuh(i32) #1<br>
<br>
-attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }<br>
attributes #1 = { nounwind readnone }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll Wed Oct 18 11:07:07 2017<br>
@@ -19,5 +19,5 @@ b5:<br>
<br>
declare double @fabs(double) #1<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
-attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }<br>
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/bit-extract.ll Wed Oct 18 11:07:07 2017<br>
@@ -72,4 +72,4 @@ entry:<br>
ret i32 %bf.ashr<br>
}<br>
<br>
-attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-has.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-has.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-has.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/bit-has.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/bit-has.ll Wed Oct 18 11:07:07 2017<br>
@@ -60,5 +60,5 @@ b23:<br>
<br>
declare i32 @llvm.hexagon.A2.sath(i32) #1<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }<br>
attributes #1 = { nounwind readnone }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll Wed Oct 18 11:07:07 2017<br>
@@ -24,7 +24,7 @@ for.end:<br>
declare hidden i64 @danny(i32*, i32* nocapture readonly dereferenceable(4)) #1 align 2<br>
declare hidden i32 @sammy(i32* nocapture, i32) #0 align 2<br>
<br>
-attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
-attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
attributes #2 = { optsize }<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/bit-rie.ll Wed Oct 18 11:07:07 2017<br>
@@ -190,7 +190,7 @@ declare i64 @llvm.hexagon.M2.mpyd.ll.s1(<br>
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1<br>
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1<br>
<br>
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
attributes #1 = { argmemonly nounwind }<br>
attributes #2 = { nounwind readnone }<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll Wed Oct 18 11:07:07 2017<br>
@@ -24,4 +24,4 @@ entry:<br>
<br>
<br>
attributes #0 = { nounwind readnone }<br>
-attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }<br>
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/build-vector-shuffle.ll Wed Oct 18 11:07:07 2017<br>
@@ -17,5 +17,5 @@ entry:<br>
; Function Attrs: nounwind readnone<br>
declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }<br>
attributes #1 = { nounwind readnone }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/builtin-expect.ll Wed Oct 18 11:07:07 2017<br>
@@ -39,6 +39,6 @@ b14:<br>
<br>
declare i32 @bar(i32) local_unnamed_addr #0<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b,-long-calls" }<br>
<br>
!0 = !{!"branch_weights", i32 1, i32 2000}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/cfgopt-fall-through.ll Wed Oct 18 11:07:07 2017<br>
@@ -68,4 +68,4 @@ b19:<br>
unreachable<br>
}<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/cfi-offset.ll Wed Oct 18 11:07:07 2017<br>
@@ -39,5 +39,5 @@ declare i8* @__cxa_begin_catch(i8*)<br>
<br>
declare void @__cxa_end_catch()<br>
<br>
-attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
attributes #1 = { nounwind }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/common-gep-inbounds.ll Wed Oct 18 11:07:07 2017<br>
@@ -17,4 +17,4 @@ entry:<br>
ret i16 %a<br>
}<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/const-pool-tf.ll Wed Oct 18 11:07:07 2017<br>
@@ -1,6 +1,6 @@<br>
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic < %s | FileCheck %s<br>
+; RUN: opt -relocation-model pic -march=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic<br>
<br>
-; CHECK: @PCREL<br>
+; CHECK: jumpr<br>
<br>
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"<br>
target triple = "hexagon-unknown--elf"<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/convert-to-dot-old.ll Wed Oct 18 11:07:07 2017<br>
@@ -103,8 +103,8 @@ declare i32 @llvm.hexagon.S2.asr.r.r.sat<br>
declare i32 @llvm.hexagon.A2.aslh(i32) #2<br>
declare void @foo(i16*, i32*, i16*, i16 signext, i16 signext, i16 signext) local_unnamed_addr #3<br>
<br>
-attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }<br>
attributes #1 = { argmemonly nounwind }<br>
attributes #2 = { nounwind readnone }<br>
-attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }<br>
attributes #4 = { nounwind optsize }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll Wed Oct 18 11:07:07 2017<br>
@@ -14,4 +14,4 @@ entry:<br>
declare <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32>, <32 x i32>)<br>
declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>)<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll Wed Oct 18 11:07:07 2017<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc -O2 -march=hexagon < %s | FileCheck %s<br>
+; RUN: llc -O2 -march=hexagon -mcpu=hexagonv62< %s | FileCheck %s<br>
; CHECK: ParseFunc:<br>
; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]])<br>
; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]]<br>
@@ -126,6 +126,7 @@ sw.epilog:<br>
; Function Attrs: nounwind<br>
declare void @snprintf(i8* nocapture, i32, i8* nocapture readonly, ...) local_unnamed_addr #1<br>
<br>
-attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
-attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
attributes #2 = { nounwind }<br>
+<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll Wed Oct 18 11:07:07 2017<br>
@@ -82,7 +82,7 @@ declare i64 @llvm.hexagon.A2.addp(i64, i<br>
declare i64 @llvm.hexagon.A2.subp(<a href="https://maps.google.com/?q=i64,+i64)+%231&entry=gmail&source=g">i64, i64) #1</a><br>
declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1<br>
<br>
-attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }<br>
attributes #1 = { nounwind readnone }<br>
<br>
!0 = !{!1, !<a href="https://maps.google.com/?q=1,+i64&entry=gmail&source=g">1, i64</a> 0}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/early-if-vecpi.ll Wed Oct 18 11:07:07 2017<br>
@@ -66,4 +66,4 @@ for.end:<br>
ret void<br>
}<br>
<br>
-attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }<br>
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll Wed Oct 18 11:07:07 2017<br>
@@ -31,7 +31,7 @@ b5:<br>
declare <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1<br>
declare <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1>) #1<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }<br>
attributes #1 = { nounwind readnone }<br>
attributes #2 = { nounwind }<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/eliminate-pred-spill.ll Wed Oct 18 11:07:07 2017<br>
@@ -139,5 +139,5 @@ declare <64 x i32> @llvm.hexagon.V6.vmpy<br>
<br>
declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }<br>
attributes #1 = { nounwind readnone }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll Wed Oct 18 11:07:07 2017<br>
@@ -51,4 +51,4 @@ b23:<br>
ret void<br>
}<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll Wed Oct 18 11:07:07 2017<br>
@@ -42,4 +42,4 @@ b20:<br>
br label %b1<br>
}<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/expand-vselect-kill.ll Wed Oct 18 11:07:07 2017<br>
@@ -48,6 +48,6 @@ declare <32 x i32> @llvm.hexagon.V6.hi.1<br>
declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #2<br>
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #2<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }<br>
-attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }<br>
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }<br>
attributes #2 = { nounwind readnone }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef.ll Wed Oct 18 11:07:07 2017<br>
@@ -91,5 +91,5 @@ b22:<br>
<br>
attributes #0 = { nounwind }<br>
attributes #1 = { nounwind readnone }<br>
-attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvx-double" }<br>
+attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }<br>
attributes #3 = { nobuiltin nounwind }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll Wed Oct 18 11:07:07 2017<br>
@@ -210,7 +210,7 @@ b34:<br>
br i1 %v146, label %b33, label %b34<br>
}<br>
<br>
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" }<br>
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }<br>
attributes #1 = { nounwind readnone }<br>
attributes #2 = { nounwind }<br>
attributes #3 = { nobuiltin nounwind }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/find-loop-instr.ll Wed Oct 18 11:07:07 2017<br>
@@ -76,4 +76,4 @@ b21:<br>
br i1 %v23, label %b13, label %b10<br>
}<br>
<br>
-attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }<br>
+attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/fminmax.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/fminmax.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/fminmax.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/fminmax.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/fminmax.ll Wed Oct 18 11:07:07 2017<br>
@@ -22,6 +22,6 @@ entry:<br>
declare float @fminf(float, float) #0<br>
declare float @fmaxf(float, float) #0<br>
<br>
-attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
attributes #1 = { nounwind readnone }<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/frame-offset-overflow.ll Wed Oct 18 11:07:07 2017<br>
@@ -156,7 +156,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmpa<br>
declare <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32>, <16 x i32>, i32) #0<br>
<br>
attributes #0 = { nounwind readnone }<br>
-attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }<br>
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }<br>
<br>
!1 = !{!2, !<a href="https://maps.google.com/?q=2,+i64&entry=gmail&source=g">2, i64</a> 0}<br>
!2 = !{!"omnipotent char", !<a href="https://maps.google.com/?q=3,+i64&entry=gmail&source=g">3, i64</a> 0}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/hasfp-crash1.ll Wed Oct 18 11:07:07 2017<br>
@@ -18,7 +18,7 @@ entry:<br>
; Function Attrs: nounwind readnone speculatable<br>
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1<br>
<br>
-attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }<br>
attributes #1 = { nounwind readnone speculatable }<br>
<br>
!<a href="http://llvm.dbg.cu" rel="noreferrer" target="_blank">llvm.dbg.cu</a> = !{!0}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/hasfp-crash2.ll Wed Oct 18 11:07:07 2017<br>
@@ -19,7 +19,7 @@ entry:<br>
; Function Attrs: nounwind readnone speculatable<br>
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1<br>
<br>
-attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" }<br>
+attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"=",-hvx,-long-calls" }<br>
attributes #1 = { nounwind readnone speculatable }<br>
<br>
!<a href="http://llvm.dbg.cu" rel="noreferrer" target="_blank">llvm.dbg.cu</a> = !{!0}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll Wed Oct 18 11:07:07 2017<br>
@@ -73,7 +73,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmax<br>
; Function Attrs: nounwind readnone<br>
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1<br>
<br>
-attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
attributes #1 = { nounwind readnone }<br>
<br>
!llvm.ident = !{!0}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll?rev=316101&r1=316100&r2=316101&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll?rev=316101&r1=316100&r2=316101&view=diff</a><br>
===================================</blockquote></div>