[PATCH] D38689: [X86] Fix a bug with i386 subtarget in LowerCONCAT_VECTORSvXi1 func

[Uriel Korach via Phabricator via llvm-commits]

uriel.k created this revision.

Previously, did not consider i386 subtargets which led to a crash in legalization stage.

This is required before adding support for X86TESTM and X86TESTNM 
for also eliminating zeroing upper bits redundant instructions.


https://reviews.llvm.org/D38689

Files:
  lib/Target/X86/X86ISelLowering.cpp


Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -8028,7 +8028,8 @@
   // output register, mark it as legal and catch the pattern in instruction
   // selection to avoid emitting extra insturctions (for zeroing upper bits).
   if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op)) {
-    SDValue ZeroC = DAG.getConstant(0, dl, MVT::i64);
+    SDValue ZeroC = DAG.getConstant(0, dl,
+                                    Subtarget.is64Bit() ? MVT::i64 : MVT::i32);
     SDValue AllZeros = DAG.getSplatBuildVector(ResVT, dl, ZeroC);
     return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, AllZeros, Promoted,
                        ZeroC);


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