[llvm] r315184 - [X86] Regenerate fast-isel-select-pseudo-cmov.ll to prepare for D38609.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 8 10:54:50 PDT 2017
Author: ctopper
Date: Sun Oct 8 10:54:50 2017
New Revision: 315184
URL: http://llvm.org/viewvc/llvm-project?rev=315184&view=rev
Log:
[X86] Regenerate fast-isel-select-pseudo-cmov.ll to prepare for D38609.
Modified:
llvm/trunk/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll?rev=315184&r1=315183&r2=315184&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll Sun Oct 8 10:54:50 2017
@@ -1,136 +1,285 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mcpu=corei7-avx | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
define float @select_fcmp_one_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_one_f32
-; CHECK: ucomiss %xmm1, %xmm0
-; CHECK-NEXT: jne [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: movaps %xmm2, %xmm0
+; SSE-LABEL: select_fcmp_one_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: ucomiss %xmm1, %xmm0
+; SSE-NEXT: jne LBB0_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm3, %xmm2
+; SSE-NEXT: LBB0_2:
+; SSE-NEXT: movaps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_one_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: vucomiss %xmm1, %xmm0
+; AVX-NEXT: jne LBB0_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm3, %xmm2
+; AVX-NEXT: LBB0_2:
+; AVX-NEXT: vmovaps %xmm2, %xmm0
+; AVX-NEXT: retq
%1 = fcmp one float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_one_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_one_f64
-; CHECK: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: jne [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: movaps %xmm2, %xmm0
+; SSE-LABEL: select_fcmp_one_f64:
+; SSE: ## BB#0:
+; SSE-NEXT: ucomisd %xmm1, %xmm0
+; SSE-NEXT: jne LBB1_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm3, %xmm2
+; SSE-NEXT: LBB1_2:
+; SSE-NEXT: movaps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_one_f64:
+; AVX: ## BB#0:
+; AVX-NEXT: vucomisd %xmm1, %xmm0
+; AVX-NEXT: jne LBB1_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm3, %xmm2
+; AVX-NEXT: LBB1_2:
+; AVX-NEXT: vmovaps %xmm2, %xmm0
+; AVX-NEXT: retq
%1 = fcmp one double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_icmp_eq_f32(i64 %a, i64 %b, float %c, float %d) {
-; CHECK-LABEL: select_icmp_eq_f32
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: je [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: retq
+; SSE-LABEL: select_icmp_eq_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: cmpq %rsi, %rdi
+; SSE-NEXT: je LBB2_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: LBB2_2:
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_icmp_eq_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: cmpq %rsi, %rdi
+; AVX-NEXT: je LBB2_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: LBB2_2:
+; AVX-NEXT: retq
%1 = icmp eq i64 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_ne_f32(i64 %a, i64 %b, float %c, float %d) {
-; CHECK-LABEL: select_icmp_ne_f32
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: jne [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: retq
+; SSE-LABEL: select_icmp_ne_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: cmpq %rsi, %rdi
+; SSE-NEXT: jne LBB3_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: LBB3_2:
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_icmp_ne_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: cmpq %rsi, %rdi
+; AVX-NEXT: jne LBB3_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: LBB3_2:
+; AVX-NEXT: retq
%1 = icmp ne i64 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_ugt_f32(i64 %a, i64 %b, float %c, float %d) {
-; CHECK-LABEL: select_icmp_ugt_f32
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: ja [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: retq
+; SSE-LABEL: select_icmp_ugt_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: cmpq %rsi, %rdi
+; SSE-NEXT: ja LBB4_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: LBB4_2:
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_icmp_ugt_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: cmpq %rsi, %rdi
+; AVX-NEXT: ja LBB4_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: LBB4_2:
+; AVX-NEXT: retq
%1 = icmp ugt i64 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_uge_f32(i64 %a, i64 %b, float %c, float %d) {
-; CHECK-LABEL: select_icmp_uge_f32
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: jae [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: retq
+; SSE-LABEL: select_icmp_uge_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: cmpq %rsi, %rdi
+; SSE-NEXT: jae LBB5_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: LBB5_2:
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_icmp_uge_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: cmpq %rsi, %rdi
+; AVX-NEXT: jae LBB5_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: LBB5_2:
+; AVX-NEXT: retq
%1 = icmp uge i64 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_ult_f32(i64 %a, i64 %b, float %c, float %d) {
-; CHECK-LABEL: select_icmp_ult_f32
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: jb [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: retq
+; SSE-LABEL: select_icmp_ult_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: cmpq %rsi, %rdi
+; SSE-NEXT: jb LBB6_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: LBB6_2:
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_icmp_ult_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: cmpq %rsi, %rdi
+; AVX-NEXT: jb LBB6_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: LBB6_2:
+; AVX-NEXT: retq
%1 = icmp ult i64 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_ule_f32(i64 %a, i64 %b, float %c, float %d) {
-; CHECK-LABEL: select_icmp_ule_f32
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: jbe [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: retq
+; SSE-LABEL: select_icmp_ule_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: cmpq %rsi, %rdi
+; SSE-NEXT: jbe LBB7_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: LBB7_2:
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_icmp_ule_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: cmpq %rsi, %rdi
+; AVX-NEXT: jbe LBB7_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: LBB7_2:
+; AVX-NEXT: retq
%1 = icmp ule i64 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_sgt_f32(i64 %a, i64 %b, float %c, float %d) {
-; CHECK-LABEL: select_icmp_sgt_f32
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: jg [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: retq
+; SSE-LABEL: select_icmp_sgt_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: cmpq %rsi, %rdi
+; SSE-NEXT: jg LBB8_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: LBB8_2:
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_icmp_sgt_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: cmpq %rsi, %rdi
+; AVX-NEXT: jg LBB8_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: LBB8_2:
+; AVX-NEXT: retq
%1 = icmp sgt i64 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_sge_f32(i64 %a, i64 %b, float %c, float %d) {
-; CHECK-LABEL: select_icmp_sge_f32
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: jge [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: retq
+; SSE-LABEL: select_icmp_sge_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: cmpq %rsi, %rdi
+; SSE-NEXT: jge LBB9_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: LBB9_2:
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_icmp_sge_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: cmpq %rsi, %rdi
+; AVX-NEXT: jge LBB9_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: LBB9_2:
+; AVX-NEXT: retq
%1 = icmp sge i64 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_slt_f32(i64 %a, i64 %b, float %c, float %d) {
-; CHECK-LABEL: select_icmp_slt_f32
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: jl [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: retq
+; SSE-LABEL: select_icmp_slt_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: cmpq %rsi, %rdi
+; SSE-NEXT: jl LBB10_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: LBB10_2:
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_icmp_slt_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: cmpq %rsi, %rdi
+; AVX-NEXT: jl LBB10_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: LBB10_2:
+; AVX-NEXT: retq
%1 = icmp slt i64 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define float @select_icmp_sle_f32(i64 %a, i64 %b, float %c, float %d) {
-; CHECK-LABEL: select_icmp_sle_f32
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: jle [[BB:LBB[0-9]+_2]]
-; CHECK: [[BB]]
-; CHECK-NEXT: retq
+; SSE-LABEL: select_icmp_sle_f32:
+; SSE: ## BB#0:
+; SSE-NEXT: cmpq %rsi, %rdi
+; SSE-NEXT: jle LBB11_2
+; SSE-NEXT: ## BB#1:
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: LBB11_2:
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_icmp_sle_f32:
+; AVX: ## BB#0:
+; AVX-NEXT: cmpq %rsi, %rdi
+; AVX-NEXT: jle LBB11_2
+; AVX-NEXT: ## BB#1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: LBB11_2:
+; AVX-NEXT: retq
%1 = icmp sle i64 %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
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