[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection

[Haicheng Wu via Phabricator via llvm-commits]

haicheng updated this revision to Diff 118145.
haicheng marked 2 inline comments as done.
haicheng added a comment.

Add the support of "glue".


Repository:
  rL LLVM

https://reviews.llvm.org/D36104

Files:
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  test/CodeGen/AArch64/arm64-addr-type-promotion.ll
  test/CodeGen/AArch64/arm64-cse.ll
  test/CodeGen/AArch64/copy-zero-reg.ll
  test/CodeGen/AArch64/i128-fast-isel-fallback.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D36104.118145.patch
Type: text/x-patch
Size: 4921 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171008/078bb20b/attachment.bin>