[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection

[Geoff Berry via Phabricator via llvm-commits]

gberry added a comment.

Someone else should probably approve this since I wrote some of the code.



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Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2788
+    SDNode *CopyVal = Node->getOperand(2).getNode();
+    if (ConstantSDNode *CopyValConst = dyn_cast<ConstantSDNode>(CopyVal)) {
+      if (CopyValConst->isNullValue()) {
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Style nit: you can reduce the level of indentation below by inverting these if tests and doing an early break after each one.


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Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2794
+          break;
+        if (Node->getValueType(Node->getNumValues() - 1) == MVT::Glue)
+          break;
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This could use a comment explaining why it is being rejected.


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Comment at: test/CodeGen/AArch64/copy-zero-reg.ll:3
+
+; Verify no tiny block has only one mov wzr instruction
+define void @unroll_by_2(i32 %trip_count, i32* %p) {
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This description seems a little vague.  Can you spell out which block you don't want the mov to appear in?  Also, it seems like you might want a negative CHECK-NOT below to make sure there isn't another mov?


Repository:
  rL LLVM

https://reviews.llvm.org/D36104