[PATCH] D37687: [X86][LLVM]Expanding Supports lowerInterleaved{store|load}() in X86InterleavedAccess (VF64 stride 3)

[Zvi Rackover via Phabricator via llvm-commits]

zvi accepted this revision.
zvi added a comment.
This revision is now accepted and ready to land.

LGTM, and yes please add the assert



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Comment at: lib/Target/X86/X86InterleavedAccess.cpp:479
+
+  for (unsigned i = 32; i < VecElems; ++i)
+    Concat.push_back(i);
----------------
m_zuckerman wrote:
> zvi wrote:
> > If we reach this point, can VecElems be other than 64?
> In theory, yes, but I block all the other cases with the if supported stage so in practice, the answer is no. Do you prefer to add an assertion? 
I think we should since the path > 64 is not tested


https://reviews.llvm.org/D37687