[PATCH] D38181: [x86] swap order of srl (and X, C1), C2 when it saves size

[Sanjay Patel via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL314023: [x86] swap order of srl (and X, C1), C2 when it saves size (authored by spatel).

Changed prior to commit:
  https://reviews.llvm.org/D38181?vs=116354&id=116539#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D38181

Files:
  llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
  llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll
  llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
  llvm/trunk/test/CodeGen/X86/divide-by-constant.ll
  llvm/trunk/test/CodeGen/X86/known-bits.ll
  llvm/trunk/test/CodeGen/X86/live-out-reg-info.ll
  llvm/trunk/test/CodeGen/X86/test-shrink.ll
  llvm/trunk/test/CodeGen/X86/urem-i8-constant.ll
  llvm/trunk/test/CodeGen/X86/xor-icmp.ll

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