[PATCH] D38181: [x86] swap order of srl (and X, C1), C2 when it saves size

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:31785
+  // If the mask fits in a byte, then we know we can generate smaller and
+  // potentially better code by shifting first.
+  APInt MaskVal = AndC->getAPIntValue();
----------------
craig.topper wrote:
> spatel wrote:
> > craig.topper wrote:
> > > What about a larger than 32-bit and mask that would allow us to use a 32-bit and? Otherwise we use a movabsq to load the immediate.
> > Yes, that's a limitation. I'll have to check if that causes regressions for the other patterns. Ok to make that a TODO in this patch?
> TODO is fine.
http://llvm.org/viewvc/llvm-project?view=revision&revision=314064


https://reviews.llvm.org/D38181