[PATCH] D38175: [ARM] Make sure assembler rejects PC as an operand for VMOV.F16

[Andre Vieira via Phabricator via llvm-commits]

avieira created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

Hi,

This restricts the general purpose register of vmov.f16 such that the assembler does not accept PC as a valid operand.

Is this OK?

Cheers,
Andre


https://reviews.llvm.org/D38175

Files:
  lib/Target/ARM/ARMInstrVFP.td
  test/MC/ARM/fullfp16.s


Index: test/MC/ARM/fullfp16.s
===================================================================
--- test/MC/ARM/fullfp16.s
+++ test/MC/ARM/fullfp16.s
@@ -1,5 +1,7 @@
-@ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16 -show-encoding < %s | FileCheck %s --check-prefix=ARM
-@ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+thumb-mode -show-encoding < %s | FileCheck %s --check-prefix=THUMB
+@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16 -show-encoding < %s 2> %t | FileCheck %s --check-prefix=ARM
+@ RUN: FileCheck --check-prefix=ERROR-ARM < %t %s
+@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+thumb-mode -show-encoding < %s 2> %t | FileCheck %s --check-prefix=THUMB
+@ RUN: FileCheck --check-prefix=ERROR-THUMB < %t %s
 
          vadd.f16  s0, s1, s0
 @ ARM:    vadd.f16 s0, s1, s0        @ encoding: [0x80,0x09,0x30,0xee]
@@ -255,3 +257,10 @@
 @ ARM:   vmov.f16        r3, s4          @ encoding: [0x10,0x39,0x12,0xee]
 @ THUMB: vmov.f16       s1, r2          @ encoding: [0x00,0xee,0x90,0x29]
 @ THUMB: vmov.f16       r3, s4          @ encoding: [0x12,0xee,0x10,0x39]
+
+  vmov.f16 pc, r0
+@ ERROR-ARM: invalid operand for instruction
+@ ERROR-THUMB: invalid operand for instruction
+  vmov.f16 r0, pc
+@ ERROR-ARM: invalid operand for instruction
+@ ERROR-THUMB: invalid operand for instruction
Index: lib/Target/ARM/ARMInstrVFP.td
===================================================================
--- lib/Target/ARM/ARMInstrVFP.td
+++ lib/Target/ARM/ARMInstrVFP.td
@@ -1180,7 +1180,7 @@
 
 // Move H->R, clearing top 16 bits
 def VMOVRH : AVConv2I<0b11100001, 0b1001,
-                      (outs GPR:$Rt), (ins SPR:$Sn),
+                      (outs GPRnopc:$Rt), (ins SPR:$Sn),
                       IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn",
                       []>,
              Requires<[HasFullFP16]>,
@@ -1200,7 +1200,7 @@
 
 // Move R->H, clearing top 16 bits
 def VMOVHR : AVConv4I<0b11100000, 0b1001,
-                      (outs SPR:$Sn), (ins GPR:$Rt),
+                      (outs SPR:$Sn), (ins GPRnopc:$Rt),
                       IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt",
                       []>,
              Requires<[HasFullFP16]>,


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