[PATCH] D37683: [mips] Correcting operand range for DINSM instruction

[Aleksandar Beserminji via Phabricator via llvm-commits]

abeserminji updated this revision to Diff 114814.
abeserminji marked 2 inline comments as done.
abeserminji added a comment.

Comment resolved.


Repository:
  rL LLVM

https://reviews.llvm.org/D37683

Files:
  lib/Target/Mips/Mips64InstrInfo.td
  test/MC/Mips/mips64r2/valid.s
  test/MC/Mips/mips64r6/valid.s


Index: test/MC/Mips/mips64r6/valid.s
===================================================================
--- test/MC/Mips/mips64r6/valid.s
+++ test/MC/Mips/mips64r6/valid.s
@@ -114,6 +114,7 @@
         ddivu   $2,$3,$4         # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
         di                       # CHECK: di               # encoding: [0x41,0x60,0x60,0x00]
         di      $s8              # CHECK: di  $fp          # encoding: [0x41,0x7e,0x60,0x00]
+        dinsm   $2,$3,4,34       # CHECK: dinsm $2, $3, 4, 34    # encoding: [0x7c,0x62,0x29,0x05]
         div     $2,$3,$4         # CHECK: div $2, $3, $4   # encoding: [0x00,0x64,0x10,0x9a]
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         dlsa    $2, $3, $4, 3    # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x95]
Index: test/MC/Mips/mips64r2/valid.s
===================================================================
--- test/MC/Mips/mips64r2/valid.s
+++ test/MC/Mips/mips64r2/valid.s
@@ -106,6 +106,7 @@
         deret
         di        $s8                  # CHECK: di  $fp        # encoding: [0x41,0x7e,0x60,0x00]
         di                             # CHECK: di             # encoding: [0x41,0x60,0x60,0x00]
+        dinsm     $2,$3,4,34           # CHECK: dinsm $2, $3, 4, 34    # encoding: [0x7c,0x62,0x29,0x05]
         ddiv      $zero,$k0,$s3
         ddivu     $zero,$s0,$s1
         div       $zero,$25,$11
Index: lib/Target/Mips/Mips64InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips64InstrInfo.td
+++ lib/Target/Mips/Mips64InstrInfo.td
@@ -331,7 +331,7 @@
              EXT_FM<7>, ISA_MIPS64R2;
   def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1>,
               EXT_FM<6>, ISA_MIPS64R2;
-  def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm5_inssize_plus1>,
+  def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>,
               EXT_FM<5>, ISA_MIPS64R2;
 }
 


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