[PATCH] D37665: [SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat vectors

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

This teach simplifyDemandedBits to handle constant splat vector shifts.

This required changing all the uses of getZExtValue to getLimitedValue since we can't rely on legalization using getShiftAmountTy for the shift amount.

I believe there may have been a bug in the ((X << C1) >>u ShAmt) handling where we didn't check if the inner shift was too large. I've fixed that here, but maybe I should split that out.

I had to add new patterns to ARM because the zext/sext the patterns were trying to look for got turned into an any_extend with this patch. Happy to split that out too, but not sure how to test without this change.


https://reviews.llvm.org/D37665

Files:
  include/llvm/CodeGen/SelectionDAGNodes.h
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  lib/Target/ARM/ARMInstrNEON.td
  test/CodeGen/X86/combine-shl.ll
  test/CodeGen/X86/not-and-simplify.ll
  test/CodeGen/X86/sse2-vector-shifts.ll
  test/CodeGen/X86/vector-blend.ll
  test/CodeGen/X86/vector-rotate-128.ll
  test/CodeGen/X86/vector-rotate-256.ll
  test/CodeGen/X86/widen_cast-4.ll

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