[PATCH] D29933: [RISCV 11/n] Initial codegen support for ALU operations

[Krzysztof Parzyszek via Phabricator via llvm-commits]

kparzysz added inline comments.


================
Comment at: lib/Target/RISCV/RISCVISelDAGToDAG.cpp:49
+  // If we have a custom node, we have already selected
+  if (Node->isMachineOpcode()) {
+    DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
----------------
I'm curious---do you expect Select to be called with a machine node?  Normally that should not happen.


================
Comment at: lib/Target/RISCV/RISCVRegisterInfo.cpp:49
+  Reserved.set(RISCV::X8_32); // fp
+  return Reserved;
+}
----------------
You could use `markSuperRegs` to make sure that all super-registers of a reserved register are also marked as reserved.  It may (or may not) make sense to add `assert(checkAllSuperRegsMarked(Reserved))` too.



https://reviews.llvm.org/D29933