[PATCH] D37514: [PowerPC] DAGCombine for better exploitation of rotate-and-mask instruction

[Hiroshi Inoue via Phabricator via llvm-commits]

inouehrs created this revision.
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This patch add a PPC-specific DAGcombine, which tries to increase the opportunity to generate rotate-and-mask instructions (e.g. rlwinm) in PPCDAGToDAGISel::tryBitPermutation by reordering ZEXT and ANDI.
Since tryBitPermutation stops analyzing nodes if it hits a ZEXT node while traversing SDNodes, we want to avoid ZEXT between two nodes that can be folded into a rotate-and-mask instruction.

For example, we modify these nodes

        t9: i32 = add t7, Constant:i32<1>
      t11: i32 = and t9, Constant:i32<255>
    t12: i64 = zero_extend t11
  t14: i64 = shl t12, Constant:i64<2>

into

        t9: i32 = add t7, Constant:i32<1>
      t25: i64 = any_extend t9
    t27: i64 = and t25, Constant:i64<255>
  t14: i64 = shl t12, Constant:i64<2>

to fold t27 and t14 into a rotate-and-mask instruction.
Such case often happens in array accesses with logical AND operation in an index, e.g. array[i & 0xFF];

We modify nodes only if the parent of ZEXT node (t14 in above example) has a logical opcode supported in tryBitPermutation and the first operand of AND node (t9 in example) is not a supported logical opcode.


https://reviews.llvm.org/D37514

Files:
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.h
  test/CodeGen/PowerPC/zext-bitperm.ll

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