[PATCH] D37211: [PowerPC] eliminate redundant compare instruction

[Hiroshi Inoue via Phabricator via llvm-commits]

inouehrs marked 2 inline comments as done.
inouehrs added inline comments.


================
Comment at: lib/Target/PowerPC/PPCMIPeephole.cpp:436
+        BII != BB.instr_end() &&
+        (*BII).getOpcode() == PPC::BCC &&
+        (*BII).getOperand(1).isReg()) {
----------------
hfinkel wrote:
> I think you can also handle BCCLR and BCA. BCA doesn't come up much, but we can have BCCLR in loops where this might be helpful.
I added PPC::BCCLR as a opcode to optimize. Also I added a test case that generates bgelr.
(In many case, BCCLR is not used at the time of PPC MI Peephole since BCCLR is typically generated afterward at If Converter.)


================
Comment at: lib/Target/PowerPC/PPCMIPeephole.cpp:527
+      unsigned Cmp2Operand2 = CMPI2->getOperand(2).getReg();
+      if (Cmp1Operand1 == Cmp2Operand1 && Cmp1Operand2 == Cmp2Operand2) {
+        // Same pair of registers in the same order; ready to merge as is.
----------------
hfinkel wrote:
> I think that you can run into trouble if these are physical registers (similar to the problem recently uncovered with PPCBranchCoalescing. This will work for virtual registers, but not for physical registers, unless MRI->isConstantPhysReg or TRI->isCallerPreservedPhysReg is true, or you scan the instructions in the first BB to make sure that nothing changes the register.
I added checks of physical registers in `eligibleForCompareElimination`. 


================
Comment at: lib/Target/PowerPC/PPCMIPeephole.cpp:537
+        switch (PredCond) {
+        case PPC::PRED_LT:
+          NewPredicate2 = (unsigned)PPC::getPredicate(PPC::PRED_GT, PredHint);
----------------
hfinkel wrote:
> I don't think you need this switch, but can use:
> 
>   NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred);
I modified with getSwappedPredicate.


https://reviews.llvm.org/D37211